Philips TDA8950 User Manual

TDA8950

2 × 150 W class-D power ampliﬁer

Rev. 01 — 9 September 2008 Preliminary data sheet

1. General description

The TDA8950 is a high efﬁciency class-D audio powerampliﬁer. The typical output power is 2 × 150 W with a speaker load impedance of 4 Ω.

The TDA8950 is available in the HSOP24 power package and DBS23P power package. The ampliﬁer operates over a wide supply voltage range from ±12.5 V to ±40 V and consumes a low quiescent current.

2. Features

n Pin compatible with TDA8920B for both HSOP24 and DBS23P packages n Symmetrical high operating supply voltage range from ±12.5 V to ±40 V n Stereo full differential inputs, usableas stereo Single-Ended (SE) or mono Bridge-Tied

Load (BTL) ampliﬁer

n High output power at typical applications:

u SE 2 × 150 W, RL=4Ω (VP = ±37 V) u SE 2 × 170 W, RL=4Ω (VP = ±39 V) u SE 2 × 100 W, RL=6Ω (VP = ±37 V)

u BTL 1 × 300 W, RL=8Ω (VP = ±37 V) n Low noise in BTL due to BD-modulation n Smooth pop noise-free start-up and switch down n Zero dead time Pulse Width Modulation (PWM) output switching n Fixed frequency n Internal or external clock switching frequency n High efﬁciency n Low quiescent current n Advanced protection strategy: voltage protection and output current limiting n Thermal foldback n Fixed gain of 30 dB in SE and 36 dB in BTL n Full short-circuit proof across load

3. Applications

n DVD n Mini and micro receiver n Home Theater In A Box (HTIAB) system n High power speaker system

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4. Quick reference data

Table 1. Quick reference data

Symbol Parameter Conditions Min Typ Max Unit

General, V

P(ovp)

q(tot)

Stereo single-ended conﬁguration

Mono bridge-tied load conﬁguration

= ±35 V

supply voltage ±12.5 ±35 ±40 V overvoltage protection

supply voltage total quiescent current Operating mode; no load;

output power RL=4Ω; THD=10%;

output power RL=8Ω; THD=10%;

2 × 150 W class-D power ampliﬁer

non-operating; VDD− V

no ﬁlter; no RC-snubber network connected

= ±39 V

=4Ω; THD=10%;

= ±37 V

=6Ω; THD=10%;

= ±37 V

TDA8950

85 - 90 V

- 5075mA

- 170 - W

- 150 - W

- 100 - W

- 300 - W

5. Ordering information

Table 2. Ordering information

Type number Package

Name Description Version

TDA8950J DBS23P plastic DIL-bent-SIL power package; 23 leads (straight lead length 3.2 mm) SOT411-1 TDA8950TH HSOP24 plastic, heatsink small outline package; 24 leads; low stand-off height SOT566-3

Preliminary data sheet Rev. 01 — 9 September 2008 2 of 39

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6. Block diagram

TDA8950

2 × 150 W class-D power ampliﬁer

VDDA

3 (20)

9 (3)

IN1M

IN1P

n.c.

OSC

MODE

SGND

IN2P

IN2M

8 (2)

11 (5)

7 (1)

6 (23)

2 (19)

5 (22)

4 (21)

INPUT

STAGE

mute

MODE

mute

INPUT

STAGE

1 (18)

VSSA

The pin numbers in parenthesis refer to type number TDA8950J.

Fig 1. Block diagram

n.c.

10 (4)

OSCILLATOR

12 (6)

n.c.

PWM

MODULATOR

STABI

MANAGER

PWM

MODULATOR

PROTSTABI

SWITCH1

TEMPERATURE SENSOR

CURRENT PROTECTION VOLTAGE PROTECTION

SWITCH2

19 (-)24 (17)

VSSD n.c.

CONTROL

AND

HANDSHAKE

CONTROL

AND

HANDSHAKE

VDDP2

23 (16)13 (7)18 (12) 14 (8)

DRIVER

HIGH

DRIVER

LOW

TDA8950TH (TDA8950J)

DRIVER

HIGH

DRIVER

LOW

17 (11)

VDDP1

16 (10)

SSP1

DDP2

22 (15)

21 (14)

20 (13)

VSSP2VSSP1

15 (9)

BOOT1

OUT1

BOOT2

OUT2

001aah653

Preliminary data sheet Rev. 01 — 9 September 2008 3 of 39

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7. Pinning information

7.1 Pinning

VSSD VSSA

VDDP2 SGND

BOOT2 VDDA

OUT2 IN2M

VSSP2 IN2P

n.c. MODE

STABI OSC

VSSP1 IN1P

OUT1 IN1M

BOOT1 n.c.

VDDP1 n.c.

PROT n.c.

TDA8950TH

TDA8950

2 × 150 W class-D power ampliﬁer

OSC

IN1P

IN1M

n.c.

PROT

OUT1

STABI

OUT2

VSSD

VSSA

SGND

VDDA

IN2M

IN2P

MODE

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

TDA8950J

VDDP1 BOOT1

VSSP1

1 2 3 4 5 6 7 8

9 10 11 12

VSSP2

BOOT2 VDDP2

001aah654

001aah655

Fig 2. Pin conﬁguration TDA8950TH Fig 3. Pin conﬁguration TDA8950J

Preliminary data sheet Rev. 01 — 9 September 2008 4 of 39

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7.2 Pin description

Table 3. Pin description

Symbol Pin Description

VSSA 1 18 negative analog supply voltage SGND 2 19 signal ground VDDA 3 20 positive analog supply voltage IN2M 4 21 negative audio input for channel 2 IN2P 5 22 positive audio input for channel 2 MODE 6 23 mode selection input: Standby,Mute or Operating

OSC 7 1 oscillator frequency adjustment or tracking input IN1P 8 2 positive audio input for channel 1 IN1M 9 3 negative audio input for channel 1 n.c. 10 4 not connected n.c. 11 5 not connected n.c. 12 6 not connected PROT 13 7 decoupling capacitor for protection (OCP) VDDP1 14 8 positive power supply voltage for channel 1 BOOT1 15 9 bootstrap capacitor for channel 1 OUT1 16 10 PWM output from channel 1 VSSP1 17 11 negative power supply voltage for channel 1 STABI 18 12 decoupling of internal stabilizer for logic supply n.c. 19 - not connected VSSP2 20 13 negative power supply voltage for channel 2 OUT2 21 14 PWM output from channel 2 BOOT2 22 15 bootstrap capacitor for channel 2 VDDP2 23 16 positive power supply voltage for channel 2 VSSD 24 17 negative digital supply voltage

TDA8950

2 × 150 W class-D power ampliﬁer

TDA8950TH TDA8950J

mode

8. Functional description

8.1 General

The TDA8950 is a two-channel audio power ampliﬁer using class-D technology. The audio input signal is converted into a digital pulse width modulated signal via an

analog input stage and PWM modulator, see Figure 1. To enable the output power transistors to be driven, this digital PWM signal is applied to a control and handshake block and driver circuits for both the high side and low side. In this way a level shift is performed from the low power digital PWM signal (at logic levels) to a high power PWM signal that switches between the main supply lines.

A 2nd-order low-pass ﬁlter converts the PWM signal to an analog audio signal across the loudspeakers.

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The TDA8950 one-chip class-D ampliﬁer contains high power switches, drivers, timing and handshaking between the power switches and some control logic. Also an advanced protection strategy is implemented which contains several voltage protections, temperature protections and a maximum current protection to secure maximum system robustness.

The two audio channels of the TDA8950 each contain a PWM modulator, an analog feedback loop and a differential input stage. It also contains circuits common to both channels such as the oscillator, all reference sources, the mode interface and a digital timing manager.

The TDA8950 contains two independent ampliﬁer channels with high output power, high efﬁciency, low distortion and low quiescent current. The ampliﬁer channels can be connected in the following conﬁgurations:

• Mono Bridge-Tied Load (BTL) ampliﬁer

• Stereo Single-Ended (SE) ampliﬁers

The ampliﬁer system can be switched to one of three operating modes by pin MODE:

TDA8950

2 × 150 W class-D power ampliﬁer

• Standby mode; with a very low supply current

• Mute mode; the ampliﬁers are operational, but the audio signal at the output is

suppressed by disabling the VI-converter input stages

• Operating mode; the ampliﬁers are fully operational

To ensure pop noise-free start-up, the DC output offset voltage is applied gradually to the output at a level between Mute mode and Operating mode levels. The bias current setting of the VI converters is related to the voltage on pin MODE; in Mute mode the bias current setting of the VI converters is zero (VI converters disabled) and in Operating mode the bias current is at maximum. The time constant required to apply the DC output offset voltage gradually between Mute and Operating mode levels can be generated via an RC-network on pin MODE. An example of a switching circuit for driving pin MODE is illustrated in Figure 4. If the capacitor C is left out of the application, the voltage on pin MODE will be applied with a much smaller time-constant, which might result in audible pop noises during start-up (depending on DC output offset voltage and loudspeaker used).

5 V

standby/

mute

MODE pin

mute/on

SGND

001aab172

Fig 4. Example of mode selection circuit

Preliminary data sheet Rev. 01 — 9 September 2008 6 of 39

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In order to fully charge the coupling capacitors at the inputs, the ampliﬁer will remain automatically in the Mute mode before switching to the Operating mode. A complete overview of the start-up timing is given in Figure 5.

MODE

TDA8950

2 × 150 W class-D power ampliﬁer

audio output

(1)

modulated PWM

50 %

duty cycle

2.2 V < V

> 4.2 V

< 3 V

MODE

0 V (SGND)

MODE

> 4.2 V

< 3 V

MODE

standby

mute

100 ms

50 %

duty cycle

mute

(1)

50 ms

operating

> 350 ms

audio output

modulated PWM

operating

time

0 V (SGND)

standby

100 ms

50 ms

> 350 ms

time

001aah657

(1) First1⁄4 pulse down.

Upper diagram: When switching from standby to mute, there is a delay of approximately 100 ms before the output starts switching. The audio signal is available after V

has been set to

MODE

operating, but not earlier than 150 ms after switching to mute. For pop noise-free start-up it is recommended that the time constant applied to pin MODE is at least 350 ms for the transition between mute and operating.

Lower diagram: When switchingdirectlyfromstandbyto operating, there is a ﬁrst delay of 100 ms before the outputs starts switching. The audio signal is available after a second delay of 50 ms. For pop noise-free start-up it is recommended that the time constant applied to pin MODE is at least 500 ms for the transition between standby and operating.

Fig 5. Timing on mode selection input

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8.2 Pulse width modulation frequency

The output signal of the ampliﬁer is a PWM signal with a carrier frequency that typically lies between 300 kHz and 400 kHz. Using a 2nd-order LC demodulation ﬁlter in the application results in an analog audio signal across the loudspeaker. The carrier frequency is determined by an external resistor R pin VSSA. An optimal setting for the carrier frequency is between 300 kHz and 400 kHz.

Using an external resistor of 30 kΩ on pin OSC, the carrier frequency is set to 345 kHz. For more details see Table 8.

If two or more class-D ampliﬁers are used in the same audio application, it is recommended that all devices operate at the same switching frequency by using an external clock circuit.

Due to an internal clock divider:

• The external applied clock frequency must have the double frequency of the output

• The duty cycle of the external clock is not critical for product performance.

PWM frequency.

TDA8950

2 × 150 W class-D power ampliﬁer

, connected between pin OSC and

OSC

8.3 Protections

The following protections are included in TDA8950:

• Thermal protections:

– Thermal FoldBack (TFB) – OverTemperature Protection (OTP)

• OverCurrent Protection (OCP, diagnostic via pin PROT)

• Window Protection (WP)

• Supply voltage protections:

– UnderVoltage Protection (UVP) – OverVoltage Protection (OVP) – UnBalance Protection (UBP)

The reaction of the device to the different fault conditions differs per protection.

8.3.1 Thermal protection

In the TDA8950 an advanced thermal protection strategy is implemented. It consists of a TFB function that gradually reduces the out put power within a certain temperature range. When temperature is still rising an OTP is implemented which shuts down the device completely.

8.3.1.1 Thermal FoldBack (TFB)

If the junction temperature Tj exceeds a deﬁned threshold value, the gain is gradually reduced. This will result in a smaller output signal and less dissipation. Eventually the temperature will stabilize.

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TDA8950

2 × 150 W class-D power ampliﬁer

TFB is speciﬁed at the temperature value T reduced with 6 dB. The range of the TFB is:

act(th_fold)

For the TDA8950 the value of T

− 5 °C < T

act(th_fold)

< T

act(th_prot)

act(th_fold)

8.3.1.2 OverTemperature Protection (OTP)

If, despite the TFB function, the junction temperature Tj of the TDA8950 continues rising and exceeds the threshold T

act(th_prot)

ampliﬁer resumes switching approximately 100 ms after the temperature drops below T

act(th_prot)

In Figure 6 the thermal behavior is visualized.

Gain

(dB)

30 dB

24 dB

0 dB

act(th_fold)

12 3

act(th_fold)

where the closed loop voltage gain is

is about +153 °C. For more details see: Table 7.

the ampliﬁer will shutdown immediately. The

(°C) T

− 5°C)

act(th_fold)

act(th_prot)

001aah656

(1) Duty cycle of PWM output modulated according audio input signal. (2) Duty cycle of PWM output reduced due to TFB. (3) Ampliﬁer is switched off due to OTP.

Fig 6. Behavior of TFB and OTP

8.3.2 OverCurrent Protection (OCP)

If a short-circuit is applied to one of the demodulated outputs of the ampliﬁer, the OCP will detect this. If the output current exceeds the maximum of 9.2 A, it is automatically limited to its maximum value by the OCP protection circuit. The ampliﬁer outputs remain switching (the ampliﬁer is NOT shut-down completely). If the active current limiting continues longer than time τ, the TDA8950 shuts down. Activation of current limiting and the triggering of the OCP are observed at pin PROT.

The ampliﬁer can distinguish between an impedance drop of the loudspeaker and a low-ohmic short-circuit across the load. In the TDA8950 the impedance threshold (Zth) depends on the supply voltage used.

When a short-circuit is made across the load, causing the impedance to drop below the threshold level (<Zth), the ampliﬁer is switched off completely and, after a time of 100 ms, it will try to restart. If the short-circuit condition is still present after this time, the cycle will be repeated. The average dissipation will be low because of this low duty cycle.

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Should there be an impedance drop (e.g. due to dynamic behavior of the loudspeaker) the same protection will be activated. The maximum output current will again be limited to

9.2 A, but the ampliﬁer will not switch-off completely (thus preventing audio holes from occurring).

The result will be a clipping output signal. See Section 13.7 for more information on this maximum output current limiting feature.

8.3.3 Window Protection (WP)

The WP checks the conditions at the output terminals of the power stage and is activated:

• During the start-up sequence, when pin MODE is switched from standby to mute. In

• When the ampliﬁer is completely shut-down due to activation of the OCP because a

TDA8950

2 × 150 W class-D power ampliﬁer

the event of a short-circuit at one of the output terminals to pin VDDPn or pin VSSPn the start-up procedure is interrupted and the TDA8950 waits until the short-circuit to the supply lines has been removed. Because the test is done before enabling the power stages, no large currents will ﬂow in an event of short-circuit.

short-circuit to one of the supply lines is made, then during restart (after 100 ms) the WP will be activated. As a result the ampliﬁer will not start-up until the short-circuit to the supply lines is removed.

8.3.4 Supply voltage protections

If the supply voltage drops below minimum supply voltage, the UVP circuit is activated and the system will shutdown correctly. If the internal clock is used, this switch-off will be silent and without pop noise. When the supply voltage rises above the threshold level, the system is restarted again after 100 ms.

If the supply voltage exceeds maximum supply voltage, the OVP circuit is activated and the power stages will shutdown. When the supply voltage drops below the threshold level, the system is restarted again after 100 ms.

An additional UBP circuit compares the positive analog (voltage on pin VDDA) and the negative analog (voltage on pin VSSA) supply voltage and is triggered if the voltage difference exceeds a factor of two.

When the supply voltage difference drops below the threshold level, the system is restarted again after 100 ms.

Example: With a symmetrical supply of ±30 V, the protection circuit will be triggered if the unbalance exceeds approximately 15 V. See Section 13.7.

In Table 4 an overview is given of all protections and their respective effects on the output signal.

Preliminary data sheet Rev. 01 — 9 September 2008 10 of 39

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Table 4. Overview of TDA8950 protections

Protection name Complete

TFB OTP Y N Y N OCP Y WP N UVPYNYN OVP Y N Y N UBPYNYN

[1] Ampliﬁer gain will depend on junction temperature and heatsink size. [2] Only complete shutdown of ampliﬁer if short-circuit impedance is below threshold of 1 Ω. In all other cases

[3] Fault condition detected during (every) transition between standby-to-mute and during restart after

8.4 Differential audio inputs

Restart directly Restart after

shutdown

[1]

current limiting results in clipping of the output signal.

activation of OCP (short-circuit to one of the supply lines).

NNNN

[2] [3]

[2]

N YNN

TDA8950

2 × 150 W class-D power ampliﬁer

Pin PROT

100 ms

[2]

detection

Fora high common mode rejection ratio and a maximum of ﬂexibility in the application, the audio inputs are fully differential.

There are two possibilities:

• For stereo operation it is advised to use the inputs in anti phase and also to connect

the speakers in anti phase (to avoid acoustical phase differences). This construction has several advantages:

– The peak current in the power supply is minimized – The supply pumping effect is minimized, especially at low audio frequencies

• For mono BTL operation it is required that the inputs are connected in anti parallel.

The output of one of the channels is inverted and the speaker load is now connected between the two outputs of the TDA8950. In principle the output power to the speaker can be signiﬁcantly boosted to two times the output power in single ended stereo.

The input conﬁguration for a mono BTL application is illustrated in Figure 7.

IN1P

IN1M

IN2P

IN2M

OUT1

SGND

OUT2

power stage

mbl466

Fig 7. Input conﬁguration for mono BTL application

Preliminary data sheet Rev. 01 — 9 September 2008 11 of 39

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9. Limiting values

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

ORM

stg

amb

MODE

OSC

PROT

esd

q(tot)

TDA8950

2 × 150 W class-D power ampliﬁer

supply voltage non-operating mode; VDD− V repetitive peak

maximum output current limiting 9.2 - A

output current storage temperature −55 +150 °C ambient temperature −40 +85 °C junction temperature - 150 °C voltage on pin

referenced to SGND 0 6 V

MODE voltage on pin OSC 0 SGND

input voltage referenced to SGND; pin IN1P; IN1M;

IN2P and IN2M voltage on pin PROT referenced to voltage on pin VSSD 0 12 V electrostatic

discharge voltage

Human Body Model (HBM);

pin VSSP1 with respect to other pins

HBM; all other pins −2000 +2000 V

Machine Model (MM); all pins −200 +200 V

Charged Device Model (CDM) −500 +500 V total quiescent

current

Operating mode; no load; no ﬁlter; no

RC-snubber network connected

-90V

+ 6

−5+5V

−1800 +1800 V

-75mA

10. Thermal characteristics

Table 6. Thermal characteristics

Symbol Parameter Conditions Typ Unit

th(j-a)

th(j-c)

Preliminary data sheet Rev. 01 — 9 September 2008 12 of 39

thermal resistance from junction to ambient in free air 40 K/W thermal resistance from junction to case 1.1 K/W

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