Philips TDA8950 User Manual

TDA8950

2 × 150 W class-D power ampliﬁer

Rev. 01 — 9 September 2008 Preliminary data sheet

1. General description

The TDA8950 is a high efﬁciency class-D audio powerampliﬁer. The typical output power is 2 × 150 W with a speaker load impedance of 4 Ω.

The TDA8950 is available in the HSOP24 power package and DBS23P power package. The ampliﬁer operates over a wide supply voltage range from ±12.5 V to ±40 V and consumes a low quiescent current.

2. Features

n Pin compatible with TDA8920B for both HSOP24 and DBS23P packages n Symmetrical high operating supply voltage range from ±12.5 V to ±40 V n Stereo full differential inputs, usableas stereo Single-Ended (SE) or mono Bridge-Tied

Load (BTL) ampliﬁer

n High output power at typical applications:

u SE 2 × 150 W, RL=4Ω (VP = ±37 V) u SE 2 × 170 W, RL=4Ω (VP = ±39 V) u SE 2 × 100 W, RL=6Ω (VP = ±37 V)

u BTL 1 × 300 W, RL=8Ω (VP = ±37 V) n Low noise in BTL due to BD-modulation n Smooth pop noise-free start-up and switch down n Zero dead time Pulse Width Modulation (PWM) output switching n Fixed frequency n Internal or external clock switching frequency n High efﬁciency n Low quiescent current n Advanced protection strategy: voltage protection and output current limiting n Thermal foldback n Fixed gain of 30 dB in SE and 36 dB in BTL n Full short-circuit proof across load

3. Applications

n DVD n Mini and micro receiver n Home Theater In A Box (HTIAB) system n High power speaker system

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4. Quick reference data

Table 1. Quick reference data

Symbol Parameter Conditions Min Typ Max Unit

General, V

P(ovp)

q(tot)

Stereo single-ended conﬁguration

Mono bridge-tied load conﬁguration

= ±35 V

supply voltage ±12.5 ±35 ±40 V overvoltage protection

supply voltage total quiescent current Operating mode; no load;

output power RL=4Ω; THD=10%;

output power RL=8Ω; THD=10%;

2 × 150 W class-D power ampliﬁer

non-operating; VDD− V

no ﬁlter; no RC-snubber network connected

= ±39 V

=4Ω; THD=10%;

= ±37 V

=6Ω; THD=10%;

= ±37 V

TDA8950

85 - 90 V

- 5075mA

- 170 - W

- 150 - W

- 100 - W

- 300 - W

5. Ordering information

Table 2. Ordering information

Type number Package

Name Description Version

TDA8950J DBS23P plastic DIL-bent-SIL power package; 23 leads (straight lead length 3.2 mm) SOT411-1 TDA8950TH HSOP24 plastic, heatsink small outline package; 24 leads; low stand-off height SOT566-3

Preliminary data sheet Rev. 01 — 9 September 2008 2 of 39

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6. Block diagram

TDA8950

2 × 150 W class-D power ampliﬁer

VDDA

3 (20)

9 (3)

IN1M

IN1P

n.c.

OSC

MODE

SGND

IN2P

IN2M

8 (2)

11 (5)

7 (1)

6 (23)

2 (19)

5 (22)

4 (21)

INPUT

STAGE

mute

MODE

mute

INPUT

STAGE

1 (18)

VSSA

The pin numbers in parenthesis refer to type number TDA8950J.

Fig 1. Block diagram

n.c.

10 (4)

OSCILLATOR

12 (6)

n.c.

PWM

MODULATOR

STABI

MANAGER

PWM

MODULATOR

PROTSTABI

SWITCH1

TEMPERATURE SENSOR

CURRENT PROTECTION VOLTAGE PROTECTION

SWITCH2

19 (-)24 (17)

VSSD n.c.

CONTROL

AND

HANDSHAKE

CONTROL

AND

HANDSHAKE

VDDP2

23 (16)13 (7)18 (12) 14 (8)

DRIVER

HIGH

DRIVER

LOW

TDA8950TH (TDA8950J)

DRIVER

HIGH

DRIVER

LOW

17 (11)

VDDP1

16 (10)

SSP1

DDP2

22 (15)

21 (14)

20 (13)

VSSP2VSSP1

15 (9)

BOOT1

OUT1

BOOT2

OUT2

001aah653

Preliminary data sheet Rev. 01 — 9 September 2008 3 of 39

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7. Pinning information

7.1 Pinning

VSSD VSSA

VDDP2 SGND

BOOT2 VDDA

OUT2 IN2M

VSSP2 IN2P

n.c. MODE

STABI OSC

VSSP1 IN1P

OUT1 IN1M

BOOT1 n.c.

VDDP1 n.c.

PROT n.c.

TDA8950TH

TDA8950

2 × 150 W class-D power ampliﬁer

OSC

IN1P

IN1M

n.c.

PROT

OUT1

STABI

OUT2

VSSD

VSSA

SGND

VDDA

IN2M

IN2P

MODE

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

TDA8950J

VDDP1 BOOT1

VSSP1

1 2 3 4 5 6 7 8

9 10 11 12

VSSP2

BOOT2 VDDP2

001aah654

001aah655

Fig 2. Pin conﬁguration TDA8950TH Fig 3. Pin conﬁguration TDA8950J

Preliminary data sheet Rev. 01 — 9 September 2008 4 of 39

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7.2 Pin description

Table 3. Pin description

Symbol Pin Description

VSSA 1 18 negative analog supply voltage SGND 2 19 signal ground VDDA 3 20 positive analog supply voltage IN2M 4 21 negative audio input for channel 2 IN2P 5 22 positive audio input for channel 2 MODE 6 23 mode selection input: Standby,Mute or Operating

OSC 7 1 oscillator frequency adjustment or tracking input IN1P 8 2 positive audio input for channel 1 IN1M 9 3 negative audio input for channel 1 n.c. 10 4 not connected n.c. 11 5 not connected n.c. 12 6 not connected PROT 13 7 decoupling capacitor for protection (OCP) VDDP1 14 8 positive power supply voltage for channel 1 BOOT1 15 9 bootstrap capacitor for channel 1 OUT1 16 10 PWM output from channel 1 VSSP1 17 11 negative power supply voltage for channel 1 STABI 18 12 decoupling of internal stabilizer for logic supply n.c. 19 - not connected VSSP2 20 13 negative power supply voltage for channel 2 OUT2 21 14 PWM output from channel 2 BOOT2 22 15 bootstrap capacitor for channel 2 VDDP2 23 16 positive power supply voltage for channel 2 VSSD 24 17 negative digital supply voltage

TDA8950

2 × 150 W class-D power ampliﬁer

TDA8950TH TDA8950J

mode

8. Functional description

8.1 General

The TDA8950 is a two-channel audio power ampliﬁer using class-D technology. The audio input signal is converted into a digital pulse width modulated signal via an

analog input stage and PWM modulator, see Figure 1. To enable the output power transistors to be driven, this digital PWM signal is applied to a control and handshake block and driver circuits for both the high side and low side. In this way a level shift is performed from the low power digital PWM signal (at logic levels) to a high power PWM signal that switches between the main supply lines.

A 2nd-order low-pass ﬁlter converts the PWM signal to an analog audio signal across the loudspeakers.

Preliminary data sheet Rev. 01 — 9 September 2008 5 of 39

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The TDA8950 one-chip class-D ampliﬁer contains high power switches, drivers, timing and handshaking between the power switches and some control logic. Also an advanced protection strategy is implemented which contains several voltage protections, temperature protections and a maximum current protection to secure maximum system robustness.

The two audio channels of the TDA8950 each contain a PWM modulator, an analog feedback loop and a differential input stage. It also contains circuits common to both channels such as the oscillator, all reference sources, the mode interface and a digital timing manager.

The TDA8950 contains two independent ampliﬁer channels with high output power, high efﬁciency, low distortion and low quiescent current. The ampliﬁer channels can be connected in the following conﬁgurations:

• Mono Bridge-Tied Load (BTL) ampliﬁer

• Stereo Single-Ended (SE) ampliﬁers

The ampliﬁer system can be switched to one of three operating modes by pin MODE:

TDA8950

2 × 150 W class-D power ampliﬁer

• Standby mode; with a very low supply current

• Mute mode; the ampliﬁers are operational, but the audio signal at the output is

suppressed by disabling the VI-converter input stages

• Operating mode; the ampliﬁers are fully operational

To ensure pop noise-free start-up, the DC output offset voltage is applied gradually to the output at a level between Mute mode and Operating mode levels. The bias current setting of the VI converters is related to the voltage on pin MODE; in Mute mode the bias current setting of the VI converters is zero (VI converters disabled) and in Operating mode the bias current is at maximum. The time constant required to apply the DC output offset voltage gradually between Mute and Operating mode levels can be generated via an RC-network on pin MODE. An example of a switching circuit for driving pin MODE is illustrated in Figure 4. If the capacitor C is left out of the application, the voltage on pin MODE will be applied with a much smaller time-constant, which might result in audible pop noises during start-up (depending on DC output offset voltage and loudspeaker used).

5 V

standby/

mute

MODE pin

mute/on

SGND

001aab172

Fig 4. Example of mode selection circuit

Preliminary data sheet Rev. 01 — 9 September 2008 6 of 39

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In order to fully charge the coupling capacitors at the inputs, the ampliﬁer will remain automatically in the Mute mode before switching to the Operating mode. A complete overview of the start-up timing is given in Figure 5.

MODE

TDA8950

2 × 150 W class-D power ampliﬁer

audio output

(1)

modulated PWM

50 %

duty cycle

2.2 V < V

> 4.2 V

< 3 V

MODE

0 V (SGND)

MODE

> 4.2 V

< 3 V

MODE

standby

mute

100 ms

50 %

duty cycle

mute

(1)

50 ms

operating

> 350 ms

audio output

modulated PWM

operating

time

0 V (SGND)

standby

100 ms

50 ms

> 350 ms

time

001aah657

(1) First1⁄4 pulse down.

Upper diagram: When switching from standby to mute, there is a delay of approximately 100 ms before the output starts switching. The audio signal is available after V

has been set to

MODE

operating, but not earlier than 150 ms after switching to mute. For pop noise-free start-up it is recommended that the time constant applied to pin MODE is at least 350 ms for the transition between mute and operating.

Lower diagram: When switchingdirectlyfromstandbyto operating, there is a ﬁrst delay of 100 ms before the outputs starts switching. The audio signal is available after a second delay of 50 ms. For pop noise-free start-up it is recommended that the time constant applied to pin MODE is at least 500 ms for the transition between standby and operating.

Fig 5. Timing on mode selection input

Preliminary data sheet Rev. 01 — 9 September 2008 7 of 39

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8.2 Pulse width modulation frequency

The output signal of the ampliﬁer is a PWM signal with a carrier frequency that typically lies between 300 kHz and 400 kHz. Using a 2nd-order LC demodulation ﬁlter in the application results in an analog audio signal across the loudspeaker. The carrier frequency is determined by an external resistor R pin VSSA. An optimal setting for the carrier frequency is between 300 kHz and 400 kHz.

Using an external resistor of 30 kΩ on pin OSC, the carrier frequency is set to 345 kHz. For more details see Table 8.

If two or more class-D ampliﬁers are used in the same audio application, it is recommended that all devices operate at the same switching frequency by using an external clock circuit.

Due to an internal clock divider:

• The external applied clock frequency must have the double frequency of the output

• The duty cycle of the external clock is not critical for product performance.

PWM frequency.

TDA8950

2 × 150 W class-D power ampliﬁer

, connected between pin OSC and

OSC

8.3 Protections

The following protections are included in TDA8950:

• Thermal protections:

– Thermal FoldBack (TFB) – OverTemperature Protection (OTP)

• OverCurrent Protection (OCP, diagnostic via pin PROT)

• Window Protection (WP)

• Supply voltage protections:

– UnderVoltage Protection (UVP) – OverVoltage Protection (OVP) – UnBalance Protection (UBP)

The reaction of the device to the different fault conditions differs per protection.

8.3.1 Thermal protection

In the TDA8950 an advanced thermal protection strategy is implemented. It consists of a TFB function that gradually reduces the out put power within a certain temperature range. When temperature is still rising an OTP is implemented which shuts down the device completely.

8.3.1.1 Thermal FoldBack (TFB)

If the junction temperature Tj exceeds a deﬁned threshold value, the gain is gradually reduced. This will result in a smaller output signal and less dissipation. Eventually the temperature will stabilize.

Preliminary data sheet Rev. 01 — 9 September 2008 8 of 39

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TDA8950

2 × 150 W class-D power ampliﬁer

TFB is speciﬁed at the temperature value T reduced with 6 dB. The range of the TFB is:

act(th_fold)

For the TDA8950 the value of T

− 5 °C < T

act(th_fold)

< T

act(th_prot)

act(th_fold)

8.3.1.2 OverTemperature Protection (OTP)

If, despite the TFB function, the junction temperature Tj of the TDA8950 continues rising and exceeds the threshold T

act(th_prot)

ampliﬁer resumes switching approximately 100 ms after the temperature drops below T

act(th_prot)

In Figure 6 the thermal behavior is visualized.

Gain

(dB)

30 dB

24 dB

0 dB

act(th_fold)

12 3

act(th_fold)

where the closed loop voltage gain is

is about +153 °C. For more details see: Table 7.

the ampliﬁer will shutdown immediately. The

(°C) T

− 5°C)

act(th_fold)

act(th_prot)

001aah656

(1) Duty cycle of PWM output modulated according audio input signal. (2) Duty cycle of PWM output reduced due to TFB. (3) Ampliﬁer is switched off due to OTP.

Fig 6. Behavior of TFB and OTP

8.3.2 OverCurrent Protection (OCP)

If a short-circuit is applied to one of the demodulated outputs of the ampliﬁer, the OCP will detect this. If the output current exceeds the maximum of 9.2 A, it is automatically limited to its maximum value by the OCP protection circuit. The ampliﬁer outputs remain switching (the ampliﬁer is NOT shut-down completely). If the active current limiting continues longer than time τ, the TDA8950 shuts down. Activation of current limiting and the triggering of the OCP are observed at pin PROT.

The ampliﬁer can distinguish between an impedance drop of the loudspeaker and a low-ohmic short-circuit across the load. In the TDA8950 the impedance threshold (Zth) depends on the supply voltage used.

When a short-circuit is made across the load, causing the impedance to drop below the threshold level (<Zth), the ampliﬁer is switched off completely and, after a time of 100 ms, it will try to restart. If the short-circuit condition is still present after this time, the cycle will be repeated. The average dissipation will be low because of this low duty cycle.

Preliminary data sheet Rev. 01 — 9 September 2008 9 of 39

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Should there be an impedance drop (e.g. due to dynamic behavior of the loudspeaker) the same protection will be activated. The maximum output current will again be limited to

9.2 A, but the ampliﬁer will not switch-off completely (thus preventing audio holes from occurring).

The result will be a clipping output signal. See Section 13.7 for more information on this maximum output current limiting feature.

8.3.3 Window Protection (WP)

The WP checks the conditions at the output terminals of the power stage and is activated:

• During the start-up sequence, when pin MODE is switched from standby to mute. In

• When the ampliﬁer is completely shut-down due to activation of the OCP because a

TDA8950

2 × 150 W class-D power ampliﬁer

the event of a short-circuit at one of the output terminals to pin VDDPn or pin VSSPn the start-up procedure is interrupted and the TDA8950 waits until the short-circuit to the supply lines has been removed. Because the test is done before enabling the power stages, no large currents will ﬂow in an event of short-circuit.

short-circuit to one of the supply lines is made, then during restart (after 100 ms) the WP will be activated. As a result the ampliﬁer will not start-up until the short-circuit to the supply lines is removed.

8.3.4 Supply voltage protections

If the supply voltage drops below minimum supply voltage, the UVP circuit is activated and the system will shutdown correctly. If the internal clock is used, this switch-off will be silent and without pop noise. When the supply voltage rises above the threshold level, the system is restarted again after 100 ms.

If the supply voltage exceeds maximum supply voltage, the OVP circuit is activated and the power stages will shutdown. When the supply voltage drops below the threshold level, the system is restarted again after 100 ms.

An additional UBP circuit compares the positive analog (voltage on pin VDDA) and the negative analog (voltage on pin VSSA) supply voltage and is triggered if the voltage difference exceeds a factor of two.

When the supply voltage difference drops below the threshold level, the system is restarted again after 100 ms.

Example: With a symmetrical supply of ±30 V, the protection circuit will be triggered if the unbalance exceeds approximately 15 V. See Section 13.7.

In Table 4 an overview is given of all protections and their respective effects on the output signal.

Preliminary data sheet Rev. 01 — 9 September 2008 10 of 39

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Table 4. Overview of TDA8950 protections

Protection name Complete

TFB OTP Y N Y N OCP Y WP N UVPYNYN OVP Y N Y N UBPYNYN

[1] Ampliﬁer gain will depend on junction temperature and heatsink size. [2] Only complete shutdown of ampliﬁer if short-circuit impedance is below threshold of 1 Ω. In all other cases

[3] Fault condition detected during (every) transition between standby-to-mute and during restart after

8.4 Differential audio inputs

Restart directly Restart after

shutdown

[1]

current limiting results in clipping of the output signal.

activation of OCP (short-circuit to one of the supply lines).

NNNN

[2] [3]

[2]

N YNN

TDA8950

2 × 150 W class-D power ampliﬁer

Pin PROT

100 ms

[2]

detection

Fora high common mode rejection ratio and a maximum of ﬂexibility in the application, the audio inputs are fully differential.

There are two possibilities:

• For stereo operation it is advised to use the inputs in anti phase and also to connect

the speakers in anti phase (to avoid acoustical phase differences). This construction has several advantages:

– The peak current in the power supply is minimized – The supply pumping effect is minimized, especially at low audio frequencies

• For mono BTL operation it is required that the inputs are connected in anti parallel.

The output of one of the channels is inverted and the speaker load is now connected between the two outputs of the TDA8950. In principle the output power to the speaker can be signiﬁcantly boosted to two times the output power in single ended stereo.

The input conﬁguration for a mono BTL application is illustrated in Figure 7.

IN1P

IN1M

IN2P

IN2M

OUT1

SGND

OUT2

power stage

mbl466

Fig 7. Input conﬁguration for mono BTL application

Preliminary data sheet Rev. 01 — 9 September 2008 11 of 39

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9. Limiting values

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

ORM

stg

amb

MODE

OSC

PROT

esd

q(tot)

TDA8950

2 × 150 W class-D power ampliﬁer

supply voltage non-operating mode; VDD− V repetitive peak

maximum output current limiting 9.2 - A

output current storage temperature −55 +150 °C ambient temperature −40 +85 °C junction temperature - 150 °C voltage on pin

referenced to SGND 0 6 V

MODE voltage on pin OSC 0 SGND

input voltage referenced to SGND; pin IN1P; IN1M;

IN2P and IN2M voltage on pin PROT referenced to voltage on pin VSSD 0 12 V electrostatic

discharge voltage

Human Body Model (HBM);

pin VSSP1 with respect to other pins

HBM; all other pins −2000 +2000 V

Machine Model (MM); all pins −200 +200 V

Charged Device Model (CDM) −500 +500 V total quiescent

current

Operating mode; no load; no ﬁlter; no

RC-snubber network connected

-90V

+ 6

−5+5V

−1800 +1800 V

-75mA

10. Thermal characteristics

Table 6. Thermal characteristics

Symbol Parameter Conditions Typ Unit

th(j-a)

th(j-c)

Preliminary data sheet Rev. 01 — 9 September 2008 12 of 39

thermal resistance from junction to ambient in free air 40 K/W thermal resistance from junction to case 1.1 K/W

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TDA8950

2 × 150 W class-D power ampliﬁer

11. Static characteristics

Table 7. Static characteristics

VP =±35 V; f

Symbol Parameter Conditions Min Typ Max Unit

Supply

P(ovp)

P(uvp)

q(tot)

stb

Mode select input; pin MODE

MODE

Audio inputs; pins IN1M, IN1P, IN2P and IN2M

Ampliﬁer outputs; pins OUT1 and OUT2

O(offset)

Stabilizer output; pin STABI

O(STABI)

Temperature protection

act(th_prot)

act(th_fold)

= 345 kHz; T

osc

supply voltage overvoltage protection supply voltage non-operating; VDD− V undervoltage protection supply voltage VDD− V total quiescent current Operating mode; no load; no

= 25°C; unless otherwise speciﬁed.

amb

[1]

±12.5 ±35 ±40 V 85 - 90 V 20 - 25 V

- 5075mA ﬁlter; no RC-snubbernetwork connected

standby current - 480 600 µA

voltage on pin MODE referenced to SGND

Standby mode Mute mode Operating mode

[2]

0 - 6.0 V

[2][3]

0 - 0.8 V

[2][3]

2.2 - 3.0 V

[2][3]

4.2 - 6.0 V

input current VI = 5.5 V - 110 150 µA

input voltage DC input

[2]

-0-V

output offset voltage SE; mute - - ±15 mV

[4]

SE; operating

--±150 mV BTL; mute - - ±21 mV

[4]

BTL; operating

output voltage on pin STABI mute and operating; with

--±210 mV

9.3 9.8 10.3 V respect to VSSP1

thermal protection activation

- 154 - °C

temperature thermal foldback activation

temperature

closed loop SE voltage gain reduced with 6 dB

[5]

- 153 - °C

[1] The circuit is DC adjusted at VP= ±12.5 V to ±42.5 V. [2] With respect to SGND (0 V). [3] The transition between Standby and Mute mode has hysteresis, while the slope of the transition between Mute and Operating mode is

determined by the time-constant of the RC-network on pin MODE; see Figure 8.

[4] DC output offset voltage is gradually applied to the output during the transition between the Mute and Operating modes. The slope

caused by any DC output offset is determined by the time-constant of the RC-network on pin MODE.

[5] At a junction temperature of approximately T

approximately T

Preliminary data sheet Rev. 01 — 9 September 2008 13 of 39

act(th_prot)

the ampliﬁer switches off.

act(th_fold)

− 5 °C the gain reduction will commence and at a junction temperature of

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VO (V)

O(offset)(on)

O(offset)(mute)

TDA8950

2 × 150 W class-D power ampliﬁer

slope is directly related to the time-constant

of the RC network on the MODE pin

Standby Mute On

Fig 8. Behavior of mode selection pin MODE

12. Dynamic characteristics

12.1 Switching characteristics

Table 8. Dynamic characteristics

VP =±35 V; T

Symbol Parameter Conditions Min Typ Max Unit

Internal oscillator

osc(typ)

osc

External oscillator or frequency tracking

OSC

trip(OSC)

track

[1] When using an external oscillator, the f

in a PWM frequency f

Section 8.2.

= 25°C; unless otherwise speciﬁed.

amb

typical oscillator frequency

oscillator frequency 250 - 450 kHz

voltage on pin OSC SGND + 4.5 SGND + 5 SGND + 6 V trip voltage on pin

OSC tracking frequency

4.23.02.20.80 V

MODE

= 30.0 kΩ 325 345 365 kHz

OSC

5.5

(V)

coa021

- SGND + 2.5 - V

[1]

250 - 450 kHz

frequency (500 kHz minimum, 900 kHz maximum) will result

(250 kHz minimum, 450 kHz maximum) due to the internal clock divider. See

track

osc(ext)

Preliminary data sheet Rev. 01 — 9 September 2008 14 of 39

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12.2 Stereo and dual SE application characteristics

TDA8950

2 × 150 W class-D power ampliﬁer

Table 9. Dynamic characteristics

VP =±35 V; RL = 4Ω; fi = 1 kHz; f

= 345 kHz; RsL < 0.1

osc

[1]

Ω

; T

= 25°C; unless otherwise speciﬁed.

amb

Symbol Parameter Conditions Min Typ Max Unit

output power L = 22 µH; C = 680 nF; Tj=85°C

[2]

RL=4Ω; THD = 0.5 %; VP = ±37 V - 100 - W

=4Ω; THD = 10 %; VP = ±37 V - 150 - W

=6Ω; THD = 10 %; VP = ±37 V - 100 - W

=4Ω; THD = 10 %; VP = ±39 V - 170 - W

THD total harmonic distortion P

v(cl)

closed-loop voltage gain 29 30 31 dB

= 1 W; fi= 1 kHz

= 1 W; fi= 6 kHz

[3]

- 0.05 - %

[3]

- 0.05 - %

SVRR supply voltage ripple rejection between pin VDDPn and SGND

operating; f operating; f mute; f

= 100 Hz

standby; f

= 100 Hz

= 1 kHz

= 100 Hz

[4]

-90-dB

[4]

-70-dB

[4]

-75-dB

[4]

- 120 - dB

between pin VSSPn and SGND

operating; f operating; f mute; f standby; f

n(o)

input impedance between the input pins and SGND 45 63 - kΩ output noise voltage operating; Rs=0Ω

= 100 Hz

= 1 kHz

= 100 Hz

mute

|∆G

mute

CMRR common mode rejection ratio V

DSon(hs)

DSon(ls)

channel separation

| voltage gain difference - - 1 dB

mute attenuation fi= 1 kHz; Vi= 2 V (RMS)

= 1 V (RMS) - 75 - dB

i(CM)

output power efﬁciency SE, RL = 4 Ω -88-%

= 6 Ω -90-

SE, R

BTL, R

= 8 Ω -88-%

high-side drain-source on-state resistance low-side drain-source on-state resistance

[4]

-80-dB

[4]

-60-dB

[4]

-80-dB

[4]

- 115 - dB

[5]

- 160 - µV

[6]

-85-µV

[7]

-70-dB

[8]

-75-dB

[9]

- 200 - mΩ

[9]

- 190 - mΩ

[1] RsL is the series resistance of inductor of low-pass LC ﬁlter in the application. [2] Output power is measured indirectly; based on R [3] THD is measured in a bandwidth of 22 Hz to 20 kHz, using AES17 20 kHz brickwall ﬁlter. Maximum limit is not guaranteed100 % tested. [4] V [5] B = 22 Hz to 20 kHz, using AES17 20 kHz brickwall ﬁlter. [6] B = 22 Hz to 22 kHz, using AES17 20 kHz brickwall ﬁlter; independent of Rs. [7] Po = 1 W; Rs = 0 Ω; fi = 1 kHz. [8] Vi = V [9] Leads and bond wires included.

Preliminary data sheet Rev. 01 — 9 September 2008 15 of 39

ripple

= V

i(max)

ripple(max)

= 2 V (p-p); Rs = 0 Ω. Measured independently between VDDPn and SGND and between VSSPn and SGND.

= 1 V (RMS); fi = 1 kHz.

measurement. See also Section 13.3.

DSon

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12.3 Mono BTL application characteristics

TDA8950

2 × 150 W class-D power ampliﬁer

Table 10. Dynamic characteristics

VP =±35 V; RL = 8Ω; fi = 1 kHz; f

= 345 kHz; RsL < 0.1

osc

[1]

Ω

; T

= 25°C; unless otherwise

amb

speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

output power L = 22 µH; C = 680 nF;

=85°C; RL=8Ω

[2]

THD = 10 %; VP= ±39 V - 340 - W

= ±37 V - 300 - W

= ±37 V - 200 - W

[3]

- 0.05 - %

[3]

- 0.05 - %

-36-dB

THD total harmonic

distortion

v(cl)

closed-loop voltage

THD = 10 %; V THD = 0.5 %; V

= 1 W; fi= 1 kHz

= 1 W; fi= 6 kHz

gain

SVRR supply voltage ripple

rejection

between pin VDDPn and SGND

operating; f operating; f mute; f standby; f

= 100 Hz

= 1 kHz

= 100 Hz

[4]

-80-dB

[4]

-80-dB

[4]

-95-dB

[4]

- 120 - dB

between pin VSSPn and SGND

operating; f operating; f mute; f standby; f

input impedance measured between the input

= 100 Hz

= 1 kHz

= 100 Hz

[4]

-75-dB

[4]

-75-dB

[4]

-90-dB

[4]

- 130 - dB 45 63 - kΩ

pins and SGND

n(o)

mute

output noise voltage operating; Rs=0Ω

mute attenuation fi= 1 kHz; Vi= 2 V (RMS)

CMRR common mode

mute

= 1 V (RMS) - 75 - dB

i(CM)

[5]

- 190 - µV

[6]

-45-µV

[7]

-82-dB

rejection ratio

[1] RsL is the series resistance of inductor of low-pass LC ﬁlter in the application. [2] Output power is measured indirectly; based on R [3] Total harmonic distortion is measured in a bandwidth of 22 Hz to 20 kHz, using an AES17 20 kHz brickwall

ﬁlter. Maximum limit is guaranteed but may not be 100 % tested. [4] V [5] B = 22 Hz to 20 kHz, using an AES17 20 kHz brickwall ﬁlter. Low noise due to BD modulation. [6] B = 22 Hz to 20 kHz, using an AES17 20 kHz brickwall ﬁlter; independent of Rs. [7] Vi = V

Preliminary data sheet Rev. 01 — 9 September 2008 16 of 39

ripple

= V

i(max)

= 2 V (p-p); Rs = 0 Ω.

ripple(max)

= 1 V (RMS); fi = 1 kHz.

measurement. See also Section 13.3.

DSon

NXP Semiconductors

13. Application information

13.1 Mono BTL application

When using the power ampliﬁer in a mono BTL application the inputs of both channels must be connected in parallel and the phase of one of the inputs must be inverted (see

Figure 7). In principle the loudspeaker can be connected between the outputs of the two

single-ended demodulation ﬁlters.

13.2 Pin MODE

For pop noise-free start-up, an RC time-constant must be applied on pin MODE. The bias-current setting of the VI-converter input is directly related to the voltage on pin MODE. In turn the bias-current setting of the VI converters is directly related to the DC output offset voltage. Thus a slow dV/dt on pin MODE results in a slow dV/dt for the DC output offset voltage, resulting in pop noise-free start-up. A time-constant of 500 ms is sufﬁcient to guarantee pop noise-free start-up (see also Figure 4, 5 and 8).

13.3 Output power estimation

TDA8950

2 × 150 W class-D power ampliﬁer

13.3.1 SE

Maximum output power:

Maximum current internally limited to 9.2 A:

opeak()

Variables:

---------------------------------------------------- -

RLR

o 0.5%()

• R

• f

osc

• t

min

• V

• P

----------------------------------------------------------------------------------------------------------------------------------

--------------------------------------------------------------

RLR

: load impedance

: series impedance of the ﬁlter coil

sL DSon(hs)

: high-side R

: oscillator frequency

: minimum pulse width (typical 150 ns, temp. dependent)

: single-sided supply voltage (or 0.5 × (VDD + |VSS|))

: output power at the onset of clipping

o(0.5 %)

DSon hs()RsL

min

0.5 f

×–()×

DSon

–()××

osc

min

of power stage output DMOS (temperature dependent)

0.5× f

osc

(1)

(2)

Note that I

should be below 9.2 A (Section 8.3.2). I

o(peak)

o(peak)M

is the sum of the current through the load and the ripple current. The value of the ripple current is dependent on the coil inductance and voltage drop over the coil.

Preliminary data sheet Rev. 01 — 9 September 2008 17 of 39

NXP Semiconductors

13.3.2 Bridge-Tied Load (BTL)

Maximum output power:

TDA8950

2 × 150 W class-D power ampliﬁer

osc

(3)

o 0.5%()

----------------------------------------------------------------- -

RLR

--------------------------------------------------------------------------------------------------------------------------------------------------

DSon hs()Rdson ls()

2VP1t

min

×–()××

0.5 f

Maximum current internally limited to 9.2 A:

opeak()

2VP1t

-------------------------------------------------------------------------------------------

RLR

DSon hs()RDSon ls()

0.5 f

×–()×

min

osc

+()2R

(4)

Variables:

• R

: load impedance

• R

: series impedance of the ﬁlter coil

• R

DSon(hs)

• R

DSon(ls)

• f

osc

• t

min

• V

• P

o(0.5 %)

Note that I

: high-side R

: low-side R

of power stage output DMOS (temperature dependent)

DSon

of power stage output DMOS (temperature. dependent)

DSson

: oscillator frequency

: minimum pulse width (typical 150 ns, temp. dependent)

: single-sided supply voltage (or 0.5 × (VDD + |VSS|))

: output power at the onset of clipping

o(peak)M

should be below 9.2 A (Section 8.3.2). I

o(peak)

is the sum of the current through the load and the ripple current. The value of the ripple current is dependent on the coil inductance and voltage drop over the coil.

13.4 External clock

For duty cycle independent operation of the device, the external clock input frequency is internally divided by two. This implies that the frequency of the external clock is as twice as high as the internal clock (typical 2 × 345 kHz = 690 kHz).

If two or more class-D ampliﬁers are used it is recommended that all devices run at the same switching frequency. This can be realized by connecting all OCS pins together and feeding them from an external oscillator. When applying an external oscillator, it is necessary to force pin OSC to a DC level above SGND. The internal oscillator is disabled and the PWM modulator will switch with half the externally applied frequency.

The internal oscillator requires an external resistor R

ext(OSC)

pin OSC and PIN VSSA. The noise contribution of the internal oscillator is supply voltage dependent. An external

low noise oscillator is recommended for low noise applications running at high supply voltage.

Preliminary data sheet Rev. 01 — 9 September 2008 18 of 39

and capacitor C

OSC

between

NXP Semiconductors

13.5 Noise

Noise should be measured using a high order low-pass ﬁlter with a cut-off frequency of 20 kHz. The standard audio band pass ﬁlters, used in audio analyzers, do not suppress the residue of the carrier frequency sufﬁciently to ensure a reliable measurement of the audible noise. Noise measurements should preferably be carried out using AES 17 (‘brickwall’) ﬁlters or an audio precision AUX 0025 ﬁlter, which was designed speciﬁcally for measuring class-D switching ampliﬁers.

13.6 Heatsink requirements

In many applications it may be necessary to connect an external heatsink to the TDA8950.

Equation 5 shows the relationship between the maximum power dissipation, before

activation of the TFB, and the total thermal resistance from junction to ambient

th j a–()

TjT

----------------------- -

–

diss

amb

TDA8950

2 × 150 W class-D power ampliﬁer

(5)

Power dissipation (P

) is determined by the efﬁciency of the TDA8950. The efﬁciency

diss

measured as a function of output power is given in Figure 21. The power dissipation can be derived as a function of output power (Figure 20).

amb

mbl469

(°C)

(1) R (2) R (3) R (4) R (5) R

th(j-a) th(j-a) th(j-a) th(j-a) th(j-a)

= 5 K/W. = 10 K/W. = 15 K/W. = 20 K/W. = 35 K/W.

(W)

0 20 10040 60 80

(1)

(2)

(3) (4)

(5)

Fig 9. De-rating curves for power dissipation as a function of maximum ambient

temperature

In the following example, a heatsink calculation is made for an 8 Ω BTL application with a ±35 V supply:

Preliminary data sheet Rev. 01 — 9 September 2008 19 of 39

NXP Semiconductors

The audio signal has a crest factor of 10 (the ratio between peak power and average power (20 dB)), this means that the average output power is1⁄10 of the peak power.

In this case, the peak RMS output power level would be the 0.5 % THD level, i.e. 220 W. The average power would then be1⁄10× 220W=22W. The dissipated power at an output power of 22 W is approximately 5 W.

TDA8950

2 × 150 W class-D power ampliﬁer

When the maximum expected ambient temperature is 85 °C, the total R become

th(j-a)

R R

140 85–()

-------------------------

= R

th(j-c) th(c-h)

+ R

th(j-c)

= 1.1 K/W

= 0.5 K/W to 1 K/W (dependent on mounting)

th(c-h)

11 K/W=

+ R

So the thermal resistance between heatsink and ambient temperature is:

= 11 − (1.1 + 1) = 8.9 K/W

th(h-a)

The de-rating curves (given for several values of R maximum junction temperature Tj= 150 °C is taken into account. From Figure 9 the maximum allowable power dissipation for a given heatsink size can be derived or the required heatsink size can be determined at a required dissipation level.

13.7 Output current limiting

To guarantee the robustness of the TDA8950, the maximum output current that can be delivered by the output stage is limited. An advanced OverCurrent Protection (OCP) is included for each output power switch.

When the current ﬂowing through any of the power switches exceeds the deﬁned internal threshold current of 9.2 A (e.g. in case of a short-circuit to the supply lines or a short-circuit across the load), the maximum output current of the ampliﬁer will be regulated to 9.2 A.

th(h-a)

th(j-a)

) are illustrated in Figure 9. A

th(j-a)

would then

The TDA8950 ampliﬁer can distinguish between a low-ohmic short-circuit condition and other over current conditions like dynamic impedance drops of the loudspeakers used. The impedance threshold (Zth) depends on the supply voltage used.

Depending on the impedance of the short-circuit, the ampliﬁer will react as follows:

• Short-circuit impedance > Z

: The maximum output current of the ampliﬁer is

regulated to 9.2 A, but the ampliﬁer will not shut-down its PWM outputs. Effectively this results in a clipping output signal across the load (behavior is very similar to voltage clipping).

• Short-circuit impedance < Z

: The ampliﬁer will limit the maximum output current to

9.2 A and at the same time the capacitor on pin PROT is discharged. When the voltage across this capacitor drops below an internal threshold voltage, the ampliﬁer will shutdown completely and an internal timer will be started.

A typical value for the capacitor on pin PROT is 220 pF. After a ﬁxed time of 100 ms the ampliﬁer is switched on again. If the requested output current is still too high, the ampliﬁer will switch-off again. Thus the ampliﬁer will try to switch to the Operating mode every

Preliminary data sheet Rev. 01 — 9 September 2008 20 of 39

NXP Semiconductors

100 ms. The averagedissipation will be low in this situation because of this low duty cycle. If the over current condition is removed the ampliﬁer will remain in Operating mode after being restarted. In this way the TDA8950 ampliﬁer is fully protected against short-circuit conditions while at the same time so-called audio holes, as a result of loudspeaker impedance drops, are eliminated.

13.8 Pumping effects

In a typical stereo half-bridge SE application the TDA8950 is supplied by a symmetrical voltage (e.g. VDD= +35 V and VSS= −35 V). When the ampliﬁer is used in an SE conﬁguration, a ‘pumping effect’ can occur. During one switching interval, energy is taken from one supply (e.g. VDD), while a part of that energy is returned to the other supply line (e.g. VSS) and vice versa. When the voltage supply source cannot sink energy,the voltage across the output capacitors of that voltage supply source will increase and the supply voltage is pumped to higher levels. The voltage increase caused by the pumping effect depends on:

• Speaker impedance

• Supply voltage

• Audio signal frequency

• Value of decoupling capacitors on supply lines

• Source and sink currents of other channels

TDA8950

2 × 150 W class-D power ampliﬁer

When applying the TDA8950, measures must be taken within the application to minimize the pumping effect and prevent malfunctions of either the audio ampliﬁer and/or the voltage supply source. Ampliﬁer malfunction due to the pumping effect can cause triggering of the UVP, OVP or UBP.

The best remedy against pumping effects is to use the TDA8950 in a mono full-bridge application or, in the case of stereo half-bridge applications, adapt the power supply (e.g. increase supply decoupling capacitors).

13.9 Application schematics

Notes for the application schematic:

• A solid ground plane connected to V

prevent emission.

• 100 nF capacitors must be placed as close as possible to the power supply pins of the

TDA8950.

• The internal heat spreader of the TDA8950 is internally connected to V

• The external heatsink must be connected to the ground plane.

• Use a thermally conductive, electrically non-conductive, Sil-Pad between the backside

of the TDA8950 and a small external heatsink.

• The differential inputs enable the best system level audio performance with

unbalanced signal sources. In case of hum, due to ﬂoating inputs, connect the shielding or source ground to the ampliﬁer ground. Jumpers J1 and J2 are open on set level and are closed on the stand-alone demo board.

• Minimum total required capacitance per power supply line is 3300 µF.

around the switching ampliﬁer is necessary to

Preliminary data sheet Rev. 01 — 9 September 2008 21 of 39

Preliminary data sheet Rev. 01 — 9 September 2008 22 of 39

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

NXP Semiconductors

VDDP

GND

VSSP

IN1

IN2

Rvdda

Cvddp 470 µF

Cvssp 470 µF

Cin

470 nF

Cin

−

470 nF

Cin

−

470 nF

Cin

470 nF

IN1P

IN1N

SGND

IN2P

IN2N

Cvp 22 µF

Rvssa

20 18

VDDA

Cvdda

100 nF

VDDA VSSA

10 Ω

n.c.

VDDA

VDDP

SINGLE ENDED

OUTPUT FILTER VALUES

LOAD Llc Clc

2 Ω - 3 Ω 10 µH 1000 nF

mode

Rosc 30 kΩ

OSC 1

PROT

Cprot 100 nF

control

MODE

SSA

177

VSSD

Cvddp

100 nF

Cvddp

100 nF

VDDP

VDDP1

VDDP2

VDDP

Cvp

100 nF

Cvp

100 nF

VSSP

VSSP1

VSSP2

VSSP

Cvssp

100 nF

Cvssp

100 nF

OUT1

BOOT1

BOOT2

OUT2

Rsn

10 Ω

Cbo

15 nF

Cbo

15 nF

Rsn

10 Ω

VSSA

VSSP

VSSA

n.c.

TDA8950J

VSSA

Cvssa

100 nF

STABI

SSP

Cstab 470 nF

3 Ω - 6 Ω 15 µH 680 nF 4 Ω - 8 Ω 22 µH 470 nF

VDDP

Csn 220 pF

VSSP

Llc

VDDP

Csn 220 pF

VSSP

Clc

Rzo 22 Ω

Czo 100 nF

Rzo 22 Ω

Czo 100 nF

−

001aai420

2 × 150 W class-D power ampliﬁer

TDA8950

Fig 10. Simpliﬁed application diagram

NXP Semiconductors

13.10 Layout and grounding

To obtain a high-level system performance, certain grounding techniques are essential. The input reference grounds have to be tied with their respective source grounds and must have separate tracks from the power ground tracks. This will prevent the large (output) signal currents from interfering with the small AC input signals. The small-signal ground tracks should be physically located as far as possible from the power ground tracks. Supply and output tracks should be as wide as possible for delivering maximum output power.

TDA8950

2 × 150 W class-D power ampliﬁer

R19 FBGNDR20, R21 ground

Fig 11. Printed-circuit board layout (quasi-single-sided); components view

Preliminary data sheet Rev. 01 — 9 September 2008 23 of 39

001aai421

NXP Semiconductors

13.11 Curves measured in reference design

TDA8950

2 × 150 W class-D power ampliﬁer

001aai422

Po (W)

THD

(%)

−1

−2

−3

−2

−1

110

(2)

(1)

(3)

VP = ±35 V, 2 × 4 Ω SE conﬁguration. (1) OUT2, fi = 6 kHz (2) OUT2, fi = 1 kHz (3) OUT2, fi = 100 Hz

Fig 12. THD as a function of output power, SE conﬁguration with 2 × 4 Ω load

001aai700

Po (W)

THD

(%)

−1

−2

−3

−2

−1

110

(2)

(1)

(3)

VP = ±35 V, 2 × 6 Ω SE conﬁguration. (1) OUT2, fi = 6 kHz (2) OUT2, fi = 1 kHz (3) OUT2, fi = 100 Hz

Fig 13. THD as a function of output power, SE conﬁguration with 2 × 6 Ω load

Preliminary data sheet Rev. 01 — 9 September 2008 24 of 39

NXP Semiconductors

TDA8950

2 × 150 W class-D power ampliﬁer

THD

(%)

−1

−2

−3

−2

VP = ±35 V, f

−1

= 350 kHz, 1 × 8 Ω BTL conﬁguration.

osc

110

(1)

(2)

(3)

001aai423

PO (W)

(1) fi = 6 kHz (2) fi = 1 kHz (3) fi = 100 Hz

Fig 14. THD as a function of output power, BTL conﬁguration with 1 × 8 Ω load

THD

(%)

−1

(1)

−2

−3

10 10

(2)

001aai424

fi (Hz)

VP = ±35 V, 2 × 4 Ω SE conﬁguration. (1) OUT2, PO = 1 W (2) OUT2, PO = 10 W

Fig 15. THD as a function of frequency, SE conﬁguration with 2 × 4 Ω load

Preliminary data sheet Rev. 01 — 9 September 2008 25 of 39

NXP Semiconductors

TDA8950

2 × 150 W class-D power ampliﬁer

THD

(%)

−1

(1)

−2

−3

10 10

(2)

001aai701

fi (Hz)

VP = ±35 V, 2 × 6 Ω SE conﬁguration. (1) OUT2, Po = 1 W (2) OUT2, Po = 10 W

Fig 16. THD as a function of frequency, SE conﬁguration with 2 × 6 Ω load

THD

(%)

001aai702

−1

−2

−3

10 10

(1)

(2)

f (Hz)

VP = ±35 V, 1 × 8 Ω BTL conﬁguration (1) Po = 1 W (2) Po = 10 W

Fig 17. THD as a function of frequency, BTL conﬁguration with 1 × 8 Ω load

Preliminary data sheet Rev. 01 — 9 September 2008 26 of 39

NXP Semiconductors

TDA8950

2 × 150 W class-D power ampliﬁer

(dB)

−20

−40

−60

−80

−100

10 10

001aai703

f (Hz)

VP = ±35 V, 2 × 4 Ω SE conﬁguration

For OUT1 and OUT2 for both 1 W and 10 W.

Fig 18. Channel separation as a function of frequency, SE conﬁguration with 2 × 4 Ω load

001aai704

(dB)

−20

−40

−60

−80

−100

10 10

f (Hz)

VP = ±35 V, 2 × 6 Ω SE conﬁguration

For OUT1 and OUT2 for both 1 W and 10 W.

Fig 19. Channel separation as a function of frequency, SE conﬁguration with 2 × 6 Ω load

Preliminary data sheet Rev. 01 — 9 September 2008 27 of 39

NXP Semiconductors

TDA8950

2 × 150 W class-D power ampliﬁer

(W)

0 120804020 10060

VP = ±35 V, fi = 1 kHz, f

= 325 kHz

osc

(1)

(2)

(3)

(1) 2 × 4 Ω SE conﬁguration (2) 2 × 6 Ω SE conﬁguration (3) 2 × 8 Ω SE conﬁguration

Fig 20. Power dissipation as function of output power per channel

001aai705

Po (W)

100

(%)

0 120804020 10060

VP = ±35 V, fi = 1 kHz, f

= 325 kHz

osc

(1)

(1) 2 × 4 Ω SE conﬁguration (2) 2 × 6 Ω SE conﬁguration (3) 2 × 8 Ω SE conﬁguration

Fig 21. Efﬁciency as function of output power per channel

001aai706

(2)

(3)

Po (W)

Preliminary data sheet Rev. 01 — 9 September 2008 28 of 39

NXP Semiconductors

TDA8950

2 × 150 W class-D power ampliﬁer

200

(W)

180 160 140 120 100

12.5 4032.53022.5 2515 17.5 20 37.53527.5

fi = 1 kHz, f

= 325 kHz

osc

(1)

(2)

(3) (4)

Note: inﬁnite heat sink used. (1) THD = 10 %, 4 Ω (2) THD = 0.5 %, 4 Ω; THD = 10 %, 6 Ω (3) THD = 0.5 %, 6 Ω; THD = 10 %, 8 Ω (4) THD = 0.5 %, 8 Ω

Fig 22. Output power as a function of supply voltage, SE conﬁguration

001aai707

Vp (V)

350

(W)

300

250

(1)

200

(2)

150

100

12.5 4032.53022.5 2515 17.5 20 37.53527.5

fi = 1 kHz, f

= 325 kHz

osc

(3)

(4)

Note: inﬁnite heat sink used. (1) THD = 10 %, 8 Ω (2) THD = 0.5 %, 8 Ω (3) THD = 10 %, 16 Ω (4) THD = 0.5 %, 16 Ω

Fig 23. Output power as function of supply voltage, BTL conﬁguration

001aai708

Vp (V)

Preliminary data sheet Rev. 01 — 9 September 2008 29 of 39

NXP Semiconductors

TDA8950

2 × 150 W class-D power ampliﬁer

v(cl)

(dB)

10 10

VP = ±35 V, Vi = 100 mV, Rs = 0 Ω, Ci = 330 pF. (1) 1 × 8 Ω BTL conﬁguration (2) 2 × 4 Ω SE conﬁguration (3) 2 × 6 Ω SE conﬁguration (4) 2 × 8 Ω SE conﬁguration

Fig 24. Gain as function of frequency, Rs = 0 Ω, Ci = 330 pF

001aai709

(1)

(2)

(3)

(4)

f (Hz)

−20

SVRR

(dB)

−40

−60

(1)

−80

(2)

−100

−120

−140

(3)

10 10

Ripple on VDD, short on input pins.

VP = ±35 V, RL = 4 Ω, V

= 2 V (p-p).

ripple

(1) OUT2, mute (2) OUT2, on (3) OUT2, standby

Fig 25. SVRR as function of ripple frequency

001aai710

(Hz)

ripple

Preliminary data sheet Rev. 01 — 9 September 2008 30 of 39

NXP Semiconductors

TDA8950

2 × 150 W class-D power ampliﬁer

−20

SVRR

(dB)

−40

−60

−80

−100

−120

−140

(2) (1)

(3)

10 10

Ripple on VSS, short on input pins.

VP = ±35 V, RL = 4 Ω, V

= 2 V (p-p).

ripple

(1) OUT2, mute (2) OUT2, on (3) OUT2, standby

Fig 26. SVRR as function of ripple frequency

001aai711

(Hz)

ripple

(V)

0.1

0.01

0.001

0.0001

(1)

(2)

0.00001

0.000001 0 54231 4.53.51.5 2.50.5

VP = ±35 V (1) Out1, down (2) Out1, up

Fig 27. Output voltage as function of mode voltage

001aai712

MODE

(V)

Preliminary data sheet Rev. 01 — 9 September 2008 31 of 39

NXP Semiconductors

TDA8950

2 × 150 W class-D power ampliﬁer

−50

mute

(dB)

−60

−70

(1) (2) (3)

−80

−90

10 10

VP = ±35 V, Vi = 2 V (rms), f

= 325 kHz

osc

(1) OUT2, 8 Ω (2) OUT2, 6 Ω (3) OUT2, 4 Ω

Fig 28. Mute attenuation as function of frequency

001aai713

f (Hz)

Preliminary data sheet Rev. 01 — 9 September 2008 32 of 39

NXP Semiconductors

14. Package outline

TDA8950

2 × 150 W class-D power ampliﬁer

DBS23P: plastic DIL-bent-SIL power package; 23 leads (straight lead length 3.2 mm)

non-concave

view B: mounting base side

A A

SOT411-1

123

DIMENSIONS (mm are the original dimensions)

UNIT A

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

1.15

4.6

0.85

4.3

OUTLINE VERSION

SOT411-1

1.65

1.35

0.75

0.60

bpcD

0.55

0.35

(1)

deD

30.4

28.0

27.5

12 2.54

29.9

IEC JEDEC JEITA

w M

0 5 10 mm

scale

(1)

12.2

11.8

1.27

5.08

REFERENCES

10.15

9.85

6.2

1.85

1.65

3.6

2.8

5.8

10.7

9.9

2.4

4.3

1.6

EUROPEAN

PROJECTION

2.1

1.8

0.6

v M

0.25

0.03x45°

ISSUE DATE

98-02-20 02-04-24

(1)

1.43

0.78

Fig 29. Package outline SOT411-1 (DBS23P)

Preliminary data sheet Rev. 01 — 9 September 2008 33 of 39

NXP Semiconductors

TDA8950

2 × 150 W class-D power ampliﬁer

HSOP24: plastic, heatsink small outline package; 24 leads; low stand-off height

pin 1 index

SOT566-3

v M

(A3)

detail X

DIMENSIONS (mm are the original dimensions)

UNIT

Notes

1. Limits per individual lead.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

max.

3.5

3.5 0.35

3.2

OUTLINE

VERSION

SOT566-3

(1)

bpc

+0.08

0.53

−0.04

0.40

IEC JEDEC JEITA

0.32

0.23

16.0

15.8

w M

0 5 10 mm

scale

(2)

13.0

12.6

REFERENCES

1.1

0.9

(2)

6.2

11.1

5.8

10.9

2.9

2.5

14.5

13.9

1.1

0.8

1.7

0.25w0.25

1.5

EUROPEAN

PROJECTION

0.03

2.7

0.07

2.2

ISSUE DATE

03-02-18 03-07-23

8° 0°

Fig 30. Package outline SOT566-3 (HSOP24)

Preliminary data sheet Rev. 01 — 9 September 2008 34 of 39

NXP Semiconductors

15. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note

soldering description”

15.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high densities that come with increased miniaturization.

15.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:

TDA8950

2 × 150 W class-D power ampliﬁer

AN10365 “Surface mount reﬂow

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature proﬁle. Leaded packages, packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

15.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

Preliminary data sheet Rev. 01 — 9 September 2008 35 of 39

NXP Semiconductors

15.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

• Solder paste printing issues including smearing, release, and adjusting the process

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

Table 11. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

< 2.5 235 220 ≥ 2.5 220 220

TDA8950

2 × 150 W class-D power ampliﬁer

higher minimum peak temperatures (see Figure 31) than a SnPb process, thus reducing the process window

window for a mix of large and small components on one board

heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough forthe solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classiﬁed in accordance with

Table 11 and 12

Volume (mm3) < 350 ≥ 350

Table 12. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm3) < 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245 > 2.5 250 245 245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all times.

Studies have shown that small packages reach higher temperatures during reﬂow soldering, see Figure 31.

Preliminary data sheet Rev. 01 — 9 September 2008 36 of 39

NXP Semiconductors

Fig 31. Temperature proﬁles for large and small components

maximum peak temperature

temperature

MSL: Moisture Sensitivity Level

= MSL limit, damage level

minimum peak temperature

= minimum soldering temperature

TDA8950

2 × 150 W class-D power ampliﬁer

peak

temperature

time

001aac844

For further information on temperature proﬁles, refer to Application Note

“Surface mount reﬂow soldering description”

AN10365

16. Revision history

Table 13. Revision history

Document ID Release date Data sheet status Change notice Supersedes

TDA8950_1 20080909 Preliminary data sheet - -

Preliminary data sheet Rev. 01 — 9 September 2008 37 of 39

NXP Semiconductors

17. Legal information

17.1 Data sheet status

TDA8950

2 × 150 W class-D power ampliﬁer

Document status

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development. Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation. Product [short] data sheet Production This document contains the product speciﬁcation.

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Deﬁnitions”. [3] The product status of device(s)described in this document mayhave changedsince this document was publishedand maydiffer incase of multipledevices. Thelatest product status

information is available on the Internet at URL

[1][2]

Product status

17.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in modiﬁcations or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information includedherein and shall have no liabilityfor the consequencesof use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet with thesame product type number(s)and title. Ashort datasheet is intended for quickreference only and shouldnot be relied upon to containdetailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the full data sheet shall prevail.

17.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXPSemiconductors does not give anyrepresentations or warranties, expressed or implied, as tothe accuracy or completeness ofsuch information and shall have no liability for the consequences of use of such information.

Right to make changes — NXP Semiconductors reserves the right tomake changes to information published in this document, including without limitation speciﬁcations and product descriptions, at any time and without notice. This documentsupersedes and replaces all informationsuppliedprior to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental

[3]

http://www.nxp.com.

Deﬁnition

damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in the Absolute MaximumRatings System of IEC 60134)may cause permanent damage tothedevice. Limiting valuesare stress ratingsonly and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercialsale,as published at

http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conﬂict between information in this document and such terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of anylicense under any copyrights, patents or other industrial or intellectual property rights.

Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.

17.4 Trademarks

Notice: Allreferenced brands,product names, service namesand trademarks are the property of their respective owners.

18. Contact information

For more information, please visit: http://www.nxp.com For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

Preliminary data sheet Rev. 01 — 9 September 2008 38 of 39

NXP Semiconductors

19. Contents

TDA8950

2 × 150 W class-D power ampliﬁer

1 General description . . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2

5 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

8 Functional description . . . . . . . . . . . . . . . . . . . 5

8.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

8.2 Pulse width modulation frequency . . . . . . . . . . 8

8.3 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

8.3.1 Thermal protection . . . . . . . . . . . . . . . . . . . . . . 8

8.3.1.1 Thermal FoldBack (TFB) . . . . . . . . . . . . . . . . . 8

8.3.1.2 OverTemperature Protection (OTP) . . . . . . . . . 9

8.3.2 OverCurrent Protection (OCP) . . . . . . . . . . . . . 9

8.3.3 Window Protection (WP). . . . . . . . . . . . . . . . . 10

8.3.4 Supply voltage protections . . . . . . . . . . . . . . . 10

8.4 Differential audio inputs . . . . . . . . . . . . . . . . . 11

9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 12

10 Thermal characteristics. . . . . . . . . . . . . . . . . . 12

11 Static characteristics. . . . . . . . . . . . . . . . . . . . 13

12 Dynamic characteristics . . . . . . . . . . . . . . . . . 14

12.1 Switching characteristics . . . . . . . . . . . . . . . . 14

12.2 Stereo and dual SE application

characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 15

12.3 Mono BTL application characteristics. . . . . . . 16

13 Application information. . . . . . . . . . . . . . . . . . 17

13.1 Mono BTL application. . . . . . . . . . . . . . . . . . . 17

13.2 Pin MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

13.3 Output power estimation. . . . . . . . . . . . . . . . . 17

13.3.1 SE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

13.3.2 Bridge-Tied Load (BTL) . . . . . . . . . . . . . . . . . 18

13.4 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 18

13.5 Noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

13.6 Heatsink requirements . . . . . . . . . . . . . . . . . . 19

13.7 Output current limiting. . . . . . . . . . . . . . . . . . . 20

13.8 Pumping effects . . . . . . . . . . . . . . . . . . . . . . . 21

13.9 Application schematics . . . . . . . . . . . . . . . . . . 21

13.10 Layout and grounding. . . . . . . . . . . . . . . . . . . 23

13.11 Curves measured in reference design . . . . . . 24

14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 33

15 Soldering of SMD packages . . . . . . . . . . . . . . 35

15.1 Introduction to soldering . . . . . . . . . . . . . . . . . 35

15.2 Wave and reﬂow soldering. . . . . . . . . . . . . . . 35

15.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 35

15.4 Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 36

16 Revision history . . . . . . . . . . . . . . . . . . . . . . . 37

17 Legal information . . . . . . . . . . . . . . . . . . . . . . 38

17.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 38

17.2 Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

17.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 38

17.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 38

18 Contact information . . . . . . . . . . . . . . . . . . . . 38

19 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 9 September 2008

Document identifier: TDA8950_1

Philips TDA8950 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1. General description

2. Features

3. Applications

4. Quick reference data

5. Ordering information

6. Block diagram

7. Pinning information

7.1 Pinning

7.2 Pin description

8. Functional description

8.1 General

8.2 Pulse width modulation frequency

8.3 Protections

8.3.1 Thermal protection

8.3.1.1 Thermal FoldBack (TFB)

8.3.1.2 OverTemperature Protection (OTP)

8.3.2 OverCurrent Protection (OCP)

8.3.3 Window Protection (WP)

8.3.4 Supply voltage protections

8.4 Differential audio inputs

9. Limiting values

10. Thermal characteristics

11. Static characteristics

12. Dynamic characteristics

12.1 Switching characteristics

12.2 Stereo and dual SE application characteristics

12.3 Mono BTL application characteristics

13. Application information

13.1 Mono BTL application

13.2 Pin MODE

13.3 Output power estimation

13.3.1 SE

13.3.2 Bridge-Tied Load (BTL)

13.4 External clock

13.5 Noise

13.6 Heatsink requirements

13.7 Output current limiting

13.8 Pumping effects

13.9 Application schematics

13.10 Layout and grounding

13.11 Curves measured in reference design

14. Package outline

15. Soldering of SMD packages

15.1 Introduction to soldering

15.3 Wave soldering

16. Revision history

17. Legal information

17.1 Data sheet status

17.3 Disclaimers

17.4 Trademarks

18. Contact information

19. Contents