Philips TDA5360 User Manual

INTEGRATED CIRCUITS

TDA5360

Pre–Amplifier for Hard Disk Drive with MR-Read / Inductive Write Heads

Objective specification, Revision 2.2 1998 Jul 30

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Philips Semiconductors Objective Specification, Revision 2.2

Pre-Amplifier for Hard Disk Drive with MR-Read / Inductive Write Heads

1 FEATURES 2 APPLICATIONS 3 QUICK REFERENCE DATA 4 DESCRIPTION 5 ORDERING INFORMATION 6 BLOCK DIAGRAM 7 PINOUT DIAGRAM 8 PIN DESCRIPTIONS 9 FUNCTIONAL DESCRIPTION

9.1 ACTIVE READ MODE

9.2 ACTIVE WRITE MODE

9.3 ACTIVE STW MODE

9.4 STANDBY MODE

9.5 SLEEP MODE 10 BIASING OFTHE MR ELEMENT

10.1 MR HEAD RESISTANCE AND TEMPERATURE MEASUREMENT

10.2 FAULT MODE

10.3 SERIAL INTERFACE ADDRESSING

10.4 SERIAL INTERFACE REGISTER BIT ALLOCATION

10.5 SERIAL INTERFACE OPERATIONS

10.6 REGISTERS DESCRIPTION 11 SERIAL INTERFACE TIMING 12 ELECTRICAL PARAMETERS

12.1 DC CHARACTERISTICS

12.2 READ CHARACTERISTICS

12.3 WRITE CHARATERISTICS

12.4 SWITCHING CHARACTERISTICS 13 LIMITING VALUES / RECOMMENDED OPERATION CONDITIONS 14 ABSOLUTE MAXIMUM RATINGS

TDA5360

1998 July 30

Philips Semiconductors Objective Specification, Revision 2.2

Pre-Amplifier for Hard Disk Drive with MR-Read / Inductive Write Heads

1 FEATURES

• 12 channels design for Single-stripe (SAL and GMR) Read / Thin-film Write heads.

• Design target 350 Mbps, for d=0 (16 / 17) rate code.

• Differential Hybrid sense Reader architecture.

• MR element biased by direct programmable constant Power or constant Current.

• Voltage driven Writer architecture.

• MR read / inductive write heads biased at ground level.

• Short rise and fall time with near rail to rail voltage swing.

• Dual power supplies : +5.0 V and -5.0 V.

• On-chip AC couplings eliminate MR head DC and DC offset voltage.

• Programmable 3-wire Serial Port Interface for programming (3.3 V and 5 V TTL / CMOS compatible).

• Extensive programmability of Write current wave overshoot.

• Programmable voltage / current mode write data input.

• Programmable voltage / current mode read data output.

• Programmable Read gain.

• Programmable Reader input impedance.

• Thermal asperity detection with programmable threshold.

• Thermal asperity compression with extensive programmability.

• High spurious-noise rejections.

• Internal Dummy Head available for MR heads protection during switchings.

• FAST mode available for short Write to Read mode transient.

• Sleep, Standby, Active, Servo Track Write, and Test modes available.

• Support servo writing.

• Write / Read Fault detection with fault code read back register and Fault masking capability.

• Low power-supplies fault protections.

• Short Write to Read Recovery, including DC settling.

• On-chip digitizing of Temperature and MR element Resistance value.

• Vendor ID and chip revision register.

• Illegal Multiple Device Selected detection.

• 2 pads CS0 and CS1, hard wired, for separate activation for multiple pre-amplifiers operation.

• Requires one external resistor.

TDA5360

2 APPLICATIONS

Hard Disk Drive (HDD).

1998 July 30

Philips Semiconductors Objective Specification, Revision 2.2

Pre-Amplifier for Hard Disk Drive with MR-Read / Inductive Write Heads

TDA5360

3 QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

DC Supply voltage +4.5 +5 +5.5 V

-4.5 -5 -5.5 V

NF Noise Figure Note 3, Section 14 1.7 1.7 dB IRNV Input Referred Noise

Voltage

Avd Differential gain VIN=1mVpp @ 20 MHz,

Rmr=66Ω; Imr=8mA; 10 MHz<f<100 MHz

=330Ω, Imr=8mA,

Loaddif

0.8 nV/ sqrtHz

50 dB

Rmr=66Ω, GAIN0=0, GAIN1=1;

-3dB frequency bandwidth Rmr=66Ω, Lmr=30 nH

-3dB: without Boost SAL GMR

225 225

MHz MHz

CMR Common Mode Rejection Imr=8mA, Rmr=66Ω,

10MHz<f<200MHz 1 MHz<f< 10MHz f<100 kHz, 1mV input signal

20 40 60

dB dB dB

PSR Power Supply Rejection 200mVpp on Vcc or Vee,

Imr=8mA, Rmr=66Ω,

tr, t

MR(PR)

WR(b-p)

Write Current Rise/Fall times

(-0.8 * Iwr => +0.8 * Iwr)

Programming MR bias current range

Programming Write current

10MHz<f<200MHz 1 MHz<f<10 MHz f<100 kHz

Iwr=50mA; f=20 MHz; LH=75nH, RH=10Ω 0.84 ns

SAL GMR (see note section 10)43

Rext = 10 kΩ 10 50.3 mA

20 40 60

10.2 6 .1

dB dB dB

mA mA

range (base-to-peak)

sclk

Serial interface clock rate 40 MHz

1998 July 30

Philips Semiconductors Objective Specification, Revision 2.2

Pre-Amplifier for Hard Disk Drive with MR-Read / Inductive Write Heads

4 DESCRIPTION

The +/- 5.0 volt pre-amplifier for HDD described here has been designed for 12 terminals, comprised of a SAL or GMR magneto-resistive reader and an inductive thin film writer. In read mode, the device operates as a low noise differential preamplifier which senses resistance changes in the MR element that correspond to flux changes on the disk. In write mode, the circuit operates as a thin film head current switch, driving the inductive element of the head.

The IC incorporates Read amplifiers with programmable gain and HF boosts, Write amplifiers, 3-wires Serial Interface, Digital-to-Analog Converters, Thermal Asperity Detector and Programmable Thermal Asperity Compressor, reference and control circuits which operate on a Dual Supply Voltage of +/-5V (+/-10%).

The Read amplifier has programmable medium input impedance. The DC offset between the two terminals of the MR head is eliminated using on chip AC coupling. The bandwidth can be enhanced by using programmable high frequency gain-boost. Fast settling features are used to keep the transients short. As an option, the Read amplifier may be left biased during writing, so as to reduce the duration of these transients even further.

The Write amplifier has a programmable current overshoot which may be added to the programmable steady state write current.

Fault protection is provided for a variety of read or write unsafe conditions. For added data protection, internal pull up resistors are connected to RWN, CS0, CS1, STWN, WDP and WDN pins and pull down resistors are connected to SEN, SDATA, SCLK, DRN and BFAST pins, to prevent accidental writing due to open lines and to ensure the device will power up in a non-writing condition.

On-chip Digital to Analog converters for MR bias current or power and Write current are programmed via a 3 wire Serial Interface. Head selection, Mode control, Testing and Servo Writing can also be programmed using the serial interface. In Sleep mode, the CMOS serial interface is operationnal. Fig 2 shows the block diagram of the IC. Invalid head select codes disable the writer, select the dummy head and trigger the FLT output.

TDA5360

5 ORDERING INFORMATION

EXTENDED TYPE NUMBER PACKAGE

TDA5360UH bare die TDA5360UK bumped die

Fig.1 Type Number

1998 July 30

Philips Semiconductors Objective Specification, Revision 2.2

Pre-Amplifier for Hard Disk Drive with MR-Read / Inductive Write Heads

6 BLOCK DIAGRAM

hybrid sense

TA handling Rin:2bits

RMR

RFE

hybrid sense

TA handling Rin:2bits

RMR

RFE

HEADMUX

Read Back End

MR BIAS

CURRENT

/ POWER

SETTING

TA CORRECTOR

5 bits

3bits

1.5 bit

THERMAL ASPERITY DETECTOR

Rmr measure temperatue

DIGITIZER

On/Off

d/dt

4 bits

FAULT

DETECTION CODING

SERIAL

INTERFACE

BUFFER

out

V / I

TDA5360

RDp RDn

FLT

SDATA

SCLK

SEN

1998 July 30

voltage driven

voltage

driven

WRITE

boost:1bit

pre-driver

CURRENT

5 bits

WDI MUX

boost:2bits

boost 1 bit

pre-driver

BANDGAP

WDI

V/I

Interface

1 bit

Rext

WDp WDn

Philips Semiconductors Objective Specification, Revision 2.2

Pre-Amplifier for Hard Disk Drive with MR-Read / Inductive Write Heads

7 PAD ARRANGEMENT

DRN

BFAST

WP11

RP11

SDATA

SEN

WDP

RWN

RDN

SHIELDP

SCLK

FLT

WDN

SHIELDN

RDP

REXT

CS0

CS1

WN11

RN11

VCC

RP10

RN10

VCC

WP10

WN10

VCC

GND

TDA5360

WN7

RN9

WN9

RP9

WP9

GND

RP8

RN8

VCC

VEE

WP8

WN8

WP7

RP7

RN7

RN6

RP6

WP6

WN6

WN5

WP5

RP5

RN5

STWN

1998 July 30

RN4

RP4

WP4

RN0

WN0

RP0

WP0

RN1

RP1

WP1

WN1

RP2

WP2

WN2

RN3

RN2

RP3

VEE

WP3

WN3

WN4

Fig.2 TDA5360 pad arrangement pads up.

Philips Semiconductors Objective Specification, Revision 2.2

Pre-Amplifier for Hard Disk Drive with MR-Read / Inductive Write Heads

8 PAD DESCRIPTION

SYMBOL Pin Description

VCC +5V supply GND Ground VEE -5V supply RDP,RDN output Read Data, Differential read signal outputs RWN logic input Read/Write : read = HIGH, write = LOW WDP,WDN input Differential PECL or current mode write data input FLT output

input REXT a 10kΩ external resistor must be connected between REXT and GND SEN logic input Serial Enable line. Active High SCLK logic input Serial Clock line. 40 MHz max. SDATA logic

input/output BFAST logic input Controls reader passband or enables the Imr generator depending on the state

DRN logic input Selects the dummy head or performs a system reset depending on the state of

RP0...RP11 input MR head connections, positive end RN0...RN11 input MR head connections, negative end WP0...WP11 output Write head connections, positive end WN0...WN11 output Write head connections, negative end STWN logic input Set Low for Servo Track Write mode only CS0 logic input Code for Chip ID CS1 logic input Code for Chip ID

In Write mode, a fault is flagged when FLT is high. In Read Mode, a fault is flagged when FLT is low. a 5kΩ external resistor must be connected between FLT and VCC. This pad is used as an input in MDS mode.

Serial Data line. Bi-directional interface

of BFCTL bit from Reg.01

RSTDMY bit from Reg.09

TDA5360

1998 July 30

Philips Semiconductors Objective Specification, Revision 2.2

Pre-Amplifier for Hard Disk Drive with MR-Read / Inductive Write Heads

9 FUNCTIONAL DESCRIPTION

9.1 Active READ mode

Taking RWN high and programming bits MODE0 and MODE1 (see Reg.09) selects the read mode. The Head select inputs, in serial register, select the appropriate head. In read mode, the circuit provides either a constant power bias or a constant current bias that flows from the P to the N side of the MR section of the head. The value of the current/power is programmed in Reg. 02 and is referenced by the external resistor, REXT, which is connected between the REXT pin and GND. The reference voltage on REXT pin is stable over the entire operating temperature range and process. The current or power in the MR element is constant over temperature. The resistance of the MR element, RMR, changes in the presence of a magnetic field and causes a change in the MR head voltage. The circuit acts as a low-noise differential amplifier to sense this voltage change. The read amplifier outputs, RDP and RDN, are in phase with the MRP and MRN head ports.

The read data at pins RDP, RDN can output either voltage or current, depending on how the RVORI bit in Reg.01 is set: LOW or HIGH respectively.

The polarity convention for current mode is :

“positive” => pin with least current flowing

“negative” => pin with most current flowing Write current is not present in read mode under any circumstances; either transient or steady state. The read path includes the following programmable features : Gain programmation (Reg. 02 and Reg. 03) :

- gain only,

- a combination of gain plus differentiator (therefore HF-gain-boost),

- differentiator only. The gain is programmable with step of 3dB between 44dB and 50dB.

Input impedance :

With bits RIN1, RIN0 (Reg.01), the input impedance of the readpath can be programmed from 15 to 30Ω.

Low Pole Frequency :

Bits LFP (Reg.03) allow the programmation of the Low Pole Frequency from 1 to 4 MHz.

Thermal Asperity Detection and Compression :

Thermal Asperity Detector flags an error on FLT line when a thermal disturbance is detected and load the appropriate error code in Reg. 07. The threshold is programmable via Reg. 05.

Thermal Asperity Compressor extracts the signal from the disturbance. Its thresholds levels and frequency response are also programmable with Reg.11.

TDA5360

1998 July 30

Philips Semiconductors Objective Specification, Revision 2.2

Pre-Amplifier for Hard Disk Drive with MR-Read / Inductive Write Heads

9.2 Active WRITE mode

Taking RWN low from an Active READ mode selects the Active WRITE mode. The head select inputs, in a serial register, select the appropriate head.

In write mode the circuit acts as a current switch with write current toggled between the P and N directions of the thinfilm section of the selected head x. The signal polarity is noninverting from WDP, WDN to WPx, WNx.

The write data at pins WDP, WDN could be driven by either a voltage or a current, according to the WVORI bit in Reg.01 (set LOW or HIGH respectively.)

The polarity convention for current mode is :

“positive” => input pin with minimum current flowing

“negative” => input pin with maximum current flowing The writer terminal voltages are driven to GND during read mode to avoid accidental discharges to the disc.

Note that the write mode CAN NOT be selected directly from a sleep or standby condition. The steady state value of the write current is programmed in Reg. 04 and is referenced by the external resistor, REXT,

which is connected between the REXT pin and GND. The reference voltage on REXT pin is stable over the entire operating temperature range and process.

Internal compensation networks are optimized and provided to control the write current shape and settling characteristics based on specified head loads. The value can be programmed in Reg. 04.

TDA5360

9.3 Active STW mode

In Active Read or Active Write mode, only one head in one preamp is selected. A special programmation of Reg. 09, using (STWN = LOW) AND (CS0 = CS1 = HIGH) allows the user to either :

- select one head per preamp (if several preamps are adressed at the same time)

- select one head in one preamp when in read mode but two heads in one preamp when going to write mode. In that case Head x and Head (x+6) will be selected, with x=0...5. Head x is selected via Reg. 00

9.4 STANDBY mode

The standby mode is selected by programming bits MODE0 and MODE1. (see Reg.09) The internal write current source, and MR bias current source are deactivated while RDP, RDN and FLT outputs are in

a high-impedance state so that they can be OR’d in multiple preamplifiers applications. The device is specially designed for reduced dissipation in this mode. Response time from Standby to Active Read mode is much shorter than from Sleep mode to Active Read. The CMM of RDP and RDN is the same as in Sleep or Active mode. (see Note 2)

Internal fault detectors are powered off.

1998 July 30

Philips Semiconductors Objective Specification, Revision 2.2

Pre-Amplifier for Hard Disk Drive with MR-Read / Inductive Write Heads

9.5 SLEEP mode

The sleep mode is selected by programming bits MODE0 and MODE1. (see Reg.09) In Sleep Mode, the IC is accessible via the Serial Interface. All circuits, other than those of the CMOS Serial Interface

and the circuit which forces the data registers to their default values at power up and which fixes the DC level of RDpRDn (required when operating with more than one amplifier), are inactive. Typical static current consumption is less than one mA, depending on the state of the logic pins where internal pull-up or pull-down resistors are connected. Dynamic current consumption during operation of the Serial Interface in the Sleep mode and owing to external activity at the inputs to the Serial Interface is not included. In all Modes including the Sleep mode, data registers can be programmed. Sleep is the default Mode at power-up. Switching to other modes takes less than 0.1 ms.

The CMM of RDP and RDN is the same as in Standby or Active mode. (see Note) Internal fault detectors are powered off.

Note 1 : At power-up, as long as DRN pin is LOW, a reset of the Serial Interface registers occurs. Before any register programmation, the user should first force DRN pin to HIGH in order to exit the reset mode and enable a register programmation. See description of DRN function in (10.6).

Note 2 : As a goal, the CMM of RDP and RDN is identical in all operating modes. The term “high-impedance” here means at least 10 to 20 kOhm from RDP or RDN to an internal CMM voltage reference.

TDA5360

1998 July 30

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