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TDA2579C

Synchronization circuit with synchronized vertical divider system for 60 Hz

Preliminary speciﬁcation File under Integrated Circuits, IC02

Philips Semiconductors

January 1994

Philips Semiconductors Preliminary speciﬁcation

Synchronization circuit with synchronized vertical divider system for 60 Hz

FEATURES Synchronization and horizontal part

• Horizontal sync separator and noise inverter

• Horizontal oscillator

• Horizontal output stage

• Horizontal phase detector (sync to oscillator)

• Triple current source in the phase detector with

automatic selection

• Normal phase detector time constant is increased to fast during the vertical blanking period (external switching for VTR conditions not necessary)

• Slow phase detector time constant and gated sync pulse operation are automatically switched on by an internal sync pulse noise level detection circuit

• Fast phase detector time is switched on for locking

• Time constant externally switchable

• Inhibit of horizontal phase detector and video transmitter

identification circuit during equalizing pulses and vertical sync pulse

• Inhibit of horizontal phase detector during separated vertical sync pulse

• Second phase detector for storage compensation of the line output stage

• 3-level sandcastle pulse generator

• Automatic adaption of the burst key pulse width

• Video transmitter identification circuit

• Stabilizer and supply circuit for starting the horizontal

oscillator and output stage directly from the mains rectifier

• Horizontal output current with constant duty factor value of 55%

• Duty factor of the horizontal output pulse is 55% when the horizontal flyback pulse is absent.

Vertical part

• fV = 60 Hz (M) system

• Vertical synchronization pulse separator without

external components and two integration times

• Zener diode reference voltage source for the vertical sawtooth generator and vertical comparator

• Divider system with three different reset enable windows

• Synchronization is set to 528 divider ratio when no

vertical sync pulse and no video transmitter is identified

• Divider window is forced to wide window when a vertical sync pulse is detected within the window provided by reset divider and end of vertical blanking period, on condition that the voltage on pin 18 is ≤1.2 V

• Divider ratio is 528 (f

• Linear negative-going sawtooth generated via the

divider system (no frequency adjustment)

• Comparator with low DC level feedback signal

• Output stage driver

• fV = 60 Hz identification output combined with mute

function

• Start of vertical blanking is shifted to the start of the pre-equalizing pulses when the divider ratio is between 522 and 528 lines per picture

• Guard circuit which generates the vertical blanking pulse level on the sandcastle output pin 17 when the feedback level at pin 2 is not within the specified limits.

GENERAL DESCRIPTION

The TDA2579C is an integrated circuit generating all requirements for synchronization of its horizontal oscillator and output stage plus those of the vertical part which comprises a divider system, sawtooth generator, comparator and output stage. The TDA2579C is almost identical to the TDA2579B. It is optimized for the M (60 Hz) TV system.

TDA2579C

= 60 Hz) for DC signal on pin 5

ORDERING INFORMATION

EXTENDED TYPE

NUMBER

TDA2579C 18 DIL plastic SOT102

January 1994 2

PINS PIN POSITION MATERIAL CODE

PACKAGE

Philips Semiconductors Preliminary speciﬁcation

Synchronization circuit with synchronized

TDA2579C

vertical divider system for 60 Hz

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

minimum required current for starting horizontal oscillator and output stage

main supply voltage − 12 − V supply current − 70 − mA

Input signals

5-9

sync pulse input amplitude 0.05 − 1V horizontal ﬂyback pulse input current 0.2 1 − mA vertical comparator input voltage

AC (peak-to-peak value) − 0.8 − V DC − 1 − V

Output signals

horizontal output voltage (open collector)

vertical output stage driver (emitter follower)

sandcastle output voltage levels

burst key 9.8 −−V horizontal blanking − 4.5 − V vertical blanking − 2.5 − V

IDEO TRANSMITTER IDENTIFICATION OUTPUT; note 1

V V

output voltage no sync pulse present −−0.32 V output current no sync pulse present −−5mA output voltage sync pulse present;

I11 = 25 mA −−0.5 V

I1 = 1.5 mA 5 −−V

divider ratio <576

6.2 −−mA

− 7.6 − V

Note

1. Open collector loaded with external resistor to positive supply.

January 1994 3

Philips Semiconductors Preliminary speciﬁcation

Synchronization circuit with synchronized vertical divider system for 60 Hz

horizontal

drive

HORIZONTAL

12 V

1

I 6.2 mA

µF

2.7 nF

Ω33 k

Ω4.7 k

101615

SWITCH

SUPPLY

START

CIRCUIT

STABILIZER

OSCILLATOR

HORIZONTAL

Ω6.8 k

OUTPUT

TOO LOW

FLYBACK

REFERENCE

to pin 16

CURRENT

PROTECTION

PULSE

PROTECTION

PHASE

DETECTOR

WIDTH

PULSE

MODULATOR

TDA2579C

MGA791

TDA2579C

input

flyback pulse

100 nF

47 nF

KEY

BURST

VERTICAL

BLANKING

DIVIDER

VIDEO

TRANSMITTER

mute

60 Hz

OUTPUT

SANDCASTLE

GUARD

CIRCUIT

VERTICAL

ZENER

VERTICAL

REFERENCE

IDENTIFICATION

Ω15 k

VERTICAL/

12 V

OUTPUT

VERTICAL

COMPARATOR

43 2 1 17

SAWTOOTH

OSCILLATOR

GENERATOR

4.7 nF

150 nF

Ω150 k

NOISE

DETECTOR

SYNC PULSE

NOISE LEVEL

Ω1.2 k

6.8 µF

68 nF

150 pF

video

signal

Ω1 k

input

SYNC

VERTICAL/

SEPARATOR

HORIZONTAL

Ω5.6 k

2.2µF R =

PHASE

ANTITOP

REFERENCE

DETECTOR

NOISE

INVERTER

Ω22

GATING

DETECTOR

COINCIDENCE

output

sandcastle

drive

vertical

feedback

to vertical deflection

current measuring resistor

Ω220 k

Fig.1 Block diagram.

January 1994 4

Philips Semiconductors Preliminary speciﬁcation

Synchronization circuit with synchronized vertical divider system for 60 Hz

PINNING

SYMBOL PIN DESCRIPTION

OUT

FB 2 vertical feedback input SAW 3 vertical sawtooth generator VDC 4 vertical deﬂection current output VID 5 video signal input CSL 6 slicing level storage capacitor RSL 7 slicing level resistor

GND 9 ground (0 V) V

OUT

FLYB 12 horizontal ﬂyback pulse input MUTE 13 mute output H

SHIFT

OSC

STAB 16 start circuit stabilizer input SC 17 sandcastle output DET 18 coincidence detector output

1 vertical driver output

8 phase detector ϕ

10 main supply voltage (+12 V) 11 horizontal driver output

14 horizontal picture shift capacitor 15 horizontal oscillator frequency

setting

OUT

SAW

VDC

VID

TDA2579C

CSL

RSL

GND

MGA790

Fig.2 Pin configuration.

TDA2579C

DET

STAB

OSC

SHIFT

MUTE

FLYB

OUT

FUNCTIONAL DESCRIPTION

The TDA2579C generates both horizontal and vertical drive signals, a 3-level sandcastle output pulse, a transmitter identification signal and 60 Hz window information.

The horizontal oscillator and horizontal output stage functions are started via the supply current into pin 16. The required current has a typical value of 5 mA which can be taken directly from the mains rectifier. The horizontal output transistor at pin 11 is not conducting until the supply current at pin 16 has reached its typical value. The starting circuit has a hysteresis of approximately 1 mA. The horizontal output current of pin 11 starts at a duty cycle of 60%. All other IC functions are enabled via the main supply voltage on pin 10.

The pin 16 supply system enables slaved synchronized switch mode systems in which the horizontal output signal of the TDA2579C is used as master signal. In such a system the 12 V supply (main supply at pin 10) can be generated by the line output stage.

An internal Zener diode reference voltage is used for the vertical processing part. The IC embodies a synchronized

divider system for generating the vertical sawtooth at pin 3. Thus no vertical frequency adjustment is required.

The circuit operation is restricted to the M (f

= 60 Hz)

system.

Vertical part (pins 1, 2, 3 and 4)

The IC embodies a synchronized divider system for generating the vertical sawtooth at pin 3. The divider system has an internal frequency doubling circuit, thus the horizontal oscillator is operating at its nominal line frequency and one line period equals 2 clock pulses. No vertical frequency adjustment is required due to the divider system. The divider system operates with 3 different reset windows for maximum interference/disturbance protection.

The windows are activated via an up/down counter. The counter increases its value by 1 each time the separated vertical sync pulse is within the window being searched. The count is reduced by 1 when the vertical sync pulse is not present.

The reset of the counter system (clock pulse 0) is at half a line period after the start of the vertical pulse at pin 5.

January 1994 5

Philips Semiconductors Preliminary speciﬁcation

Synchronization circuit with synchronized vertical divider system for 60 Hz

In accordance with the convention for the M system, field one line 1 number 1 starts at the first equalizing pulse, the reset of the divider system is at the start of line 4 for the first field and in the middle of line 265 for the second field.

Divider system

ODE A: LARGE (SEARCH) WINDOW

M Divider ratio between 488 and 576. This mode is valid for the following five conditions:

1. Divider is locking to a new transmitter.

2. Divider ratio found, not being within the narrow window limits.

3. Up/down counter value of the divider system operating in the narrow window mode decreases below count 1.

4. External forced setting. This can be achieved by loading pin 18 with a 220 Ω resistor to earth or by connecting a 3.6 V stabistor diode between pin 18 and ground.

5. A vertical sync pulse was detected within the interval provided by reset divider (at 528) and the end of the vertical blanking while the voltage at pin 18 is ≤1.2 V.

ODE B: NARROW WINDOW

M Divider ratio between 522 and 528. The divider system switches over to this mode when the

up/down counter has reached its maximum value of 12 approved vertical sync pulses in the large window mode. When count 12 is reached the vertical sync pulse is tested for the standard TV-norm being the divider ratio

525. When this value is valid for the 12th vertical pulse, the

up/down counter is reset to 0 and the up/down counter tests for a valid 525 divider ratio. When at the 12th vertical pulse the divider ratio is not equal to n = 525 then the divider system remains in the narrow window mode and remains testing for the standard TV-norm. When the divider operates in this mode and a vertical sync pulse is missing within the window the divider is reset at the end of the window and the counter value is decreased by 1. At a counter value below count 1 the divider system switches over to the large window mode.

ODE C: STANDARD TV-NORM

M Divider ratio 525; fV = 60 Hz. When the up/down counter has reached its maximum

value of 12 in the narrow window mode and the divider ratio equals n = 525 the information applied to the up/down counter is changed such that now the standard divider ratio value is tested and the up/down counter is reset to 0.

TDA2579C

When the up/down counter reaches the value of 14 approved M TV-norm pulses the divider system is changed over to the standard divider ratio mode. In this mode the divider is always reset at the standard value even if the vertical sync pulse is missing. A missed vertical sync pulse decreases the counter value by 1. When the counter reaches the value of 10 the divider system is switched over to the large window mode. The standard TV-norm condition provides maximum protection for video recorders playing tapes with anti-copy guards.

ODE D: NO TV TRANSMITTER FOUND

At pin 18 the voltage level is less than 1.2 V. In this condition, only noise is present and no vertical sync

pulse is detected, the divider is reset to count 528. In this way a stable picture display at normal height is achieved.

ODE E: VIDEO TAPE RECORDERS IN FEATURE MODE

NTSC (M system) 3-speed video tape recorders

It should be noted that some VTRs operating in the picture search mode, generate such distorted pictures that the no TV transmitter detection circuit can be activated as the voltage on pin 18 drops below 1.2 V. This would imply a rolling picture (Mode D). In general VTRs do use a re-inserted vertical pulse in the feature mode. Therefore the divider system has been designed such that the divider is forced to the wide window mode when V18 is below 1.2 V and a vertical sync pulse is detected within the window provided by the reset divider at 528 and the end of the vertical blanking period.

General

The divider system also generates the anti-top-flutter pulse which inhibits the Phase 1 detector during the vertical sync pulse. The width of this pulse depends on the divider mode. For the divider mode A the start is generated at the reset of the divider. In modes B and C the anti-top-flutter pulse starts at the beginning of the first equalizing pulse sequence. The anti-top-flutter ends after the second equalizing pulse sequence.

The vertical blanking pulse is also generated via the divider system. The start is at the reset of the divider while the blanking pulse ends at count 34, the middle of line 21 of field 1 and at the end of line 283 of field 2.

The vertical blanking pulse generated at the sandcastle output pin 17 is made by adding the anti-top-flutter pulse and the blanking pulse. In this way the vertical blanking pulse starts at the beginning of the first equalizing pulse when the divider operates in the B or C mode.

January 1994 6

Philips Semiconductors Preliminary speciﬁcation

Synchronization circuit with synchronized vertical divider system for 60 Hz

Vertical sawtooth

To generate a vertical linear sawtooth voltage a capacitor should be connected to pin 3. The recommended value is 150 nF to 330 nF. The capacitor is charged via an internal current source starting at the reset of the divider system. The voltage on the capacitor is monitored by a comparator which is also activated at reset. When the capacitor has reached a voltage value of 5.0 V the voltage is kept constant until the charging period ends. The charging period width is 26 clock pulses. At clock pulse 26 the comparator is switched off and the capacitor is discharged by an npn transistor current source the value of which can be set by an external resistor connected between pin 4 and ground (pin 9). Pin 4 is connected to a pnp transistor current source which determines the current of the npn current source at pin 3. The pnp current source on pin 4 is connected to an internal Zener diode reference voltage which has a typical voltage of 7.5 V. The recommended operating current range is 10 to 75 µA. The resistor at pin 4 should be 100 to 770 kΩ. By using a double current mirror concept the vertical sawtooth pre-correction voltage can be set to the required value by external components connected between pins 3 and 4 or by superimposing a correction voltage in series with the earth connection of the resistor connected to pin 4. The vertical amplitude is set by the current of pin 4.

Vertical feedback

The vertical feedback voltage of the output stage has to be applied to pin 2. For the normal amplitude adjustment the values are DC = 1 V and AC = 0.8 V (p-p). The low DC voltage value improves the picture bounce behaviour as less parabola compensation is required. Even a DC-coupled feedback circuit is possible.

Vertical guard

The IC also contains a vertical guard circuit. This circuit monitors the vertical feedback signal on pin 2. When the level on pin 2 is below 0.35 V or higher than 1.85 V the guard circuit inserts a continuous voltage level of 2.5 V in the sandcastle output signal of pin 17. This results in blanking of the picture displayed, thus preventing a burnt-in horizontal line.

Vertical driver output

The driver output is at pin 1, it can deliver a drive current of 1.5 mA at 5 V output. The internal impedance is approximately 170 Ω. The output pin is also connected to an internal current source with a sink current of 0.25 mA.

TDA2579C

Integration time of the vertical synchronization pulse separator

The vertical sync separator has two integration times:

• long time; typical 19 µs, valid for 1.8 ≤ V (no noise detected)

• short time; typical 12 µs, valid for noise detected and V18≥ 1.2 V.

When V18 drops below 1.2 V, the integration time is forced back to 19 µs to prevent switching of the divider system to the wide window mode for noise only conditions.

Sync separator, phase detector and TV-station identiﬁcation (pins 5, 6, 7 and 18)

SYNC SEPARATOR

The video input signal is connected to pin 5. The sync separator is designed such that the slicing level is independent of the amplitude of the sync pulse. The black level is measured and stored in the capacitor at pin 7. The slicing level is stored in the capacitor at pin 6. The slicing level value can be chosen by the value of the external resistor connected between pins 6 and 7. The value is given by the formula:

--------------------- -

5.3 RS×

Where RS is the resistor connected between pins 6 and 7 and the top sync levels equals 100%. The recommended resistor value is 5.6 kΩ.

BLACK LEVEL DETECTOR

A gating signal is used for the black level detector. This signal is composed of an internal horizontal reference pulse with a duty factor of 50% and the flyback pulse at pin 12. In this way the TV transmitter identification operates also for all DC conditions at input pin 5 (no video modulation, plain carrier only). During the vertical blanking interval the slicing detector is inhibited by a signal which starts with the anti-top-flutter pulse and ends with the reset of the vertical divider circuit. In this way shift of the slicing level due to the vertical sync signal is reduced and separation of the vertical sync pulse is improved. An internal noise inverter is activated when the video level at pin 5 decreases below 0.7 V.

100 R

value in kΩ().×=

≤ 7.8 V

January 1994 7

Philips Semiconductors Preliminary speciﬁcation

Synchronization circuit with synchronized vertical divider system for 60 Hz

NOISE LEVEL DETECTOR

The IC also embodies a built-in sync pulse noise level detection circuit. This circuit is directly connected to pin 5 and measures the noise level at the middle of the horizontal sync pulse. When a signal-to-noise level (S/N) of ≤19 dB is detected a counter circuit is activated.

S/N

= 20 log

A video input signal is processed as "acceptable noise free" when 12 out of 15 sync pulses have a noise level below 19 dB for successive field periods. The sync pulses are processed during a 15 line width gating period generated by the divider system. The measuring circuit has a built-in noise level hysteresis of approximately 3 dB. The use of a filter of 1 kΩ and 150 pF in front of pin 5 reduces the noise content of the CVBS signal by approximately 6 dB. When the "acceptable noise free" condition is found the phase detector of pin 8 is switched to not gated and normal time constant. When a higher sync pulse noise level is found the phase detector is switched over to slow time constant and gated sync pulse detection. At the same time the integration time of the vertical sync pulse separator is reduced providing V

PHASE DETECTOR (SEE FIG.3)

The phase detector circuit is connected to pin 8. This circuit consists of 3 separate phase detectors which are activated depending on the voltage of pin 18 and the state of the sync pulse noise detection circuit. For normal and fast time constants all three phase detectors are activated during the vertical blanking period, this with the exception of the anti-top-flutter pulse period, and the separated vertical sync pulse time. As a result, phase jumps in the video signal related to the video head, take over of video recorders are quickly restored within the vertical blanking period. At the end of the blanking period the phase detector time constant is increased by a factor of 1.4. In this way there is no requirement for external VTR time constant switching, and thus all station numbers are suitable for signals from VTR, video games or home computers.

Video voltage (black-to-white signal)

----------------------------------------------------------------------------------------------- Noise (RMS)

> 1.2 V.

TDA2579C

For quick locking of a new TV station starting from a noise only signal condition (normal time constant) a special circuit is incorporated. A new TV station which is not locked to the horizontal oscillator will result in a voltage decrease below 0.1 V at pin 18. This will activate a field period counter which switches the phase detector to fast for 3 field periods during the vertical scan period. The horizontal oscillator will now lock to the new TV station and as a result, the voltage on pin 18 will increase to approximately 6.5 V. When pin 18 reaches a level of 1.8 V the mute output transistor of pin 13 is switched off and the divider is set to the large window. In general the mute signal is switched off within 5 ms (C reception of a new TV signal. When the voltage on pin 18 reaches a level of 5 V, usually within 15 ms, the field counter is switched off and the time constant is switched from fast to normal during the vertical scan period.

If the new TV station is weak, the sync noise detector is activated. This will result in a change over of pin 18 voltage from 6.5 V to approximately 10 V. When pin 18 exceeds the level of 7.8 V the phase detector is switched to slow time constant and gated sync pulse condition. The phase detector output current during the blanking period is now reduced from 2 mA to 1.35 mA. When desired, most conditions of the phase detector can also be set by external means in the following way:

• fast time constant, TV transmitter identification circuit not active, connect pin 18 to ground (pin 9)

• fast time constant, TV transmitter identification circuit active, connect a 220 kΩ resistor between pin 18 and ground; this condition can also be set by using a 3.6 V stabistor diode instead of a resistor

• slow time constant (with the exception of the vertical blanking period), connect pin 18 via a 10 kΩ resistor to +12 V (pin 10); in this condition the transmitter identification circuit is not active

• no switching to slow time constant required (transmitter identification circuit active), connect a 6.8 V Zener diode between pin 18 and ground.

= 47 nF) after

January 1994 8

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