Philips TDA2579B-N2 Datasheet

DATA SH EET

Preliminary speciﬁcation File under Integrated Circuits, IC02

September 1990

INTEGRATED CIRCUITS

TDA2579B

Horizontal/vertical synchronization circuit

September 1990 2

Philips Semiconductors Preliminary speciﬁcation

Horizontal/vertical synchronization circuit

TDA2579B

GENERAL DESCRIPTION

The TDA2579B generates and synchronizes horizontal and vertical signals. The device has a 3 level sandcastle output; a transmitter identification signal and also 50/60 Hz identification.

Features

• Horizontal phase detector, (sync to oscillator), sync separator and noise inverter

• Triple current source in the phase detector with automatic selection

• Second phase detector for storage compensation of the horizontal output

• Stabilized direct starting of the horizontal oscillator and output stage from mains supply

• Horizontal output pulse with constant duty cycle value of 29 µs

• Internal vertical sync separator, and two integration selection times

• Divider system with three different reset enable windows

• Synchronization is set to 628 divider ratio when no vertical sync pulses and no video transmitter is identified

• Vertical comparator with a low DC feedback signal

• 50/60 Hz identification output combined with mute function

• Automatic amplitude adjustment for 50 and 60 Hz and blanking pulse duration

• Automatic adaption of the burst-key pulsewidth

PACKAGE OUTLINE

18-lead dual in line; plastic (SOT 102); SOT102-1; 1996 November 19.

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Philips Semiconductors Preliminary speciﬁcation

Horizontal/vertical synchronization circuit TDA2579B

QUICK REFERENCE DATA

PARAMETER CONDITION SYMBOL MIN. TYP. MAX. UNIT

Supply

Minimum required current for starting

horizontal oscillator and output stage I

6.2 −−mA

Main supply voltage V

− 12 − V

Supply current I

− 70 − mA

Input signals

Sync pulse input amplitude V

5(p-p)

0.05 − 1.0 V

Horizontal ﬂyback pulse input current I

− 1 − mA Vertical comparator input signal Voltage AC V

− 0.8 − V Voltage DC V

− 1 − V

Output signals

Horizontal output (open collector)

=25mA V

−−0.5 V Vertical output stage driver

(emitter follower) I

= 1.5 mA V

5 −−V

Sandcastle output levels

V17 burst-key V

9.8 −−V

horizontal blanking V

− 4.5 − V

vertical blanking V

− 2.5 − V Video transmitter identiﬁcation output stage

(open collector loaded with external resistor to positive supply). No sync. pulse present

−−0.5 V

−−5mA Sync pulse present

divider ratio > 576 V

− V

divider ratio < 576 V

− 7.65 − V

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Philips Semiconductors Preliminary speciﬁcation

Horizontal/vertical synchronization circuit TDA2579B

Fig.1 Block diagram.

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Philips Semiconductors Preliminary speciﬁcation

Horizontal/vertical synchronization circuit TDA2579B

FUNCTIONAL DESCRIPTION Vertical part (pins 1,2,3,4)

The IC embodies a synchronized divider system for generating the vertical sawtooth at pin 3. The divider system has an internal frequency doubling circuit, so the horizontal oscillator is working at its normal line frequency and one line period equals 2 clock pulses. Due to the divider system no vertical frequency adjustment is needed. The divider has a discriminator window for automatically switching over from the 60 Hz to 50 Hz system. The divider system operates with 3 different divider reset windows for maximum interference/disturbance protection.

The windows are activated via an up/down counter. The counter increases its counter value by 1 for each time the separated vertical sync pulse is within the searched window. The count is decreased by 1 when the vertical sync pulse is not present.

Large (search) window: divider ratio between 488 and 722 This mode is valid for the following conditions:

1. Divider is looking for a new transmitter.

2. Divider ratio found, not within the narrow window limits.

3. Up/down counter value of the divider system operating in the narrow window mode decreases below count 1.

4. Externally setting. This can be reached by loading pin 18 with a resistor of 220 kΩ to earth or connecting a 3.6 V diode stabistor between pin 18 and ground.

Narrow window: divider ratio between 522-528 (60 Hz) or 622-628 (50 Hz). The divider system switches over to this mode when the up/down counter has reached its maximum value of 12 approved

vertical sync pulses. When the divider operates in this mode and a vertical sync pulse is missing within the window the divider is reset at the end of the window and the counter value is decreased by 1. At a counter value below count 1 the divider system switches over to the large window mode.

Standard TV-norm

When the up/down counter has reached its maximum value of 12 in the narrow window mode, the information applied to the up/down counter is changed such that the standard divider ratio value is tested. When the counter has reached a value of 14 the divider system is changed over to the standard divider ratio mode. In this mode the divider is always reset at the standard value even if the vertical sync pulse is missing. A missed vertical sync pulse decreases the counter value by 1. When the counter reaches the value of 10 the divider system is switched over to the large window mode. The standard TV-norm condition gives maximum protection for video recorders playing tapes with anti-copy guards.

No-TV-transmitter found: (pin 18 < 1.2 V) In this condition, only noise is present, the divider is rest to count 628. In this way a stable picture display at normal height

is achieved.

Video tape recorders in feature mode

It should be noted that some VTRs operating in the feature modes, such as picture search, generate such distorted pictures that the no-TV-transmitter detection circuit can be activated as pin V

drops below 1.2 V. This would imply a rolling picture (see Phase detector, sub paragraph d). In general VTR-machines use a re-inserted vertical sync pulse in the feature mode. Therefore the divider system has been made such that the automatic reset of the divider at count 628 when V18 is below 1.2 V is inhibited when a vertical sync pulse is detected.

The divider system also generates the anti-top-flutter pulse which inhibits the Phase 1 detector during the vertical sync. pulse. The width of this pulse depends on the divider mode. For the divider mode a the start is generated at the reset of the divider. In mode b and c the anti-top-flutter pulse starts at the beginning of the first equalizing pulse.

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Philips Semiconductors Preliminary speciﬁcation

Horizontal/vertical synchronization circuit TDA2579B

The anti-top-flutter pulse ends at count 8 for 50 Hz and count 10 for 60 Hz. The vertical blanking pulse is also generated via the divider system. The start is at the reset of the divider while the pulse ends at count 34 (17 lines) for 60 Hz, and at count 44 (22 lines) for 50 Hz systems. The vertical blanking pulse generated at the sandcastle output pin 17 is made by adding the anti-top-flutter pulse and the blanking pulse. In this way the vertical blanking pulse starts at the beginning of the first equalizing pulse when the divider operates in the b or c mode. For generating a vertical linear sawtooth voltage a capacitor should be connected to pin 3. The recommended value is 150 nF to 330 nF (see Fig.1).

The capacitor is charged via an internal current source starting at the reset of the divider system. The voltage on the capacitor is monitored by a comparator which is activated also at reset. When the capacitor has reached a voltage value of 5.85 V for the 50 Hz system or 4.85 V for the 60 Hz system the voltage is kept constant until the charging period ends. The charge period width is 26 clock pulses. At clock pulse 26 the comparator is switched off and the capacitor is discharged by an npn transistor current source, the value of which can be set by an external resistor between pin 4 and ground (pin 9). Pin 4 is connected to a pnp transistor current source which determines the current of the npn current source at pin 3. The pnp current source on pin 4 is connected to an internal zener diode reference voltage which has a typical voltage of ≈7.5 volts. The recommended operating current range is 10 to 75 µA. The resistance at pin R4 should be 100 to 770 kΩ. By using a double current mirror concept the vertical sawtooth pre-correction can be set on the desired value by means of external components between pin 4 and pin 3, or by connecting the pin 4 resistor to the vertical current measuring resistor of the vertical output stage. The vertical amplitude is set by the current of pin 4. The vertical feedback voltage of the output stage has to be applied to pin 2. For the normal amplitude adjustment the values are DC = 1 V and AC = 0.8 V. Due to the automatic system adaption both values are valid for 50 Hz and 60 Hz.

The low DC voltage value improves the picture bounce behaviour as less parabola compensation is necessary. Even a fully DC coupled feedback circuit is possible.

Vertical guard

The IC also contains a vertical guard circuit. This circuit monitors the vertical feedback signal on pin 2. When the level on pin 2 is below 0.35 V or higher than 1.85 V the guard circuit inserts a continuous level of 2.5 V in the sandcastle output signal of pin 17. This results in the blanking of the picture displayed, thus preventing a burnt-in horizontal line. The guard levels specified refer to the zener diode reference voltage source level.

Driver output

The driver output is at pin 1, it can deliver a drive current of 1.5 mA at 5 V output. The internal impedance is approximately 170 Ω. The output pin is also connected to an internal current source with a sink current of 0.25 mA.

Sync separator, phase detector and TV-station identiﬁcation (pins 5,6,7,8 and 18) The video input signal is connected to pin 5. The sync separator is designed such that the slicing level is independent of

the amplitude of the sync pulse. The black level is measured and stored in the capacitor at pin 7. The slicing level value is stored in the capacitor at pin 6. The slicing level value can be chosen by the value of the external resistor between pins 6 and 7. The value is given by the formula:

Where R

is the resistor between pins 6 and 7 and top sync level equals 100%. The recommended resistor value

is 5.6 kΩ.

5.3 Rs+

---------------------

100 R

value in kΩ()×=

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Philips Semiconductors Preliminary speciﬁcation

Horizontal/vertical synchronization circuit TDA2579B

Black level detector

A gating signal is used for the black level detector. This signal is composed of an internal horizontal reference pulse with a duty factor of 50% and the flyback pulse at pin 12. In this way the TV-transmitter identification operates also for all DC conditions at input pin 5 (no video modulation, plain carrier only). During the frame interval the slicing level detector is inhibited by a signal which starts with the anti-top flutter pulse and ends with the reset vertical divider circuit. In this way shift of the slicing level due to the vertical sync signal is reduced and separation of the vertical sync pulse is improved.

Noise level detector

An internal noise inverter is activated when the video level at pin 5 decreases below 0.7 V. The IC also embodies a built-in sync pulse noise level detection circuit. This circuit is directly connected to pin 5 and measures the noise level at the middle of the horizontal sync pulse. When a signal-to-noise level of 19 dB is detected a counter circuit is activated. A video input signal is processed as “acceptable noise free” when 12 out of 15 sync pulses have a noise level below 19 dB for two successive frame periods. The sync pulses are processed during a 15 line width gating period generated by the divider system. The measuring circuit has a built-in noise level hysteresis of approximately 3 dB. When the “acceptable noise free” condition is found the phase detector of pin 8 is switched to not gated and normal time constant. When a higher sync pulse noise level is found the phase detector is switched over to slow time constant and gated sync pulse phase detection. At the same time the integration time of the vertical sync pulse separator is adapted.

Phase detector

The phase detector circuit is connected to pin 8. This circuit consists of 3 separate phase detectors which are activated depending on the voltage of pin 18 and the state of the sync pulse noise detection circuit. For normal and fast time constants all three phase detectors are activated during the vertical blanking period, this with the exception of the anti-top-flutter pulse period, and the separated vertical sync-pulse time. As a result, phase jumps in the video signal related to the video head, take over of video recorders are quickly restored within the vertical blanking period. At the end of the blanking period the phase director time constant is increased by 1.5 times. In this way there is no requirement for external VTR time constant switching, and so all station numbers are suitable for signals from VTR, video games or home computers. For quick locking of a new TV station starting from a noise only signal condition (normal time constant) a special circuit is incorporated. A new TV station which is not locked to the horizontal oscillator will result in a voltage decrease below

0.1 V at pin 18. This will activate a frame period counter which switches the phase detector to fast for 3 frame periods during the vertical scan period.

The horizontal oscillator will now lock to the new TV-station and as a result, the voltage on pin 18 will increase to approximately 6.5 V. When pin 18 reaches a level of 1.8 V the mute output transistor of pin 13 is switched OFF and the divider is set to the large window. In general the mute signal is switched OFF within 5 ms (pin C

= 47 nF) after reception of a new TV-signal. When the voltage on pin 18 reaches a level of 5 V, usually within 15 ms, the frame counter is switched OFF and the time constant is switched from fast to normal during the vertical scan period.

SN⁄ 20 Log

Video voltage black to white

p-p

()

Noise

rms

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