Page 1
Colour TV Chassis
TCM2.0E
LA
MG8
ME8
Contents Page Contents Page
1. Technical Specifications, Connections, and Chassis
Overview 2
2. Safety Instructions, Warnings, and Notes 5
3. Directions for Use 6
4. Mechanical Instructions 7
5. Service Modes, Error Codes, and Fault Finding 12
6. Block Diagrams, Test Point Overview, and
Waveforms
Wiring Diagram Of Connector 19", 20", and 22" 19
Wiring Diagram Of Connector 26" 19
Block Diagram MT5335 20
7. Circuit Diagrams and PWB Layouts Diagram PWB
Main Power Supply (20") (A)21 22
Main Power Supply (26") (A1)23 25
Standby Power Supply (26") (A2)24 26
SSB: Tuner (B01)27 46-47
SSB: MCU Standby (B02)28 46-47
SSB: DC / DC (B03)29 46-47
SSB: Digital Channel Decoder (B04)30 46-47
SSB: DVBT/ CI Decoder (B05)31 46-47
SSB: Audio Amplifier (B06)32 46-47
SSB: MT5335 Video Processor (B07)33 46-47
SSB: MT5335 Interface USB/HDMI (B08)34 46-47
SSB: Interface LVDS TTL (B09)35 46-47
SSB: Flash Memory (B10)36 46-47
SSB: SDRAM (B11)37 46-47
SSB: MT5335 Interface VGA (B12)38 46-47
SSB: D/A Converter (B13)39 46-47
SSB: HDMI Switch (B14)40 46-47
SSB: I/O Scart (B15)41 46-47
SSB: I/O Side AV, S-Video, Audio (B16)42 46-47
SSB: MT5335 Interface YPbPr & VGA (B17)43 46-47
SSB: I/O VGA (B17)44 46-47
SSB: LVDS Receiver (B18)45 46-47
©
Copyright 2008 Koninklijke Philips Electronics N.V.
All rights reserved. No part of this publication may be reproduced, stored in a
retrieval system or transmitted, in any form or by any means, electronic,
mechanical, photocopying, or otherwise without the prior permission of Philips.
Keyboard Control Panel (E)48 48
Inverter Panel (I)49 50
IR LED Panel (J)51 51
8. Alignments 53
9. Circuit Descriptions, Abbreviation List, and IC Data
Sheets 54
Abbreviation List 55
IC Data Sheets 57
10. Spare Parts List & CTN Overview 65
11. Revision List 65
H_17740_000.eps
240408
Published by JY 0868 BU TV Consumer Care Printed in the Netherlands Subject to modification EN 3122 785 17951
Page 2
SSB: MCU Standby
8 76 543 21
Circuit Diagrams and PWB Layouts
28 TCM2.0E LA 7.
B02 B02
F
KEY_533 5
E
MCU S TANDBY
5V_KEY
S TANDBY
POWER_ON
+3 V3S B
35KEY_5V
3K 3
R8 42
NC
2N7002/NC
Q8 17
R8 19
KEY
D
+3 V3S B_UP
HDMI_INT
C
SHORT_PROTECT
SW_UPDATE_CTL1
HS YNC
L8 11
600R
NC
R8 17
R8 15
4K7
5V_KEY
33 R
NC
R833
5VS B
OIRI
L8 21
R8 13
R83 433R
R83 5 0R
R8 1233R
L8 22
L8 23
5V_KEY
5V_KEY
10K
R142
600R
600R
600R
+3 V3S B_UP
R8 09
10K
600R
1
2
3
4
5
6
7
8
9
R8 07
10K
P8 05
OS CO
OS CI
CEC_IRQ
+3 V3S B_UP
L8 20
600R
C8 71
1U
U8 10
11 6
OS CO VDD
2
OS CI
3
VSS
4
NRS T
5
PWMI
6
RXD/IRQ3
7
TXD/IRQ2
8
HIN
WT6702F
AD0
AD3 /IR
SCL1
SDA1
SCL2
SDA2
VIN
15
14
13
12
11
10
9
C8 23
0.1U
R8 10 10K
R8 24 33 R
R8 20
R8 23
R8 25
R8 14 33 R
CEC
+3 V3SB_UP
LL4148
R8 06
27K
33R
33R
33R
D8 01
C8 76
NC\1000P
C8 75
R8 22
R83 0
R8 05
100R
1000P
STANDBY
3V 3SB_EN
VS YNC
OS CO
33R
33R
CEC_IRQ
100P
C8 19
R8 16
33 R
KEY
OIRI_MCU
20P
C8 21
+3 V3SB_UP
10K
R8 26
X8 00
3 2K7
R8 27
10K
OS CL0_S B
OS DA0_S B
OS CI
20P
C8 22
DV33
+3 V3S B
R22
0R
Q8 10
2N7002
+3 V3SB_UP
C8 20
0.1U
R10
0R
Q8 09
1
2
3
4
OS CL0
2N7002
OS DA0
IS P PORT
P8 02
F
E
D
C
1U
C8 02
OPTION for CEC S ta nd b y Fu nction
BT3 904
OIRI_MCU
Q4
C
E
B
+3 V3S B_UP
+3 V3S B
1U
C8 24
L8 09
120R
RT9166
U8 11
2
C8 09
100U
6V3
0.1U
C8 25
GND
1
3
IN OUT
6V3
0.1U
C8 26
C8 72
100U
5VS B
R144
4K7
GND
R143
10K
B
OIRI
B
A
A
I_17950_022.eps
070508
1 23 4 5 6 78
Page 3
SSB: DC / DC
8 76554 3 21
Circuit Diagrams and PWB Layouts
29 TCM2.0E LA 7.
C
E
GND/ADJ
1
U8 09
ADJ/GND
U8 01
C8 40
0.1U
U8 04
C8 42
DV10
Q8 01
0.1U
C8 65
0.1U
1
R8 57
1K
BT3 904
16V
OUT VIN
VIN
3
VIN
3
+5V
R8 51
10K
C
B
BT3 904
E
100U
R83 1
23
4
4
GND/ADJ
OUT
2
1
4
4
OUT
2
Ba ck Light circu it
R8 48
Q8 02
100R
+5V
R8 47
NC
DIMMING
LL4148
D8 04
C8 27
1U
R8 46
10K
C8 62
0.1U
C8 10
C8 63
LD1117S 12
VIN
U8 03
3
R83 2
0.1U
C8 48
2R7
2R7
DV33 A
C8 70
R8 01
33 0R
100U
6V3
AV33 AV33
C8 18
6V3
47U
GND/ADJ
1
C8 11
6V3
47U
R8 012 NC
R8 013 NC
5V_PW
BL ON/OFF
L8 15
600R
S ELECT
L8 14
600R
+3 V3S B
R8 56 IS FOR 26"
19"20"22" NC
1
2
3
4
R9 NC
R8 52
4K7
5
6
R8 001
7
R8 003
10K
0R
5VS B
12V_IN
R8 56
4K7
ON/OFF
C
Q8 03
B
BT3 904
E
R8 55
4K7
C8 52
1U
R8 54
0R
R8 47K
0.1U
C8 29
Q8 00
A04803
8
D2A
7
D2B
D1A
D1B
5V_OUTS IDE
6
5
C8 54
1U
C8 28
C8 58
1U
0.1U
1
S 2
2
G2
3
S1
4
G1
P8 00
NC
4
4
OUT
2
0.1U
AV25
0.1U
C83 9
0.1U
12V
GND/ADJ
1
L8 02
C83 7
C8 43
200R
R8 02
120R
LD1117S
R8 03
5R1
U8 02
3 V3S B_EN
12V
C8 46
0.1U
AV12 AV12
AV_5V
+5V
AV33
+3 V3S B
C8 44
0.1U
DV33
6R8
R8 04
R88 6
2K7
R91
2K7
2K7
3K9
3K9
R888
R8 90
R8 92
C8 07
0.1U
C8 49
100U
6V3
DV33
4
4
GND/ADJ
OUT
VIN
123
R88 4
0.1U
C8 45
1K
6K2
R88 5
AV9V AV9V
C8 13
100U
16V
R92
2K2
R88 7
2K2
R88 9
4K7
R8 91
4K7
R8 93
4K7
CI_DV18
LD1117S 50
16V
U8 05
47U
LL4148
C8 14
D8 18
VIN
3
0.1U
LL4148
LL4148
LL4148
LL4148
LL4148
4
4
OUT
2
C8 50
D8 09
D8 10
D8 11
D8 12
D8 17
GND/ADJ
R8 94
100K
R8 95
10K
12V
R8 98
B
R8 96
8 K2
R8 97
D8 05
LL4148
D8 06
LL4148
D8 07
LL4148
R8 58
2K7
R8 59
4K7
R8 61
3 K
R8 62
6K8
R8 63
3 K
R8 64
6K8
47K
C
Q8 07
BT3 904
E
68 0R
CI_VCC
DDRV
AV25
LL4148
D8 16
R4
10K
AV_5V
1
C8 15
100U
6V3
0.1U
C8 51
5VS B
R8 006
10K
R2
510R
C
Q8 05
B
BT3 904
E
R5
10K
S HORT_PROTECT
B03 B03
F
DC-DC
P8 04
12V/4A
11
10
9
8
CONNECTOR
C8 59
0.1U
12V_IN
BL_ON/OFF
7
POWER CINCH
6
5
4
3
2
5V/2A
1
5V_PW
0.1U
C8 60
L8 13
3 0R
0R
5V_KEY
R8 65
5VS B
10K
Q8 16
BT3 904
R8 011
R8 010
C
4K7
B
E
ON/OFF
BL_DIM
12V_IN
R8 60
0R
5VS B
E
R46
AV33
R8 50
4K7
R8 49
10K
AV33
+5V
NC
R8 45
1K
R8 44
R8 43
4K7
B
10K
L8 19
L8 18
200R
200R
12V
L14
200R
L15
200R
1000U
C8 00
C8 04
4U7
16V
0.1U
C83 2
0.1U
22K
R8 66
D
D8 08
LL4148
1
BOOT
2
DRIVE
3 6
FB GND
4
VCC
10R
R8 67
U8 07
RT8110
PHAS E
UGATE
LGATE
8
7
5
G2
4
S2
3
G1
2
S 1
1
D13 N03 LT
U8 08
ab ou t 1mm
D2B
D2A
D1B
D1A
GND
5VS B
C8 05
1U
GND
C
B
R1 0R
C
Q8 06
BT3 904
12V
120R
L8 16
100U
16V
B
E
C8 16
C8 67
0.1U
+5V
3 V9
D8 14
R6
10K
R7
10K
C8 69
0.1U
R3
1K
U8 06
MP1411
R8 79
4
IN
1K
1
NC1
9
EN
3
NC2
10
SS
C8 68
0.01U
C83 1
5V_OUTS IDE
GND
1K2
16V
220R
R8 76
L8 04
NC
C83 0
C8 03 4U7
1000U
C8 01
0.1U
R8 72
R8 70
GND
L8 00
15UH
5
6
7
8
10R
C833
NC
NC
C83 4
0.01U
R8 71
R8 69
R8 68
NC
GND
C8 64
0.01U
2
BS
L8 01
D8 03
15UH
S K24
5
S W
7
FB
8
COMP
GND
6
NC
R8 74
4K7
C8 66
120P
C83 5
0.01U
200R
L8 05
200R
L13
R88 2
15K
R883
LD1117S33
+5V
T
6V3
6V3
200R
4U7
51K
U8 00
Z8 05
100U
C8 74
C8 06
47U
16V
4
4
OUT
VIN
2
3
NC/KD108 4-33
C8 41
0.1U
LD1117S33
C8 12
LD1117S 25
C8 17
33 0U
F
12V
C8 53
0.1U
E
D
C
B
A
I_17950_023.eps
8
4 6 7
3 21
A
070508
Page 4
Circuit Diagrams and PWB Layouts
SSB: Digital Channel Decoder
8 76 54 3 21
30 TCM2.0E LA 7.
B04 B04
F
E
D
DIGITAL CHANNEL DECODER
FAT_ IN-
TS 0INDATA7
TS 0INDATA6
TS 0INDATA5
27M
X500
1
2
3
R500
1M
R53 6
33 R
27P
C506
27P
C507
FAT_IN+
8
7
6
NC
L506
XTALI
AVDD33
DVDD12
DVD D33
C527
XTALO
NC
0.22U
C512
C511
1
2
3
4
5
6
7
8
9
10
11
12
C513
C514
0.22U
U502
AVSS33_3
AVSS33_2
XTALI
XTALO
AVDD33 _2
ALC_IN
VDD1.2
DGND1.2
TS DATA 7
TS DATA 6
TS DATA 5
VDD3 .3
1000P
1000P
ADVDD33 _1
48
C510
REFTOP
AVD D33 _3
0.22U
VCMEXT
REFBOT
454647
VCMEXT
REF_TOP
C568
NC/20P
C569
NC/20P
DVDD12
AVDD33
TUNER_S CL
TUNER_S DA
3 7383 9
40414243 44
IN-
IN+
REFBOT
AVDD33 _1
VDD1.2_3
AVSS33_1
DGND1.2_1
TUNER_S CL
TUNER_S DA
VDD3 .3 _3
XTAL_S EL1
XTAL_S EL0
DGND3 .3 _1
VDD3 .3 _2
VDD1.2_2
HOS T_S DA
HOS T_S CL
RF_AGC
IF_AGC
GPIO0
/RES ET
R508
R507
MT513 1_IF_AGC
36
35
34
33
32
31
30
29
28
27
26
25
0R
0R
SIF_ SDA
SIF_ SCL
DV33 DV33
DVD D33
0.1U
C508
DVDD33
DVDD12
R503
R13 4
10K
R150
NC/1K
1K
NC
R502 0R
R504
R501
DV33
R151
NC/10K
R506
IF_AGC
CLOS E TO MT5133
C509
0.047U
R505
100R
10K
0R
OS DA0
OS CL0
R13 6
10K
TUNER_S CL0
TUNER_S DA0
MT5133 -GPIO-AD
MT5133 _RES ET
AV12
AV12
L500
AV33
600R
Digita l 1.8 V Bypass Ca ps
1U
C500
0.1U
C517
C519
0.1U
0.1U
C516
Digita l 3 .3 V Bypass Ca ps
L501
600R
1U
C501
C521
0.1U
0.1U
C523
Ana log 3 .3 V Bypass Ca ps
0.1U
C518
0.1U
C520
DVD D12
0.1U
C515
DVDD33 DV33
0.1U
C522
AVD D33
45
AV33
L502
600R
L503
600R
1U
C502
0.1U
C525
ADVDD33_1
0.1U
C524
0.1U
C526
1U
C503
TS ERR
VDD3 .3 _1
TSS YNC
TS CLK
2223 24
DVDD33
VDD1.2_1
DGND3 .3
DVDD12
TS VAL
TS DATA 0
TS DATA 1
TS DATA 3
TS DATA 2
TS DATA 4
16
1718 192021
R53 5
33 R
TS 0INDATA4
TS 0INDATA3
C
TS 0INDATA2
TS 0INDATA1
TS 0INDATA0
TS 0INVALID
TS 0INS YNC
TS 0INCLK
1
2
3
45
R54233R
33 R R54 3
R54433R
33 R R545
MT5133
8
7
6
13 1415
L510
120R
F
E
D
C
B
120P/NC
C504
120P/NC
C505
B
A
A
I_17950_024.eps
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Page 5
SSB: DVBT/ CI Decoder
8 76554 3 21
Circuit Diagrams and PWB Layouts
31 TCM2.0E LA 7.
B05 B05
DVBT-CI-DECODER
CLOS E TO CI CONNECTOR
CI_VCC CI_VCC CI_VCC
R522
CI_VS 2#
10K
CI_WAIT#
R523
10K
CI_VS 1#
CLOS E TO MT8 295
0.1U
0.1U
0.1U
C539
C538
CLOS E TO MT8 295
C528
CI_POWE#
114
CI_INT
CI_DATA1
U501
A8
A18
47
27P
R509 1M
X501 27M
CI_RES ET#
CI_XTALO
GND
CI_AV33
CI_AV18
CI_XTALI
GND
110
109
108
111
112
113
XTALI
XTALO
AVSS18_PLL
AVDD18 _PLL
AVSS33_XTAL
AVDD 33 _XTAL
A13
WE#
A14
A19
A20
VCC33_2
48
50
53 55575962
52
51
49
C529
CI_OEB
106
107
RES ETB
A21
546056
27P
CI_ALE
105
CI_RB
READY
GND
104
CI_CLE
A22
C535
CI_CLE
103
GND33 _4
A16
58
0.1U
102
CI_ALE
CI_DATA3
A23
A15
101
CI_DATA4
GND33 _3
+5V +5V +5V
R524
10K
0.1U
C560
0.1U
C534
CI_DV33
CI_INT
CI_POCE1#
9997100
CI_DATA5
CI_DATA6
A12
A24
61
CI_RB
98
CI_DATA7
A25
63
CI_DV33
64
NC
VCC33 _4
A7
0.1U
C537
R510
4K7
4K7
CI_WEB
CI_DATA2
CI_CEB
GPIO9
GPIO8
GPIO7
GND18 _1
CD2#
VCC18 _1
BVD1
BVD2
GND33 _2
REG#
INPACK#
WAIT#
VCC33 _3
RES ET
VS 2#
R548
R547
4K7
WP
D10
0.1U
C536
CI_GPIO1
R513
0R
R546
R514 4K7
96
95
94
93
92
91
90
89
88
87
D2
86
85
D1
8 4
D9
83
D0
82
81
D 8
80
A0
79
78
A1
77
76
75
A2
74
73
A3
72
71
A4
70
69
A5
68
67
66
A6
65
L508
600R
CI_DV18 CI_DV33
1U
C554
R511
4K7
CI_GPIO0
DV33
R512
10K
MTK_IC_RES ET
CLOS E TO MT8 295
OPWM1
OPWM2
CI_PDD2
CI_PDD6
CI_PDD7
CI_VCC_EN
CI_VPP33 _EN
CI_VPP5_EN
GND
CI_IOIS 16#
CI_CD2#
CI_D2
CI_OUTDATA2
CI_D1
CI_OUTDATA1
CI_D0
CI_DV18
CI_OUTDATA0
CI_A0
CI_OUTS YNC
CI_A1
CI_OUTVALID
GND
CI_A2
CI_REG#
CI_A3
CI_INPACK#
CI_A4
CI_WAIT#
CI_A5
CI_DV33
CI_RES ET
CI_A6
CI_OUTCLK
CI_DV33 DV33 CI_DV18
LD1117S 18
3
1
2
C540
CI_DV33
6V3
47U
3 .3 V: 0.2W (60mA)
1.8 V: 0.2W
(100mA)
0.1U
0.1U
C541
CI_VCC
CI_VPP
C561
C556
U500
C552
10P
CI_IOIS 16#
1U
CI_D3
CI_D4
CI_D5
CI_D6
CI_D7
CI_CE1#
CI_A10
CI_OE#
CI_A11
CI_A9
CI_A8
CI_A13
CI_A14
CI_WE#
CI_IREQ#
CI_INVALID
CI_INCLK
CI_A12
CI_A7
CI_A6
CI_A5
CI_A4
CI_A3
CI_A2
CI_A1
CI_A0
CI_D0
CI_D1
CI_D2
GND/ADJ
OUT
VIN
4
4
L505
600R
0.1U
C544
NC/0R
R531
CI_AV18 CI_DV18
C545
0.1U
CLOS E TO CI CONNECTOR
+5V
L509
3 0R
R527
47K/NC
S
G
NC\A03 401A
0.1U/NC
C547
C557
6V3
47U
CI_VCC_EN
0.1U
C546
NC\C124ET
R528
10K/NC
C
Q502
B
E
CI_CE1## CI_CE1#
CI_OE##
CI_WE##
D
Q501
NC\0.1U
C558
100R
100R
100R
R549
R550
R551
CI_VCC
100K/NC
R526
P500
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
CI_CD1#
CI_OUTDATA3
CI_OUTDATA4
CI_OUTDATA5
CI_OUTDATA6
CI_OUTDATA7
CI_CE2#
CI_VS 1#
CI_IORD#
CI_IOWR#
CI_INS YNC
CI_INDATA0
CI_INDATA1
CI_INDATA2
CI_INDATA3
CI_INDATA4
CI_INDATA5
CI_INDATA6
CI_INDATA7
CI_VS 2#
CI_RES ET
CI_WAIT#
CI_REG#
CI_OUTVALID
CI_OUTS YNC
CI_OUTDATA0
CI_OUTDATA1
CI_OUTDATA2
CI_CD2#
CI_VCC
CI_VPP
NC\0R
R532
CI_INPACK#
CI_IORD##
CI_IOWR##
CI_VS 2#
100R
100R
100R
R552
R553
R533
CLOSE TO MT8295
L507
C562
C563
C564
C565
C566
C567
CI_VPP
3 0R
C550
100U
6V3
10P
CI_OE#
10P
CI_WE#
10P
CI_IORD#
10P
CI_IOWR#
10P
CI_OUTCLK
10P
L504
600R
C543
CI_VCC
R519
NC\10K
R518
10K
0.1U
CI_IOIS 16#
CI_AV33 CI_DV33
0.1U
C542
CI_IREQ#
0.1U
C533
R525
NC
R520
10K
CI_CD1# CI_CD2#
0.1U
C559
0.1U
C531
C532
R521
10K
C1
1U
F
CI_VCC
R517
NC\10K
CI_INPACK#
R516
10K
E
1U
C551
CLOS E TO MT8 295
10P
128
GPIO14
VCC33_1
33
TS _S YNCO
127
3 4
R538
33 R
CI_TS _S YNCO
126
125
GPIO13
GND33 _5
CE1#
D15
36
35 37 39
TS _D ATAO
R539
33 R
TS _S YNCO
CE2#
C530
CI_TS _DATAO
124
TS _DATAO
A10
TS _CKO
R54033R
TS _VALIDO
120R
L511
CI_DV33
CI_TS _VALIDO
CI_TS _CKO
122
121
123
TS _CKO
TS _VALIDO
VS 1#
OE#
38
404245
R541
33 R
5V-TUNER-ON/OF
5V-TUNER-INPUT
CI_PDD3
CI_PDD4
120
119
116
117
118
GPIO10
GPIO12
GPIO11
CI_OEB
VCC33 _5
A11
GND33 _1
IORD#
A9
IOWR#
414446
43
CI_PDD5
115
CI_DATA0
A17
D
GND
RES ET_N
T
PWRDN_EN
Z501
Z502
CI_GPIO14
T
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
GPIO0
2
GPIO1
3
GPIO2
4
GPIO3
5
VCC33
6
T0CLK_I_
7
T0S YNC_I_
8
T0VALID_I_
9
T0DATA0_I_
GND33
T0DATA1_I_
T0DATA2_I_
T0DATA3 _I_
T0DATA4_I_
VCC18
T0DATA5_I_
T0DATA6_I_
T0DATA7_I_
GPIO4
GPIO5
GPIO6
GND18
CD1#
D3
D11
D4
D12
D5
D13
D6
D14
D7
C
CI_GPIO0
CI_GPIO1
HDMIED_WP
HPDIN
CI_DV33
TS 0INCLK
TS 0INS YNC
TS 0INVALID
TS 0I N DATA 0
GND
TS 0I N DATA 1
TS 0I N DATA 2
TS 0I N DATA 3
TS 0I N DATA 4
CI_DV18
TS 0I N DATA 5
TS 0I N DATA 6
B
TS 0I N DATA 7
HDMI_S EL
YPBPR_S W_IN
GND
CI_CD1#
CI_D3
CI_OUTDATA3
CI_D4
CI_OUTDATA4
CI_D5
CI_OUTDATA5
CI_D6
CI_OUTDATA6
CI_D7
F
E
D
C
B
MT8295
CI_IOWR##
CI_IORD##
CI_A11
CI_A9
GND
CI_OE##
CI_INS YNC
CI_DV33
CI_VS 1#
CI_OUTDATA7
CI_CE2#
CI_CE1##
A
CI_A10
CI_DV33
CI_INDATA3
CI_INDATA4
CI_INDATA0
CI_A13
CI_A8
CI_IREQ#
CI_A14
CI_INDATA1
CI_INVALID
GND
CI_INDATA7
CI_A7
CI_WE##
CI_INDATA5
CI_INDATA6
CI_A12
CI_INCLK
100R
R515
CI_INDATA2
I_17950_025.eps
8
4 6 7
3 21
A
070508
Page 6
SSB: Audio Amplifier
Circuit Diagrams and PWB Layouts
32 TCM2.0E LA 7.
B06 B06
AUDIO AMPLIFIER
AL1O
S PEAK-OUTL
AR1O
S PEAK-OUTR
NC
0R
R622
R621
R617
NC
R618
0R
R624
100K
R623
100K
Y600
PGND
P600
2
3
1
1
2
U600 TDA7266
OUT1-
VCC1
IN1
NC1
MUTE
5
2R7
6
MUTE
R648
S TBY
7
SS
4
R620
2K2
2K2
R619
L-
GND
GND
L_OUT
C610
4700P
C609
C612
4700P
OUT1+
1
C608
12V
2
1U
2R7
1U
L601
3
0.1U
R603
L600
200R
200R
C611
L+
PW_GND
8
PGND
R+
GND
4
S _GND
9
16V
NC2
10
NC3
11
C607
1000U
IN2
12
0.1U
C615
VCC2
13
OUT2-
14
OUT2+
15
R_OUT
GND
GND
R-
R600
0R
Near the P502
R602
0R
R601
0R
Near the P502
PGND
PGND
12V
220R
R63 9
R641
R643
4K7
4K7
BT3 906
B
PGND
Q607
R640
16V
GND
BT3 906
4K7
100U
C602
R642
1K
GND
AMP_MUTE
LL4148
D600
R625
4K7
D601
LL4148
HW_MUTE
R644
10K
BT3904
Q602
B
R630
10K
12V
C
E
GND
R63 2
10K
R627
R647
10K
10K
GND
R628
10K
22U
C606
16V
SS
NC
R63 1
MUTE
R659
100R
R629
100R
R656
100R
R626
100R
C600
33 00P
GND GND
33 00P
C601
0R/NC
E
C
B
E
Q608
C
L602
L603
R63 6 0R/NC
R63 7
100U
600R
600R
16V
C616
HP_L
HP_R
R+
R_OUT
GND
EAR
1
P601
2
C614
C613
4700P/NC
3
9
8
7
6
L+
L_OUT
5
4
4700P/NC
GND
C617
100U 16V
I_17950_026.eps
070508
Page 7
Circuit Diagrams and PWB Layouts
SSB: MT5335 Video Processor
8 76 54 3 21
33 TCM2.0E LA 7.
B07 B07
MT533 5 VIDEO PROCESS OR
DV33
10P
NC
60M
R211
X200
TXC
OXTALO
10P
C222
F
E
D
OPWM1
MTK_IC_RES ET
AVDD33 _XTAL
KEY
DV33
HDMI_INT
R44
10K
R202
E
10K
BT3904
R200
B
Q200
OS DA1
OS CL1
BL_DIM
OPWM2
OXTALO
OXTALI
AVC C_S RV
18 0K
PANEL_S LT
S CART_FS _IN
PWRDET
AVD D33_REG
C_XREG
ORES ET#
S W_UPDATE_CTL
R203
10K
C
OS DA0
OS CL0
KEY_533 5
204
205
63
62
191
202
203
146
143
144
147
145
152
151
150
149
148
88
87
72
MT5335PKU
U203
OS DA0
OS CL0
OS DA1
OS CL1
OPWM0
OPWM1
OPWM2
VCXO
XTALO
XTALI
AVD D33_S RV
AVD D33_XTAL
ADIN4
ADIN3
ADIN2
ADIN1
ADIN0
AVD D33_REG
C_XREG
OPWRS B
DV33
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8
GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13
OPCTRL0
OPCTRL1
OPCTRL2
OPCTRL3
OPCTRL4
OPCTRL5 ORES ET_
R201
4K7
207
208
209
59
60
210
211
212
214
215
216
92
91
76
75
90
8 971
CI_PDD3
CI_PDD4
CI_PDD5
CI_PDD6
CI_PDD7
CI_POWE#
CI_OEB
CI_ALE
CI_CLE
MT5133 _RES ET
POWER_ON
LV DSVDD_EN
CI_INT
AMP_MUTE
BL_ON/OFF
EDID_PRT
DV33
R204
10K
C
DV33
C201
220U
R206
1K
C_XREG
PWRDET
10R
R207
D200
16V
R208
220R
LL4148
C203
4U7
R210
47K
Adjus t the power on timing
R209
B
1K
ORES ET#
C
Q202
BT3904
E
OXTALI
C221
R205
10K
B
CEC
E
L214
0.8 2UH
C223
F
1000P
E
D
Q201
BT3 904
DV33
Z959
Z958
OS CL0
OS DA0
T
Z956
T
R216
R215
T
4K7
4K7
8
VCC
7
WC
6
S CL
5
S DA
T
Z957
M24C16MN
IIC ADDRESS "A0"
U205
E0/NC
E1/NC
E2/NC
VSS
1
2
3
Z960
T
4
0.1U
C247
DV33
C
R38
10K
R3 6
EDID_PRT
B
R3 7
10K
NC
R3 9
4K7
C
Q1
B
E
BT3904
R40
NC\0R
B
R214
10K
C
R217
33 R
Q206
C124ET
E
DV33
DV33
L210
600R
L211
600R
1U
C204
1U
C206
AVCC_S RV
AVDD33 _XTAL
0.1U
C224
0.1U
C225
C
B
DV33
L212
600R
1U
C205
AVD D33_REG
0.1U
C226
A
A
I_17950_027.eps
1 23 4 5 6 78
070508
Page 8
Circuit Diagrams and PWB Layouts
SSB: MT5335 Interface USB/HDMI
34 TCM2.0E LA 7.
B08 B08
MT533 5 INTERFACE - US B, HDMI
AV1 2
AV12
C228
1U
L215
600R
1U
C207
AVDD12_PLL
C249
0.01U
C250
0.1U
US B_VRT
US B_DUS B_D+
AVD D33_USB
AVDD12_US B
68
65
66
67
69
157
158
U203
US B_VRT
US B_DM
US B_DP
AVD D33_USB
AVDD12_US B
TP0
TN0
AVDD12_KADCPLL
AVDD12_TVDPLL
AVDD12_KHDMIPLL
AVDD12_KAPLL
AVDD12_S YS PLL
AVDD12_KDMPLL
AVDD12_DTDPLL
160
155
153
161
159
156
154
AVDD12_PLL
AVDD12_PLL
AVDD12_PLL
AVDD12_PLL
AVDD12_PLL
AVDD12_PLL
AVDD12_PLL
AV33
GND
MT533 5PKU
AV12
AV33
AV12
L216
600R
L217
600R
AVD D33 _USB
1U
C208
AVDD12_US B
1U
C210
C251
0.1U
C252
0.1U
GND
GND
US B_VRT
R218
5K1
AV25
SIFP
SIFN
TS _VALIDO
TS _CKO
RX0_CB
RX0_C
RX0_0B
RX0_0
RX0_1B
RX0_1
RX0_2B
RX0_2
164
166
167
194
79
80
81
82
83
84
85
86
U20 3
SIFP
SIFN
AF
TUNER_CLK
MT533 5PKU
U203
RX0_CB
RX0_C
RX0_0B
RX0_0
RX0_1B
RX0_1
RX0_2B
RX0_2
AVDD25_S ADC
AVSS 25_S ADC
RF_AGC
IF_AGC TUNER_DATA
EXT_RES
OPWR0_5V
AVD D33_HDMI
AVDD12_CVCC
163
165
TS _ DATA O
193
TS _S YNCO
192 195
77
73
78
AVD D33_H
74
AVDD12_CVCC
AVDD25_S ADC
GND
HDMI_5V
AV25
AV33
AV33
HDMI_5V
AV12
AV1 2
C229
1U
C23 0
1U
L218
600R
L219
L220
600R
600R
1U
C211
1U
C212
AVDD25_S ADC
AVD D33_H
AVDD12_CVCC
0.01U
C255
0.1U
C253
GND
C254
0.1U
GND
GND
MT533 5PKU
1U
0.1U
C213
GND
I_17950_028.eps
070508
C248
Page 9
SSB: Interface LVDS TTL
Circuit Diagrams and PWB Layouts
35 TCM2.0E LA 7.
B09 B09
INTERFACE LVDS TTL
A0N
A0P
A1N
A1P
A2N
A2P
CK1N
CK1P
A3 N
A3 P
A4N
A4P
A5N
A5P
A6N
A6P
CK2N
CK2P
A7N
A7P
Footprint is ACM-2012
GND
AV33
AV33
MT533 5PKU
GND
GND
R222
0R
R223
0R
L200
EXC24C
A0N
14
A0P
2
L201
EXC24C
A1N
14
A1P
2
L202
EXC24C
A2N
14
A2P
2
L203
EXC24C
14
CK1P
2
L204
EXC24C
A3 N
14
A3 P
2
L205
EXC24C
A4N
14
A4P
2
L206
EXC24C
A5N
14
A5P
2
L207
EXC24C
A6N
14
A6P
2
L208
CK2N
CK2P CLK22+
EXC24C
14
2
L209
EXC24C
A7N
14
A7P
2
3
3
3
3
3
3
3
3
3
3
AN00
AP00
AN11
AP11
AN22
AP22
CLK11+
AN33
AP33
AN44
AP44
AN55
AP55
AN66
AP66
AN77
AP77
CLK11- CK1N
C3 28
C3 29
CLK22-
C3 20
C3 21
C3 22
C3 23
C3 24
C3 25
C3 26
C3 27
C33 0
C33 1
C33 2
C333
C33 4
C33 5
C33 6
C33 7
C338
C33 9
10P
10P
GND
10P
10P
10P
10P
10P
10P
10P
10P
10P
10P
10P
10P
10P
10P
10P
10P
10P
10P
GND
GND
GND
GND
GND
GND
GND
GND
U203
244
A0N
243
A0P
242
A2N
241
A2P
240
CK1N
23 9
CK1P
23 7
A3 N
23 6
A3 P
23 5
A4N
23 4
A4P
233
A5N
23 2
A5P
23 1
A6N
23 0
A6P
228
A7N
227
A7P
226
CK2N
225
CK2P
224
A8 N
223
A8 P
222
A9N
221
A9P
CLK11+
R213 0R
0R
R212
PANEL_CTL1
PANEL_CTL2
GND
AP00
AP11
AP22
AP33
AP44
AP55
AP66
CLK22+
AP77
AVD D33_LVDSA
AVD D33_LVDSB
AVD D33_LVDSC
AVD D33_VPLL
TP2
TN2
220
229
238
217
218
219
AVD D33_LVDS
AVD D33_LVDS
AVD D33_LVDS
AVD D33_VPLL
CI_POCE1#
P202
39
37
35
33
31
29 3 0
27
25
23
21
19
17
15
13
11
9
7
5
3
40
AN00
38
AN11
3 6
AN22
34
32
CLK11-
AN33
28
26
24
22
20
AN44
AN55
18
AN66
16
CLK22-
14
AN77
12
10
8
6
4
12
VDD_PANEL
C260
0.1U
GND
12V
5V_OUTS IDE
+5V
R25 NC
12V
3 5KEY_5V
PANEL_S LT
NC R26
L23 2
R23 2
NC
R26 FOR 19" 22" PANEL
R25 FOR OTHER +5V S UPPLY PANEL
NC/3 0R
P209
5
3
6
4
12
L233
NC/3 0R
LVD SVDD_EN
AV33
AV33
AV33
AV33
16V
GND
1U
1U
220U
C23 1
C220
C202
L221
600R
L222
600R
R229
750R
GND
4
6
C258
0.1U
1 2
3
5
P204
LV DS OUT
R219
10K
C
Q204
B
C214
C143 ZT
E
GND
AVD D33_LVDS
1U
AVD D33_VPLL
1U
C23 2
R221
100K
R23 1
100K
1U
C209
Z210
T
C256
0.1U
C257
0.1U
6K8
R228
120R
R23 0
DV33
1
S 1
2
S2
3
S3
G
DV33
GND
Q203
AO445 9
C259
0.1U
GND
R224
1K
R225
3 90R
R226
3 90R
R227
390R
8
D1
7
D2
6
D3
5 4
D4
C261
0.1U
Z212
T
VDD_PANEL
GND
GND
I_17950_029.eps
070508
Page 10
SSB: Flash Memory
Circuit Diagrams and PWB Layouts
5 4 3 2 1
36 TCM2.0E LA 7.
B10 B10
D
C
B
FLAS H MEMORY
252
251
250
249
245
248
MT533 5PKU
OIRI_MT533 5
AV33
GND
1
2
3
4
R233
U0TX
U0RX
RS -23 2
10K
POCE0#
POOE#
PDD0
PDD1
CI_RB
CI_PDD2
R23 4
10K
U203
POCE0_
POOE_
PDD0
PDD1
PAR B _
PDD2
BT3 904
P201
DV33
L223
U0RX
U0TX
OIRI
JTMS
JTRS T_
JTCK
JTDO
JTDI
95
94
93
253
1
256
255
254
U0RX
U0TX
OIRI_MT533 5
JTMS
JTRS T#
JTCK
JTDO
JTDI
600R
C240
POCE0#
PDD0
1U
GND
R28 9
10K
R245
0R
+5V
C
Q3
E
R8 9
4K7
R90
10K
B
OIRI
GND
US B_D-
US B_D+
1
1
+5V
C006
100U
6V3
0.1U
C007
GND
0R
R2011
R2012
0R
1
2
3
4
U202
11 6
HOLD# S CLK
2
VCC
3
NC
4
PO2
5
PO1
6
PO0
7
CS #
8
SO
WP#/ACC
PO6
PO5
PO4
PO3
GND
15
S I
14
13
12
11
10
9
POOE#
PDD1
DV33
R246
4K7
FRES ET#
MX25L3 205
GND
JTDO
DV33
JTRS T#
JTDI
JTMS
JTCK
33 R
R23 9
R270
10K
DV33
7
6
8
1K
R23 5
1
3
2
45
TVTREF#1
JTAG_DBGRQ
JTAG_DBGACK
4
6
8
10
12
14
16
18
20
1 2
3
5
7
9
11
13
15
17
19
P203
R23 6
10K
R238
R23 7
10K
10K
P200
R8 7
EZJZ1V270RA
2
GND
2
R88
EZJZ1V270RA
GND
0.1U
C262
GND
0.1U
C263
C264
0.1U
1U
C234
1U
C235
DV1 0
D
C
GND
B
DV33
R240
OPWM2
DV1 0
U203
14
VCCK
48
VCCK1
57
VCCK2
58
VCCK3
61
VCCK4
70
DVDD10
162
DVDD10_1
213
VCCK6
206
VCCK5
246
VCCK7
A
VCC2IO
VCC2IO1
VCC2IO2
VCC2IO3
VCC2IO4
VCC2IO5
VCC2IO6
VCC2IO7
VCC2IO8
VCC2IO9
VCC3 IO_3 _2
VCC3 IO_3 _1
VCC3 IO_3
E-PAD
10
12
16
18
27
3 0
52
54
55
56
64
197
247
257
DDRV_IC
DV33
GND
R244
4K7
Trap MODE
NORMAL MODE
ICE MODE
TRAP MODE
CORE RES ET 1 US
AOBCK
AOLRCK
4K7
R241
4K7
R242
NC\4K7
GND
OPWM2 AOBLK AOLRCK
0
0
OPCTRL5
00
0
0
1
OPCTRL4
1
1U
C237
DDRV_IC
GND
1U
C238
GND
1U
C236
1U
C239
C265
C279
0.1U
0.1U
C266
C278
0.1U
0.1U
C267
0.1U
C277
0.1U
C270
0.1U
C276
0.1U
C269
0.1U
C275
0.1U
C268
C274
0.1U
0.1U
C272
C273
0.1U
0.1U
0.1U
C271
A
MT533 5PKU
I_17950_03 0.eps
1 23 4 5
070508
Page 11
SSB: SDRAM
Circuit Diagrams and PWB Layouts
37 TCM2.0E LA 7.
B11 B11
RDQS0
RDQM0
RDQ0
RDQ1
RDQ2
RDQ3
RDQ4
RDQ5
RDQ6
RDQ7
RDQS1
RDQM1
RDQ8
RDQ9
RDQ10
RDQ11
RDQ12
RDQ13
RDQ14
RDQ15
MEM_VREF
RCS #
MT5335PKU
6V3
S DRAM
U203
11
RDQS0
13
RDQM0
9
RDQ0
8
RDQ1
7
RDQ2
6
RDQ3
5
RDQ4
4
RDQ5
3
RDQ6
2
RDQ7
17
RDQS1
15
RDQM1
19
RDQ8
20
RDQ9
21
RDQ10
22
RDQ11
23
RDQ12
24
RDQ13
25
RDQ14
26
RDQ15
53
RVREF 0
46
RCS _
MEM_ADDR12
MEM_ADDR11
MEM_ADDR9
MEM_ADDR8
MEM_ADDR7
MEM_ADDR6
MEM_ADDR5
MEM_ADDR4
MEM_WE#
MEM_CAS#
MEM_RAS#
MEM_CS#
MEM_BA0
MEM_BA1
MEM_ADDR10
MEM_ADDR0
MEM_ADDR1
MEM_ADDR2
MEM_ADDR3
+5V
C200
100U
GND
RA0
RA7
RWE_
RBA0
RA6
RBA1
RA5
RRAS_
RA8
RA10
RA4
RCAS_
RA12
RCKE
RA11
RA9
RA3
RA1
RA2
RCLK0_
RCLK0
R275
47R
1
2
3
45
R276
47R
1
2
3
45
R277
47R
1
2
3
45
R278
47R
1
2
3
45
R279
47R
1
2
3
45
U201
LD1117S
VIN
3
0.1U
C3 03
RA0
47
RA7
3 6
RWE#
40
RBA0
43
RA6
3 7
RBA1
44
RA5
38
RRAS#
42
RA8
3 5
RA10
45
RA4
3 9
RCAS#
41
RA12
3 2
RCKE
3 1
RA11
33
RA9
3 4
RA3
51
RA1
49
RA2
50
RCLK0#
28
RCLK0
29
8
7
6
RA12
RA11
RA9
RA8
8
7
6
RA7
RA6
RA5
RA4
RWE#
8
7
RCAS #
RRAS#
6
RCS #
8
7
RBA0
RBA1
6
RA10
8
7
6
RA0
RA1
RA2
RA3
4
4
GND/ADJ
OUT
1
2
R262
110R
R263
120R
GND
1.25 x (1+120/110) = 2.6V
RCKE
RCLK0
RCLK0#
22R
22R
22R
R258
R259
R260
MEM_ADDR13
MEM_CLKEN
MEM_CLK0
R261
MEM_CLK0#
MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ8
MEM_DQ9
MEM_DQ10
MEM_DQ11
MEM_DQ12
MEM_DQ13
MEM_DQ14
MEM_DQ15
DDRV_IC
100R
GND
10
11
13
54
56
57
59
60
62
63
65
14
17
19
25
43
50
53
18
33
15
55
61
3 4
48
66
12
52
58
64
2
4
5
7
8
1
3
9
6
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
NC
NC1
NC2
NC3
NC4
NC5
NC6
VDD
VDD1
VDD2
VDDQ
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VSS
VSS 2
VSS 1
VSS Q1
VSS Q2
VSS Q
VSS Q3
VSS Q4
3 2M* 16DDR
U204
A10/AP
VREF
LDQS
UDQS
UDM
CLK
CLK
CKE
RAS
CAS
LDM
MEM_VREF
49
MEM_ADDR0
29
A0
30
31
32
35
36
37
38
39
40
28
41
42
45
46
44
24
23
22
21
16
51
20
47
26
27
L224
600R
MEM_ADDR1
MEM_ADDR2
MEM_ADDR3
MEM_ADDR4
MEM_ADDR5
MEM_ADDR6
MEM_ADDR7
MEM_ADDR8
MEM_ADDR9
MEM_ADDR10
MEM_ADDR11
MEM_ADDR12
MEM_CLK0
MEM_CLK0#
MEM_CLKEN
MEM_CS #
MEM_RAS#
MEM_CAS#
MEM_WE#
MEM_DQS0
MEM_DQS1
MEM_DQM0
MEM_DQM1
MEM_BA0
MEM_BA1
R265
0R
0R
R264
0R
R266
RDQ0
RDQ1
RDQ2
RDQ3
RDQ4
RDQ5
RDQ6
RDQ7
RDQS 0
RDQM0
RDQM1
RDQS 1
RDQ11
RDQ10
RDQ9
RDQ8
R271
47R
1
2
3
45
R272
47R
1
2
3
45
R273
47R
1
3 6
47R
47R
47R
47R
R248
R249
R250
R251
8
7
6
8
7
6
MEM_DQS 0
MEM_DQM0
MEM_DQM1
MEM_DQS1
8
7 2
5 4
MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ11
MEM_DQ10
MEM_DQ9
MEM_DQ8
R287
75R
1
2
3
8
7
6
45
R286
75R
1
2
3
8
7
6
45
R254
75R
R255
75R
R256
75R
R257
75R
R285
75R
1
2
3
8
7
6
45
DDRV
GND
L225
R267
100K
600R
MEM_VREF
0.1U
R274
47R
RDQ15
RDQ14
C3 06
C3 05
C3 04
0.1U
0.1U
RDQ13
RDQ12
1
2
3
45
MEM_DQ15
8
MEM_DQ14
7
MEM_DQ13
6
MEM_DQ12
R288
75R
1
2
3
8
7
6
45
GND
47U
6V3
C217
NC3
NC2
NC1
REFEN VCNTL
RT9199
GND
VOUT
U200
VIN
1
2
3 6
L226
600R
4
8
7
5
220U
R268
100K
C3 14
16V
R269
1K
GND
A1
A2
A3
A4
A5
A6
A7
A8
A9
A11
A12
CS
WE
BA0
BA1
+5V
+1V3D
+1V3D
R280
MEM_CS#
MEM_RAS #
MEM_CAS #
MEM_WE#
DDRV_IC
MEM_ADDR10
MEM_BA1
16V
0.1U
0.1U
C281
C280
0.1U
0.1U
C283
C282
0.1U
0.1U
C284
0.1U
C285
0.1U
C287
C286
C3 15
100U
6V3
C3 49
220U
GND
MEM_VREF
+1V3D
MEM_BA0
MEM_ADDR7
MEM_ADDR6
MEM_ADDR5
MEM_ADDR4
DDRV
DDRV
C3 49 IS CLOS E TO PIN33 OF DDR
L213
600R
MEM_CLKEN
4U7
0.1U
C3 02
C215
C3 00
+1V3D
0.1U
GND
1U
0.1U
C216
C3 01
C296
0.1U
C297
0.1U
C299
0.1U
0.1U
C298
GND
MEM_ADDR12
MEM_ADDR11
MEM_ADDR9
MEM_ADDR8
MEM_ADDR13
MEM_ADDR3
MEM_ADDR2
1U
C295
0.1U
C3 16
C294
0.1U
C292
0.1U
0.1U
0.1U
C288
C293
0.1U
C291
C290
0.1U
0.1U
C289
MEM_ADDR1
MEM_ADDR0
75R
1
2
3
8
7
6
45
R281
75R
1
2
3
8
7
6
45
R282
75R
1
2
3
8
7
6
45
R252
75R
R283
75R
1
2
3
8
7
6
45
R253
75R
R284
75R
1
2
3
8
7
6
45
GND
I_17950_03 1.eps
+1V3D
070508
Page 12
Circuit Diagrams and PWB Layouts
SSB: MT5335 Interface VGA
38 TCM2.0E LA 7.
A
B12 B12
MT533 5 INTERFACE - VGA
U203
AL1
AR1
AL2
AR2
201
198
199
AOLRCK
200
196
A0S DATA0
18 6
18 5
18 9
18 7
190
AVDD33 _ADAC0
18 2
AVDD33 _ADAC1
188
GND
18 4
GND
183
ADAC_VCM
168
AVDD33 _DIG
AS PDIF
AOMCLK
AL1O
AR1O
AL2O
AR2O
AV33
AV33
600R
L23 1
600R
L23 4
AOBCK
1U
C245
AVD D33 _ADAC1
GND
C3 11
0.1U
1U
C246
ADAC_VCM
0.1U
C3 13
VGA_L
VGA_R
YPBPR_L
YPBPR_R
AIN2_L
AIN2_R
SCT_L
SCT_R
AVD D33_AADC
GND
VIMD_AADC
REFP_AADC
GND
177
AIN0_L
176
AIN0_R
175
AIN1_L
174
AIN1_R
173
AIN2_L
172
AIN2_R
171
AIN3 _L
170
AIN3 _R
169
AVD D33_AADC
18 1
AVSS33 _AADC
179
VMID_AADC
18 0
REFP_AADC
178
REFN_AADC
AS PDIF
AOMCLK
AOLRCK
AOBCK
AOS DATA0
AVDD33 _KADAC0
AVDD33 _KADAC1
AVSS33_KADAC0
AVSS33_KADAC1
ADAC_VCM
AVDD33 _DIG
MT533 5PKU
AV33
AV33
A
4U7
C219
L227
600R
1U
C241
AVDD33 _AADC
GND
0.1U
C3 07
A
GND
AV33
AV33
AV33
AV33
L228
600R
L229
600R
C242
C243
1U
1U
REFP_AADC
GND
AVDD33 _ADAC0
GND
GND
C3 08
C3 09
GND
0.1U
GND
0.1U
AV33
AV33
L23 0
600R
1U
C244
AVD D33 _DIG
GND
C3 10
GND
0.1U
GND
GND
4U7
C218
GND
GND
VIMD_AADC
C3 12
0.1U
GND
A
I_17950_03 2.eps
070508
Page 13
Circuit Diagrams and PWB Layouts
39 TCM2.0E LA 7.
SSB: D/A Converter
A
B13 B13
DIGITAL-ANALOG-CONVERTER
AL1O
AR1O
C900
C901
1U
R900
1U
R902
100K
GND
100K
GND
R901
470R
R903
470R
2200P
C925
2200P
C926
10K
R905
10K
R904
NC
C929
GND GND
GND
NC
C93 0
5K1
R906
33 K
R907
R909
33 K
OPAVREF
OPAVREF
R910
5K1
C928
GND
C927
100P
100P
C902
47U
6V3
3
2
1IN+
2IN-
6
1IN-
2OUT
7
1
1OUT
VCC+
8
U1
1U
C912
C903
47U
GND
6V3
4
VCC-
RC4558
2IN+
5
L16
600R
10R
10R
R908
S PEAK-OUTL
AV9 V
R913
S PEAK-OUTR
GND
A
A
DAC
DV33
DV33
C9013
0.1U
R902733R
R9028 33R
R9029
R9020
10K
1
2
3
4
5
6
7
U907
LRCLK
DIN
BCLK
ENABLE
VMID
ROUT
AGND
WM8 501
MCLK
FORMAT
DEEMPH
DVD D
DGND
LOUT
AVDD
C9018
0.1U
R903 0
33 R
14
13
12
11
10
9
8
AOMCL K
DACVL
ADCVA
0.1U
1U
C9016
C9014
1U
R9021
DACVL
C9017
10K
10K R9023
10K/NC
R9024
10K
R9025
NC/33 K
R9022
0
R9017
0
R9018
L900
L901
600R
600R
C913
1000P 1000P
GND
SCT1_AUL_OUT
SCT1_AUR_OUT
AV9V OPAVREF
R914
10K
R915
GND
10K
1U
C910
GND
OPAVREF
1U
C911
GND
R9019
47K
DV33
C9012
0.1U
AOLRCK
A0S DATA0
AOBCK
33 R
C9015
1U
+5V
L93 0
3 0R
ADCVA
ADCVA
1U
C9008
C9010
0.1U
DV33
1U
C9009
L93 1
3 0R
DACVL
C9011
1U
A
R9026
NC/33 K
C914
GND
I_17950_033 .eps
070508
Page 14
SSB: HDMI Switch
Circuit Diagrams and PWB Layouts
40 TCM2.0E LA 7.
B14 B14
HDMI S WITCH
P901
NC1
HPD
RX2+
RX2-
RX0+
RX0-
HPD
GND1
GND3
DDCDA
GND1
NC1
DDCDA
RX1+
RX1-
RXC+
RXC-
NC2
VCC
P903
RX1+
RX1-
GND3
RXC+
RXC-
NC2
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
CEC-IN
14
15
16
17
18
19
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
RX2+
RX2-
GND2
RX0+
RX0-
GND4
DDCCLK
GND5
GND2
GND4
DDCCLK
GND5
R42 NC\0R
HDMI1_S CL
HDMI1_S DA
+5V_HDMI1
CEC
+5V_HDMI0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DV33
DV33-HDMI
L9
600R
AV18-HDMI
R3 1
750R
C38
0.1U
0.1U
1U
C42
C3 9
GND
RX0_2
RX0_2B
RX0_1
RX0_1B
RX0_0
RX0_0B
RX0_C
RX0_CB
NC\4K7
0.1U
C43
R15
4K7
DV33
4K7
GND
RES ET_N
OS DA0
OS CL0
R54
4K7
R16
NC\4K7
R11
HDMI_S EL
R17
100R
100R
100R
R20
R18
R19
HPDIN
100R
OS DA1
OS CL1
HDMI_5V
0R
CEC-IN
1
R72
EZJZ1V270RA
2
GND
CI_DV18 AV18 -HDMI
L11
600R
0.1U
0.1U
C12
C11
R45
CEC
DV33 -HDMI
D5V0S 1
D104
D105
10P
10P
C134
D5V0S 1
D5V0S 1
D106
D107
C133
D5V0S 1
10P
10P
C13 6
C13 5
GND
CI_DV18
0.1U
0.1U
0.1U
C13
C14
0.1U
C16
C15
1U
C19
0.1U
C17
DV18 -HDMI
L10
600R
0.1U
0.1U
C21
C20
1U
0.1U
C23
C22
R12
NC\4K7
R14
4K7
R13
4K7
GND
DV33
R3 2
R33
100R
NC\100R
R3 4
NC\100R
R3 5
R52
4K7
R55
4K7
C
Q2
B
BT3 904
E
GND
100R
R53
D108
GND
134
2
D3 V3 L4
5
DV18-HDMI
R21
4K7
GND
R59
4K7
60
59
58
57
56
55
54
NC\0R R41
53
52
51
50
49
48
47
46
45
44
43
42
41
DV33
AGND7
RXC2+
RXC2AVCC18 D
HPD2
AVCC33 C
CEC-A
CEC-D
RPWR1
DS CL1
DS DA1
AVDD18 B
R1X2+
R1X2AGND6
R1X1+
R1X1AVCC33 B
R1X0+
R1X0-
R3 0
GND
NC\4K7
61
R2X0-
40
R2X0+
AGND5
3 9
62
R1XC+
AVCC 33 D
38
63
R2X1-
R1XC-
3 7
4K7
R51
656468
R2X1+
AVCC18 C
3 6
HPD1
AGND8
3 5
66
I2CS EL/INT
67
R2X2-
DGND1
3 4
R2X2+
DVCC 18A
33
69
70
AVDD 18C
DS DA2
U904
S II918 5
RPWR0
32
31
77
73
R0X2+
74
DGND2
RS VDL
R0X2-
27
26
75
76
HPDIN
AGND4
78
TS CL
TS DA
TPWR/I2CADDR
R0X1+
R0X1-
AVCC 33 A
2221252428
23
8 0
79
AGND9
EXTS WING
R0X0+
R0X0-
TX2+
AGND1
TX1+
AVCC 18A
TX0+
AGND2
TXC+
TXC-
RES ET#
LS DA
LS CL
HPD0
AVCC 18B
R0XC-
R0XC+
AGND3
TX2-
TX1-
TX0-
72
71
DS CL2
DVCC 18B
RPWR2
AVDD18 A
DS CL0
DS DA0
29
3 0
GND
HDMI0_S CL
HDMI0_S DA
R58
4K7
+5V_HDMI0
+5V_HDMI1
GND
D109
T
T
U905
1
A0
0.1U
C40
2
Z907
GND
A1
3
A2
4
GND
1
3
4
5
D3 V3 L4
2
T
AT24C02
VCC
SCL
SDA
8
R56
4K7
7
WP
6
5
R50
R49
47K
47K
HDMI0_S CL
HDMI0_S DA
T
T
Z906
Z905
T
Z908
Z904
0.1U
U906
1
VCC
A0
C41
2
WP
A1
3
SCL
A2
4
S DA
GND
AT24C02
GND
Z903
8
R57
R47
R48
4K7
47K
7
6
5
47K
HDMI1_S CL
HDMI1_S DA
T
T
Z901
Z902
GND
I_17950_03 4.eps
070508
Page 15
SSB: I/O Scart
Circuit Diagrams and PWB Layouts
41 TCM2.0E LA 7.
B15 B15
IO - S CART
P1
S CT1_AUR_OUT
1
S CT1_AUL_OUT
2
3
SCT1_B_IN
4
5
S CT1_G_IN
6
7
SCT1_R_IN
8
9
SCT1_AV_OUT
SCT1_AV_IN
SCT1_AUR_IN
SCT1_AUL_IN
SCT1_F S_IN
STC1_FB_IN
12
13
14
15
16
17
18
19
20
10
21
11
1
R63
2
EZJZ1V270RA
T
1
2
Z921
T
T
R64
Z925
Z926
T
Z924
T
T
T
Z919
T
Z918
T
Z922
Z927
EZJZ1V270RA
T
Z923
T
Z920
Z928
SCT1_AV_IN
SCT1_G_IN
1
2
GND
S CT1_B_IN
2 1
GND
S CT1_R_IN
2 1
GND
Nea rly Connector
L903
3 0R
GND
L904
3 0R
R60
GND
EZJZ1V270RA
L905
3 0R
R61
GND
EZJZ1V270RA
L906
3 0R
R62
EZJZ1V270RA
R968
75R
R971
75R
R975
75R
R976
75R
47P
C967
C970
16P
C973
16P
C976
16P
68 R
R972
100R
68 R
R974
100R
R977
68 R
R978
100R
100R
R969
R973
R970
Nea rly 533 5
C968
0.047U
C969
1U
C971
0.01U
C972
0.01U
C974
0.01U
C975
0.01U
C977
0.01U
C978
0.047U
S Y0
GND_S V
Y0P
Y0N
PB0P
PBR0N
PR0P
SC0
STC1_FB_IN
SCT1_F S_IN
L907
3 0R
R65
EZJZ1V270RA
2 1
L908
3 0R
2 1
R66
EZJZ1V270RA
GND GND
R963
S OY0
0R
GND
R960
75R
33 K
R961
GND
S CART_FS _IN
R962
10K
C979
470P
C98 0
470P
S CT1_AUR_OUT
1
2
SCT1_AUR_IN
SCT1_AUL_IN
SCT1_AUL_OUT
R67
EZJZ1V270RA
GND
2 1
R68
EZJZ1V270RA
NEARLY MT533 5
C965
C966
1U
1U
SCT_R
SCT_L
I_17950_03 5.eps
070508
C964
10K
10K
R964
R965
R966
10K
R967
10K
L1
3 0R
L2
3 0R
C963
470P
GND
470P
Page 16
Circuit Diagrams and PWB Layouts
SSB: I/O Side AV, S-Video, Audio
42 TCM2.0E LA 7.
B16 B16
CVBS _OUT
D2S A
P902
P902
WHITE
RED
YELLOW
IO - S IDE AV, S VIDEO, AUDIO
AV_ 5V
0R
NC
R918
R919
R9003
47U
10K
C001
C004
6V3
R9002
10K
9
Z975
7
5
T
T
6
8
Z974
GND
Z98 0Z 981
T T
4
3
L926
L927
30R
30R
2
1
0.01U
R920
1K
1U
C003
GND
C9004
470P
B
L925
10R
C
E
470R
R9001
Q8 15
C9003
470P
BC8 47C
10K
10K
R9004
75R
R9010
R9009
S CT1_AV_OUT
C002
47P
GND
R70
EZJZ1V270RA
2 1
R69
EZJZ1V270RA
2 1
R9012
10K
R924
0R
Nea rly Connector
L915
3 0R
GND
L916
3 0R
C9001
C9002
R9011
10K
GND
1U
1U
R947
75R
R949
75R
Q906
BC8 47C
AIN2_L
AIN2_R
47P
47P
GND
C958
C960
CVBS 0
Close to MT538 2p
R945
100R
C953
0.047U
T
Z917
CVBS 1
SY0
SC0
SY1
SC1
D2S A
CVBS 2
13 2
13 0
129
128
127
126
125
13 6
U203
CVBS 0
CVBS 1
CVBS 2
SY0
SC0
SY1
SC1
D2S A
DVDD25_VADC
DVSS25_VADC
GND_TUNER
GD_CVBS
GND_S V
AVDD25_VADC
AVSS25_VADC
AVDD25_REF
AVSS25_REF
AVDD25_VFE
AVSS25_VFE
13 9
140
133
13 1
124
141
142
13 7
138
13 5
13 4
DVDD25_VADC
GND
GND_CVBS
GND_S V
AVDD25_VADC
GND
AVDD25_REF
GND
AVDD25_VFE
GND
C920
1U
CI_GPIO14
R921
C
E
4K7
B
R944
MT533 5PKU
4K7
AV25
Nea rly 533 5
C959
R946
R948
0.047U
C961
0.047U
100R
100R
SY1
SC1
AV2 5
AV25
AV25
AV2 5
AV2 5
L911
600R
L912
600R
L913
600R
C916
1U
C917
1U
C918
1U
DVDD25_VADC
AVDD25_VADC
AVD D25 _RE F
C954
0.1U
GND
C955
0.1U
GND
C956
0.1U
AV2 5
AV25
L914
600R
1U
C919
AVD D25 _VF E
GND
C957
0.1U
GND
GND
R71
2 1
EZJZ1V270RA
GND_TUNER
Z978
GND
T
Z976
T
GND
L928
3 0R
R9014
75R
C9007
47P
R9013
100R
C9006
0.047U
C915
1U
CVBS 2
GND_CVBS
I_17950_03 6.eps
070508
Page 17
Circuit Diagrams and PWB Layouts
SSB: MT5335 Interface YPbPr & VGA
43 TCM2.0E LA 7.
B17 B17
MT533 5 INTERFACE - YPBPR, VGA
Nea rly Connector
P907
1
2
3
4
5
6
7
10
9
8
EZJZ1V270RA
YPBPR_L_IN
Y_IN
YPBPR_R_IN
PB_IN
PR_IN
VGA_R_IN
VGA_L_IN
R74
GND
EZJZ1V270RA
L4
Y_IN
3 0R
R98 2
75R
C73 1
16P
GND
L5
PB_IN
3 0R
R98 5
75R
C727
16P
R77
EZJZ1V270RA
2 1
2 1
2 1
R75
2 1
R76
EZJZ1V270RA
PR_IN
GND
L6
3 0R
R988
75R
C724
16P
WHITE
GREEN
RED
BLUE
RED
Nea rly 533 5
R98 4
0R
R98 1
68 R
R983
100R
R98 6
68 R
R98 7
100R
R98 9
68 R
C728
4700P
C73 0
0.01U
C729
0.01U
C726
0.01U
C725
0.01U
C723
0.01U
S OY1
Y1P
Y1N
PB1P
PBR1N
PR1P
U203
S OY0
Y0P
Y0N
PB0P
PBR0N
PR0P
S OY1
Y1P
Y1N
PB1P
PBR1N
PR1P
Z939
T
Z940
T
107
108
109
114
115
116
118
119
120
121
122
123
112
111
S OY0
Y0P
Y0N
PB0P
PBR0N
PR0P
S OY1
Y1P
Y1N
PB1P
PBR1N
PR1P
TN1
TP1
DVDD12_VGA
AVSS12_RGBADC
AVDD12_RGBADC
AVSS12_RGBFE
AVDD12_RGBFE
GN
VS YNC
HS YNC
S OG
117
DVDD12_VGA
113
GND
110
AVDD12_RGBADC
105
GND
101
AVDD12_RGBFE
RP
104
RP
RN
BP
BN
GP
106
98
99
102
103
96
97
100
RN
BP
BN
GP
GN
VS YNC
HS YNC
S OG
MT533 5PKU
AV12
AV12
L909
600R
1U
C98 7
DVDD12_VGA
C988
0.1U
AV12
AV12
L910
600R
AVDD12_RGBADC
GND
BLACK
P904
C990
0.1U
GND
C98 9
1U
AV12
AV12
L3
600R
AVD D12 _RG BFE
C991
1U
GND
C992
0.1U
GND
Z929
T
C73 2
2
1
S PDIF_OUT
1
2
R73
0.1U
EZJZ1V270RA
C993
33 P
R98 0
100R
GND
R979
100R
AS PDIF
YPBPR_L_IN
YPBPR_R_IN
C722
10K
10K
R990
R991
R992
10K
L8
3 0R
L7
3 0R
C719
470P
470P
R993
10K
C721
C720
1U
YPBPR_L
1U
YPBPR_R
GND
I_17950_03 7.eps
070508
Page 18
SSB: I/O VGA
Circuit Diagrams and PWB Layouts
44 TCM2.0E LA 7.
B18 B18
P908
IO - VGA
16
5
15
10
14
13
12
11
17
VGASCL_IN
4
9
3
8
2
7
1
6
W/P_CTR
VS YNC_IN
BLUE
HS YNC_IN
GREEN
VGASDA_IN
RED
GND
Z945
T
Z941
T
Z942
T
EZJZ1V270RA
R8 4
GND
T
Z943
1
2
T
Z944
T
1
2
R8 5
Z946
T
Z948
Z947
T
1
2
T
Z955
R716
0R
3
12
D913
BAV70
C005
ES D_0402
GND
EZJZ1V270RA
R8 6
W/P
VGA_PLUGPWR
+5V
GREEN
BLUE
RED
L918
L919
L920
Nea rly Connector
3 0R
GND
30R
30R
GND
GND
R996
75R
R999
75R
R702
75R
C715
16P
C711
16P
C708
16P
5VSB
Nea rly 533 5
R998
0R
R719
33 R
R997
100R
R720
33 R
R701
100R
R721
33 R
R703
100R
C712
C714
C713
C710
0.01U
C709
0.01U
C707
0.01U
C706
0.01U
4700P
0.01U
0.01U
S OG
GP
BN
RP
RN
GN
BP
GND
C996
0.1U
VGA_PLUGPWR
U903
1
A0
2
A1
3
A2
4
GND
AT24C02
VCC
WP
SCL
SDA
VGA_PLUGPWR
8
W/P
7
VGASCL
6
VGAS DA
5
R715
10K
Z972
T
Z973
T
Z971
T
Z970
T
HS YNC_IN
VS YNC_IN
VGA_R_IN
VGA_L_IN
1
2
1
2
L921
3 0R
R8 2
EZJZ1V270RA
L922
3 0R
R83
EZJZ1V270RA
22K
R718
R717
22K
Z949
T
Z950
T
HS YNC
VS YNC
L924
L923
30R
30R
GND
10P
10P
C705
C704
EZJZ1V270RA
C999
470P
C703
470P
10K
10K
R704
R705
R706
10K
C702
C701
R707
10K
5VSB
5VSB
5VSB
16P
16P
R708
10K
C998
R710
10K
C997
S W_UPDATE_CTL
R726
0R/NC
U0TX
E
VGASCL_IN
R712
100R
C143 ZT
Q903
C
B
S W_UPDATE_CTL1
R725
10K
5VSB
B
5VSB
C
C143ZT
E
GND
R714
10K
Q905
VGASDA_IN
R713
100R
C
Q904
C143 ZT
B
U0RX
E
I_17950_038 .eps
070508
1U
VGA_R
1U
VGA_L
GND
EZJZ1V270RA
EZJZ1V270RA
VGASCL_IN
1
R8 0
2
GND
VGASDA_IN
1
R8 1
2
GND
100R
100R
R711
R709
VGASCL
VGAS DA
Page 19
SSB: LVDS Receiver
Circuit Diagrams and PWB Layouts
45 TCM2.0E LA 7.
B19 B19
LVDS RECEIVER
DV33A
40
3 0
20
10
4
2
VDD_PANEL
P205
39
37 38
35 36
33 34
31 32
29
27 28
25 26
23 24
21 22
19
17 18
15 16
13 14
11 12
9
78
5 6
3
1
GND
C2010
NC\TTL\0.1U
R0
R2
R4
R6
G0
G2
G4
G6
B0
B2
B4
B6
D_VSYNC
PANEL_CTL2
CLK
GND
DV33A
NC\TTL\0.1U
L929
NC\TTL\600R
C2001
NC\TTL\0.1U
GND
DV33A_LVDS_RECEIVER
C2202
C2004
NC\TTL\0.1U
NC\TTL\0.1U
C2006
NC\TTL\0.1U
C2007
NC\TTL\0.1U
T_HS YNC
T_VS YNC
CLK11+
T_B5
T_DE
T_R6
AN00
AP00
AN11
AP11
AN22
AP22
CLK11-
AN33
AP33
PWRDN
T_CLK
T_R0
C2015
DV33A_LVDS_RECEIVER
U207
1
RXOUT22
2
RXOUT23
3
RXOUT24
4
GND1
5
RXOUT25
6
RXOUT26
7
RXOUT27
8
LVD SGND1
9
RXIN0-
10
RXIN0+
11
RXIN1-
12
RXIN1+
13
LVD SVCC1
14
LVD SGND2
15
RXIN2-
16
RXIN2+
17
RXCLKIN-
18
RXCLKIN+
19
RXIN3 -
20
RXIN3 +
21
LVD SGND3
22
PLLGND1
23
PLLVCC1
24
PLLGND2
25
PWRDWN
26
RXCLKOUT
27
RXOUT0
28
V38 6
VCC4
RXOUT21
RXOUT20
RXOUT19
GND5
RXOUT18
RXOUT17
RXOUT16
VCC3
RXOUT15
RXOUT14
RXOUT13
GND4
RXOUT12
RXOUT11
RXOUT10
VCC2
RXOUT9
RXOUT8
RXOUT7
GND3
RXOUT6
RXOUT5
RXOUT4
RXOUT3
VCC1
RXOUT2
RXOUT1 GND2
R293
T_R7
T_R6
T_R5
T_R4
T_R3
T_R2
T_R1
T_R0
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
T_B4
T_B3
T_B2
T_B1
T_B7
T_B6
T_B0
T_G5
T_G4
T_G3
T_G7
T_G6
T_G2
T_G1
T_G0
T_R5
T_R7
T_R4
T_R3
T_R2
T_R1
T_G7
T_G6
T_G5
T_G4
T_G3
T_G2
T_G1
T_G0
T_B7
T_B6
T_B5
T_B4
T_B3
GND
T_B2
T_B1
T_B0
NC\TTL\33 R
1
2
3
45
NC\TTL\33 R
1
2
3
45
NC\TTL\33 R
1
2
3
45
NC\TTL\33 R
1
2
3
45
NC\TTL\33 R
1
2
3
45
NC\TTL\33 R
1
2
3
45
R294
R295
R296
R298
R299
8
R7
R6
7
R5
6
R4
8
R3
7
R2
6
R1
R0
8
G7
7
G6
G5
6
G4
8
G3
G2
7
6
G1
G0
8
B7
B6
7
B5
6
B4
8
B3
B2
7
B1
6
B0
R1
R3
R5
R7
G1
G3
G5
G7
B1
B3
B5
B7
D_HS YNC
DE
AN00
AN11
AN22
CLK11-
AN33
R23
100R
R24
100R
R2003
100R
R2004
100R
R2005
100R
AP00
AP11
AP22
CLK11+
AP33
PWRDN_EN
DV33A
B
DV33A
R291
NC\TTL\10K
C
Q5
C143 ZT
E
GND
PWRDN
T_CLK
T_DE
T_VSYNC
T_HSYNC
L239
120R
R290
NC\TTL\33 R
1
2
3
45
NC\TTL\33 R
R292
8
7
6
CLK
DE
D_VSYNC
D_HS YNC
C2011
NC\TTL\16P
GND
I_17950_03 9.eps
070508
Page 20
Circuit Diagrams and PWB Layouts
48 TCM2.0E LA 7.
Keyboard Control Panel
KEYBOARD CONTROL
E E
Personal Notes:
P601
4
3
GND
2
1
5VIN
5VS B
KEY
0
R701
0.1U
C601
Layout Keyboard Control Panel (Top Side)
1K
1K5
2K7
4K3
7K5
R601
3 90R
R602
R603
R604
R605
R606
vol-
vol+
menu
ch-
ch+
POWER
K606
1
24
1
24
1
24
1
24
1
24
1
24
3
K605
3
K604
3
K60 3
3
K602
3
K601
3
I_1793 0_03 1.eps
250408
I_1793 0_03 2.eps
220408
E_06532_012.ep
13100
Page 21
IR LED Panel
Circuit Diagrams and PWB Layouts
51 TCM2.0E LA 7.
J J
P1
R6
100R
R9
GND
LED1
IR
+5V
R1
4K7
C3
47U
D3
5
4
3
2
1
LED2
4K7
6V3
R5
100R
C2
BT3904
C1
10U
R3
10U
1K
C
Q1
B
E
Q2
E
C
IR
VCC
GND
B
BT3906
G1
4K7
3K3
R7
R4
IR & LED
Personal Notes:
R51
4K7
R52
4K7
R2
B
BT3904
Layout IR LED Panel (Top Side)
4K7
C
E
Q5
13
RW
D1
2
I_1793 0_033 .eps
220408
I_1793 0_03 4.eps
220408
E_06532_012.ep
13100
Page 22
Personal Notes:
Circuit Diagrams and PWB Layouts
52 TCM2.0E LA 7.
E_06532_013.eps
131004