Philips SZF2002 Datasheet

INTEGRATED CIRCUITS

DATA SH EET

SZF2002

Low voltage 8-bit microcontroller with 6-kbyte embedded RAM

Product speciﬁcation File under Integrated Circuits, IC20

1998 Aug 26

Philips Semiconductors Product speciﬁcation

Low voltage 8-bit microcontroller with 6-kbyte embedded RAM

CONTENTS

1 FEATURES 2 GENERAL DESCRIPTION 3 APPLICATIONS 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 FUNCTIONAL DIAGRAM 7 PINNING INFORMATION

7.1 Pinning

7.2 Pin description 8 FUNCTIONAL DESCRIPTION

8.1 General

8.2 CPU timing 9 MEMORY ORGANIZATION

9.1 Program memory

9.2 Data memory

9.3 Special Function Registers (SFRs)

9.4 Addressing

9.5 Paging logic 10 PROGRAM STATUS WORD (PSW) 11 I/O FACILITIES

11.1 Ports

11.2 Port configuration 12 TIMER/EVENT COUNTERS

12.1 Timer 0 and Timer 1

12.2 Timer 2

12.3 Timer/Counter 2 Control Register (T2CON)

12.4 Timer/Counter 2 Mode Register (T2MOD)

12.5 Watchdog Timer (T3) 13 PULSE WIDTH MODULATED OUTPUT

13.1 Prescaler Frequency Control Register (PWMP)

13.2 Pulse Width Register (PWM) 14 ANALOG-TO-DIGITAL CONVERTER (ADC)

14.1 ADC Control Register (ADCON)

14.2 ADC Result Register (ADCH) 15 REDUCED POWER MODES

15.1 Idle mode

15.2 Power-down mode

15.3 Wake-up from Power-down mode

15.4 Status of external pins

15.5 Power Control Register (PCON)

SZF2002

16 I2C-BUS SERIAL I/O

16.1 Serial Control Register (S1CON)

16.2 Serial Status Register (S1STA)

16.3 Data Shift Register (S1DAT)

16.4 Address Register (S1ADR) 17 STANDARD SERIAL INTERFACE SIO0:

UART

17.1 Multiprocessor communications

17.2 Serial Port Control and Status Register (S0CON)

17.3 Baud rates

18 INTERRUPT SYSTEM

18.1 External interrupts INT2 to INT8

18.2 Interrupt priority

18.3 Interrupt related registers

19 CLOCK CIRCUITRY 20 RESET

20.1 External reset using the RST pin

20.2 Power-on-reset

21 SPECIAL FUNCTION REGISTERS

OVERVIEW

22 DEBUGGING SUPPORT

22.1 Recommended equipment

22.2 Connecting the pod

22.3 Powering the pod

22.4 Bank switching support

22.5 Software recommendations

23 INSTRUCTION SET 24 LIMITING VALUES 25 DC CHARACTERISTICS 26 ADC CHARACTERISTICS 27 AC CHARACTERISTICS 28 PACKAGE OUTLINE 29 SOLDERING

29.1 Introduction

29.2 Reflow soldering

29.3 Wave soldering

29.4 Repairing soldered joints

30 DEFINITIONS 31 LIFE SUPPORT APPLICATIONS 32 PURCHASE OF PHILIPS I2C COMPONENTS

1998 Aug 26 2

Philips Semiconductors Product speciﬁcation

Low voltage 8-bit microcontroller with 6-kbyte embedded RAM

1 FEATURES

• Fully static 80C51 Central Processing Unit (CPU)

• 8-bit CPU, ROM, RAM and I/O in a 80 lead LQFP

package

• 6-kbytes ROM program memory, expandable externally to 256 kbytes

• 6144 + 256 bytes low power RAM data memory, expandable externally to 32 kbytes

• Internal AUX RAM can be used for program execution (only in combination with internal ROM)

• Three 8-bit ports; 24 I/O lines

• Three 16-bit timer/event counters

• Flash Memory Interface optimized, with power saving

and programming options

• Internal demultiplexing and latching of address/data bus to reduce system component count

• Interfaces to up to 256-kbyte Flash Memory (banked)

• Fifteen source, fifteen vector nested interrupt structure

with two priority levels

• Full duplex serial port (UART)

C-bus interface for serial transfer on two lines

• I

• Analog-to-Digital Converter (ADC) with Power-down

mode; 6 input channels and 8-bit ADC

• Pulse Width Modulated (PWM) output (8-bit resolution)

• Watchdog Timer

• Enhanced architecture with:

– Non-page oriented instructions – Direct addressing – Four 8-byte RAM register banks – Stack depth limited only by available internal RAM

(maximum 256 bytes)

– Multiply, divide, subtract and compare instructions

• Modes of reduced activity: Power-down and Idle modes

SZF2002

• Wake-up via external interrupts at

• Frequency range: up to 16 MHz (only limited by external

memory and ADC performance)

• Supply voltage: 3.0 V

• Very low power consumption:

operational 0.65 mW/MHz; Idle 0.25 mW/MHz at 3.0 V

• Operating temperature: −40 to +85 °C.

2 GENERAL DESCRIPTION

The SZF2002 low power system controller is manufactured in an advanced 0.5 µm CMOS technology. The instruction set of the SZF2002 is based on that of the 80C51 and consists of over 100 instructions: 49 one-byte, 46 two-byte, and 16 three-byte. The device has low power consumption and two software selectable modes for power reduction: Idle and Power-down.

This data sheet details the specific properties of the SZF2002; for details of the 80C51 core and peripheral functions such as timers, UART and I/O, see

“Data Handbook IC20” I2C-bus and how to use it”

9398 393 40011.

3 APPLICATIONS

The SZF2002 is an 8-bit general purpose microcontroller especially suited for wireless telephone and battery powered applications. The SZF2002 also functions as an arithmetic processor having facilities for both binary and BCD arithmetic plus bit-handling capabilities.

. For the I2C-bus refer to

, ordering number

INT0 to INT8

“The

4 ORDERING INFORMATION

TYPE

NUMBER

SZF2002HL LQFP80 plastic low proﬁle quad ﬂat package; 80 leads; body 12 × 12 × 1.4 mm SOT315-1

1998 Aug 26 3

NAME DESCRIPTION VERSION

PACKAGE

Philips Semiconductors Product speciﬁcation

Low voltage 8-bit microcontroller with 6-kbyte embedded RAM

5 BLOCK DIAGRAM

INT2 to INT8

INT0

INT1

PROGRAM

CPU

XCLK

RST

T0 T1

TWO 16-BIT

TIMER/ EVENT

COUNTERS

(T0, T1)

MEMORY 6-KBYTE

ROM

3 3

DATA

MEMORY

6144 + 256 bytes RAM

PWM

PWM ADC

DDA

SSA

SZF2002

ADC0 to ADC5

RAMCE

DEBUG

D0 to D7

A0 to A17

excluding

ROM/RAM

PARALLEL I/O PORTS

AND

EXT. BUS

80C51

core

SERIAL

UART PORT

RXDTXDP3P1

8-BIT

I/O

PORTS

SZF2002

16-BIT TIMER/ EVENT

COUNTER

T2EX

I2C-BUS

INTERFACE

SDA SCL

WATCHDOG

TIMER

(T3)

MGM180

(1) Address lines A0 to A5 have alternative functions during Debug; see Section 7.2.

Fig.1 Block diagram.

1998 Aug 26 4

Philips Semiconductors Product speciﬁcation

Low voltage 8-bit microcontroller with 6-kbyte embedded RAM

6 FUNCTIONAL DIAGRAM

handbook, full pagewidth

XCLK

PWM

SSA

DDA V

PORT 1

PORT 3

T2 INT2 T2EX INT3

SCL SDA

RXD TXD

INT0 INT1 T0 T1

INT4 INT5 INT6 INT7 INT8

SZF2002

RAMCE

PORT 4

DEBUG

ADC0 ADC1 ADC2 ADC3 ADC4 ADC5

RST

SZF2002

data bus

address bus

RD WR ALE

PSEN RST TRUE_A15

MGM181

Fig.2 Functional diagram.

1998 Aug 26 5

Philips Semiconductors Product speciﬁcation

Low voltage 8-bit microcontroller with 6-kbyte embedded RAM

7 PINNING INFORMATION

7.1 Pinning

handbook, full pagewidth

n.c.

A12

A7 A6 A5 A4

PWM

RST

XCLK

P3.7

P3.6 P3.5/T1 P3.4/T0

P3.3/INT1 P3.2/INT0

P3.1/TXD

P3.0/RXD

n.c. 20

n.c.

A15

A16

A17

A14

A13

73 1 2 3 4 5 6 7 8 9

10 11 12 13 14 15 16 17 18 19

VSSVDDA11

SZF2002

A10

n.c.

n.c. D3

P4.0/RAMCE

P4.1

P4.2

P4.3

P4.4

P4.5

P4.6

P4.7

n.c.

P1.7/SDA

P1.6/INT8/SCL

P1.5/INT7

P1.4/INT6

P1.3/INT5

P1.2/INT4

P1.1/INT3/T2EX

P1.0/INT2/T2

Fig.3 Pin configuration.

1998 Aug 26 6

DDA

SSA

ADC5

ADC4

ADC3

ADC2

ADC1

ADC0

38 EA

40 n.c.

DEBUG

MGM182

Philips Semiconductors Product speciﬁcation

Low voltage 8-bit microcontroller with

SZF2002

6-kbyte embedded RAM

7.2 Pin description Table 1 LQFP80 package

SYMBOL PIN DESCRIPTION

Program memory interface; note 1

A0 55 A0/ A1 54 A1/ A2 53 A2/ALE. Address line 2, used as ALE during Debug. A3 52 A3/ A4 6 A4/RST. Address line 4, used as RST during Debug. A5 5 A5/TRUE_A15. Address line 5, used as A15 = P2.7 during Debug. A6 4 A6. Address line 6 (not needed during Debug, see D6). A7 3 A7. Address line 7 (not needed during Debug, see D7). A8 73 Address lines A8 to A14. During Debug these lines are used as P2.0 to P2.6. A9 72 A10 67 A11 69 A12 2 A13 74 A14 75 A15 79 Address lines A15 to A17. Page selection; during Debug these lines are the page A16 78 A17 76 D0 56 Data bus. During Debug these line are P0.0 to P0.7. D1 57 D2 58 D3 59 D4 62 D5 63 D6 64 D7 65 CE 66 Chip Enable. Enable strobe to external program memory. OE 68 Output Enable. Output read strobe to external memory. WE 77 Write Enable. Write strobe to external memory.

RD. Address line 0, used as RD during Debug. WR. Address line 1, used as WR during Debug.

PSEN. Address line 3, used as PSEN during Debug.

1998 Aug 26 7

Philips Semiconductors Product speciﬁcation

Low voltage 8-bit microcontroller with

SZF2002

6-kbyte embedded RAM

SYMBOL PIN DESCRIPTION

I/O Ports

INT2/T2 29 Port 1 (P1.0 to P1.7). 8-bit bidirectional I/O port with internal pull-ups; INT2 to INT8:

P1.0/ P1.1/

INT3/T2EX 28

P1.2/

INT4 27

P1.3/

INT5 26 INT6 25

P1.4/ P1.5/

INT7 24

P1.6/

INT8/SCL 23 P1.7/SDA 22 P3.0/RXD 19 Port 3 (P3.0 to P3.7). 8-bit bidirectional I/O port with internal pull-ups; RXD: serial P3.1/TXD 18 P3.2/INT0 17 P3.3/

INT1 16 P3.4/T0 15 P3.5/T1 14 P3.6 13 P3.7 12 P4.0/

RAMCE 49 Port 4 (P4.0 to P4.7). 8-bit bidirectional I/O port; RAMCE chip enable for external P4.1 48 P4.2 47 P4.3 46 P4.4 45 P4.5 44 P4.6 43 P4.7 42

external interrupt inputs; T2: Timer T2 I/O; T2EX: Timer 2 external input; SCL: I2C-bus interface clock; SDA: I2C-bus interface data.

Port 1 pins that have logic 1s written to them are pulled HIGH by the internal pull-ups, and in that state can be used as inputs (note P1.6 and P1.7 are open-drain only). As inputs, Port 1 pins that are externally pulled LOW will source current (IIL, see Chapter 25) due to the internal pull-ups.

port receiver data input (asynchronous); TXD: serial port transmitter data output (asynchronous); T0: Timer 0 external input; T1: Timer 1 external input.

Port 3 pins that have logic 1s written to them are pulled HIGH by the internal pull-ups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally pulled LOW will source current (IIL, see Chapter 25) due to the internal pull-ups.

RAM. Port 4 pins that have logic 1s written to them are pulled HIGH by the internal pull-ups,

and in that state can be used as inputs. As inputs, Port 4 pins that are externally pulled LOW will source current (IIL, see Chapter 25) due to the internal pull-ups.

INT0: external interrupt 0; INT1: external interrupt 1;

ADC interface

ADC0 37 Input channels to the ADC. ADC1 36 ADC2 35 ADC3 34 ADC4 33 ADC5 32

1998 Aug 26 8

Philips Semiconductors Product speciﬁcation

Low voltage 8-bit microcontroller with

SZF2002

6-kbyte embedded RAM

SYMBOL PIN DESCRIPTION

General

PWM 7 Pulse Width Modulation output. RST 8 Reset. A HIGH level on this pin for at least 12 clock cycles resets the device. XCLK 9 Clock input. EA 38 External Access. When EA is HIGH the CPU executes out of internal program

memory (unless the program counter exceeds 7FFFH). A LOW EA forces the CPU to execute out of external memory regardless of the value of the Program Counter. This signal is latched at the falling edge of reset (RST pin). The EA pin has an internal pull-down. When it is not connected the CPU executes from external memory.

DEBUG 39 DEBUG enable. If HIGH, forces standard 80C51 timing signals output at address and

databus. In this mode the databus is multiplexed with the lower 8 bits of the address

Power

bus, and the A0 to A3 lines are used for the allows a standard 80C51 in-circuit emulator to be connected. For normal operation connect DEBUG to VSS.

10, 50,70Power supply digital core and digital I/O pads.

RD, WR, ALE and PSEN signals. This

DDA

SSA

n.c. 1, 20,

Note

1. The pin layout has been optimized for easy connection of 256 kbytes Flash ROM (e.g. ATMEL AT29LV010A, SGS-Thomson M28V201, or AMD Am29F010).

11, 51,71Ground: circuit ground potential.

30 Analog power. 31 Analog ground.

Not connected. 21, 40, 41, 60,

61, 80

1998 Aug 26 9

Philips Semiconductors Product speciﬁcation

Low voltage 8-bit microcontroller with 6-kbyte embedded RAM

8 FUNCTIONAL DESCRIPTION

Detailed descriptions of each function are described in:

Chapter 9 “Memory organization” Chapter 10 “Program Status Word (PSW)” Chapter 11 “I/O facilities” Chapter 12 “Timer/event counters” Chapter 13 “Pulse Width Modulated output” Chapter 14 “Analog-to-digital converter (ADC)” Chapter 15 “Reduced power modes” Chapter 16 “I2C-bus serial I/O” Chapter 17 “Standard serial interface SIO0: UART” Chapter 18 “Interrupt system” Chapter 19 “Clock circuitry” Chapter 20 “Reset” Chapter 21 “Special Function Registers overview” Chapter 22 “Debugging support”.

8.1 General

The SZF2002 is a stand-alone high-performance CMOS microcontroller designed for use in real-time applications such as wireless telephone and mobile communications, instrumentation, industrial control, intelligent computer peripherals and consumer products.

The device provides hardware features, architectural enhancements and new instructions to function as a controller for applications requiring up to 256 kbytes of program memory and/or up to 6144 + 256 bytes of on-chip data memory.

SZF2002

The SZF2002 contains a 6-kbyte program memory; a static 6144 + 256 byte data memory (RAM); 24 I/O lines; three 16-bit timer/event counters; a fifteen-source two priority-level, nested interrupt structure, a 6-channel 8-bit ADC, a Watchdog Timer and a Pulse Width Modulation output.

Two serial interfaces are provided on-chip:

• A standard UART serial interface

• A standard I of up to 400 kbits/s (depending on clock frequency). The I2C-bus serial interface has byte oriented master and slave functions allowing communication with the whole family of I2C-bus compatible devices.

The device has two software selectable modes of reduced activity for power reduction:

• Idle mode: freezes the CPU while allowing the derivative functions (timers, serial I/O, RAM, ADC and PWM) and interrupt system to continue functioning

• Power-down mode: saves the RAM contents but stops the clock causing all other chip functions to be inoperative.

8.2 CPU timing

A machine cycle consists of a sequence of 6 states. Each state lasts one clock period, thus a machine cycle takes 6 clock periods or 1 µs if the clock frequency (f 6 MHz.

C-bus serial interface with a transfer speed

) is

clk

1998 Aug 26 10

Philips Semiconductors Product speciﬁcation

Low voltage 8-bit microcontroller with 6-kbyte embedded RAM

9 MEMORY ORGANIZATION

The SZF2002 has 6 kbytes of program memory plus 6 kbytes + 256 bytes of data memory on chip. The device has separate address spaces for program and data memory (see Fig.4).

The SZF2002 can directly address up to 256 kbytes of external data memory. The CPU generates the read strobe (OE), the write strobe (WE) and chip select (CE) for external program memory (Flash), and read strobe (OE) and write strobe (WE) and chip select (RAMCE) for external data memory.

9.1 Program memory

The SZF2002 contains 6 kbytes of internal ROM and 6144 + 256 bytes of RAM. The lower 6 kbytes of program memory can be implemented in either on-chip ROM or external program memory. The 6 kbytes of program memory is implemented as mask programmable ROM.

There are two modes for the program memory, depending on the state of the address range:

1. EA = 0. All program fetches are directed to the external program memory. After reset the CPU begins execution at location 8000H.

2. EA = 1. After reset the CPU begins execution at location 0000H. Fetches from addresses 2000H to 37FFH are redirected to the Auxiliary RAM. The processor can fill this RAM with normal write operations to the data memory (MOVX to addresses 0000H to 17FFH). Program memory fetches from addresses 0000H to 17FFH are directed to the internal ROM.

Program Counter values greater than 7FFFH are automatically addressed to external memory regardless of the state of the EA pin.

9.2 Data memory

The SZF2002 contains 6144 + 256 bytes of RAM and a number of Special Function Registers (SFRs). All these data spaces are addressed differently. Figure 4 shows the internal data memory space divided into the lower 128 bytes, the upper 128 bytes, Auxiliary RAM, and the SFRs space. Internal RAM locations 0 to 127 are directly and indirectly addressed. Internal RAM locations 128 to 255 are only indirectly addressed.

EA pin (latched during reset) and on the

SZF2002

The Special Function Register locations 128 to 255 are only directly addressed. Auxiliary RAM is accessible via MOVX instructions to the lower 32-kbyte address space. MOVX @R0/R1 instructions use SFR P2 as page selector. The upper 32-kbyte address space is redirected to the program memory, to accommodate flash programming.

9.3 Special Function Registers (SFRs)

The upper 128 bytes are the address locations of the SFRs. Figures 6 and 7 show the Special Function Registers space. The SFRs include the port latches, timers, peripheral control, serial I/O registers, etc. These registers are accessed by direct addressing. There are 128 directly addressed locations in the SFR address space. Bit addressed SFRs are those that end in 000B.

9.4 Addressing

The SZF2002 has five methods for addressing source operands:

• Register

• Direct

• Indirect

• Immediate

• Base-Register plus Index-Register-Indirect.

The first three methods can be used for addressing destination operands. Most instructions have a ‘destination/source’ field that specifies the data type, addressing methods and operands involved. For operations other than MOVs, the destination operand is also a source operand.

Access to memory addressing is as follows:

• Registers in one of the four register banks through Direct or Indirect (see Fig.5)

• Lower 128 bytes of internal RAM through Direct or register Indirect; upper 128 bytes of internal RAM through Indirect

• Special Function Registers through Direct

• Program memory look-up tables through Base-Register

plus Index-Register-Indirect

• Extended data memory access through register Indirect.

1998 Aug 26 11

Philips Semiconductors Product speciﬁcation

Low voltage 8-bit microcontroller with 6-kbyte embedded RAM

handbook, full pagewidth

FFFFH

EXTERNAL

FLASH ROM

(BANKED)

8000H

7FFFH

37FFH

INTERNAL AUX RAM

6-KBYTE

INTERNAL

ROM

(4)

EA = 1

0000H

EXTERNAL

ROM

BANK 0

EA = 0

2000H

17FFH

0000H

FFFFH

8000H

7FFFH

1800H

17FFH

0000H

EXTERNAL

FLASH ROM

(BANKED)

EXTERNAL

RAM

INTERNAL

AUX RAM

(MOVX)

FFH

80H

00H

INTERNAL

RAM

(1)

(2)

overlapped space

FUNCTION

(3)

REGISTERS

SZF2002

SPECIAL

INTERNAL MEMORYDATA MEMORYPROGRAM MEMORY

(1) Accessible via indirect addressing only. (2) Accessible via direct and indirect addressing. (3) Accessible via direct addressing. (4) Gaps in the address map are undefined, and should not be used.

Fig.4 Memory map.

Table 2 Memory spaces; note 1

MEMORY SPACE ADDRESS MODE USED SIGNAL

Internal RAM 00H to 7FH direct and indirect − Internal RAM 80H to FFH indirect − SFRs 80H to FFH direct − Internal AUX RAM (on-chip) 0000H to 17FFH MOVX − External RAM (off-chip) 1800H to 7FFFH MOVX External ROM (off-chip) 0000H to FFFFH; note 2 program execution

RAMCE, OE and WE

CE, OE Internal AUX RAM (on-chip) 2000H to 37FFH program execution − External Flash ROM write (off-chip) 8000H to FFFFH; note 2 MOVX

CE, OE and WE

Notes

1. Execution from internal memory is only possible when

EA = 1 during reset.

2. Page select is used to access all 8 banks in the 256-kbyte address space.

MGM183

1998 Aug 26 12

Philips Semiconductors Product speciﬁcation

Low voltage 8-bit microcontroller with

SZF2002

6-kbyte embedded RAM

9.5 Paging logic

The SZF2002 contains paging logic to handle the extended address range.

Table 3 Paging of external memory; notes 1 and 2

TRUE_A15

(INTERNAL)

0 XXX 000 0 lower 32 kbytes always bank 0 1 000 000 0 bank 0 1 001 001 1 bank 1 1 010 010 2 bank 2 1 011 011 3 bank 3 1 100 100 4 bank 4 1 101 101 5 bank 5 1 110 110 6 bank 6 1 111 111 7 bank 7

Notes

1. During Debug A<17-15> are used to output the bank register. The TRUE_ A15 line is output at the A5 pin.

2. During Debug ROM and RAM access is done via

BANK SFR [2 : 0] A<17-15> PINS BANK REMARK

PSEN, WR and RD.

handbook, halfpage

R0 R7

7FH

30H 2FH

20H 1FH

18H 17H

10H 0FH

08H 07H

4 banks of 8 registers

MGD675

Fig.5 The lower 128 bytes of internal RAM.

(R0 to R7)

1998 Aug 26 13

Philips Semiconductors Product speciﬁcation

Low voltage 8-bit microcontroller with 6-kbyte embedded RAM

MNEMONIC

PWMP

PWM

IP1

WDTKEY

IX1

IEN1

BIT ADDRESS

FEFF FD FC FB FA F9 F8

F6F7 F5 F4 F3 F2 F1 F0

EEEF ED EC EB EA E9 E8

DIRECT

BYTE

ADDRESS (HEX)

FFHT3 FEH FDH FCH

F8H F7H

F0H EFH EEH EDH ECH EBH EAH

E9H

E8H

SZF2002

ACC

S1ADR

S1DAT S1STA

S1CON

PSW

TH2

TL2

RCAP2H

RCAP2L

T2MOD

T2CON

ADCH

ADCON

IRQ1

E6E7 E5 E4 E3 E2 E1 E0

DEDF DD DC DB DA D9 D8

D6D7 D5 D4 D3 D2 D1 D0

CECF CD CC CB CA C9 C8

C6C7 C5 C4 C3 C2 C1 C0

E0H

DBH DAH D9H D8H

D0H CFH CEH

CDH CCH

CBH CAH C9H C8H

C5H C4H

C1H C0H

SFRs containing

directly addressable

bits

MGM184

Fig.6 Special Function Register memory map.

1998 Aug 26 14

Philips Semiconductors Product speciﬁcation

Low voltage 8-bit microcontroller with 6-kbyte embedded RAM

MNEMONIC

IP0

IEN0

BIT ADDRESS

BE BD BC BB BA B9 B8

B6B7 B5 B4 B3 B2 B1 B0

AEAF AD AC AB AA A9 A8

DIRECT

BYTE

ADDRESS

B8H

B0H AFH AEH ADH ACH ABH AAH A9H A8H

SZF2002

(used as

address bus)

S0BUF

S0CON

ROMBANK

TMOD TCON PCON

(used as

address bus)

TH1 TH0

TL1 TL0

DPH

DPL

A6A7 A5 A4 A3 A2 A1 A0

9E9F 9D 9C 9B 9A 99 98

9697 95 94 93 92 91 90

8E8F 8D 8C 8B 8A 89 88

8687 85 84 83 82 81 80

A0H

9AH 99H 98H

91H 90H

8DH 8CH 8BH 8AH 89H 88H 87H

83H 82H 81H 80H

SFRs containing

directly addressable

bits

MGM185

Fig.7 Special Function Register memory map (continued from Fig.6).

1998 Aug 26 15

Philips Semiconductors Product speciﬁcation

Low voltage 8-bit microcontroller with

SZF2002

6-kbyte embedded RAM

10 PROGRAM STATUS WORD (PSW)

The Program Status Word contains several status bits that reflect the current state of the CPU. The PSW, shown in Table 4, resides in the SFR memory space. It contains the Carry bit, the Auxiliary Carry (for BCD operations), the two register bank select bits, the Overflow flag, a Parity bit and two user-definable status flags.

The Carry bit, other than serving the function of a Carry bit in arithmetic operations, also serves as the Accumulator for a number of boolean operations.

Bits RS0 and RS1 are used to select one of the four register banks; see Table 5. A number of instructions refer

Table 4 Program Status Word (SFR address D0H)

76543210

CY AC F0 RS1 RS0 OV USR P

Table 5 Description of PSW bits

to these RAM locations as R0 through to R7. The selection of which of the four register banks is being referred to is made on the basis of the state of RS0 and RS1 at execution time.

The Parity bit reflects the number of 1s in the Accumulator: P = 1, if the Accumulator contains an odd number of 1s, and P = 0, if the Accumulator contains an even number of 1s. Thus, the number of 1s in the Accumulator plus P is always even. The bits F0 and USR are uncommitted and may be used as general purpose status flags.

BIT SYMBOL DESCRIPTION

7CYCarry ﬂag. The Carry ﬂag receives carry out from bit 7 of ALU operands. 6ACAuxiliary Carry ﬂag. The Auxiliary Carry ﬂag receives carry out from bit 3 of addition

operands. 5F0General purpose status ﬂag. 4 RS1 Register Bank Select 1. This bit selects Register Bank 1. 3 RS0 Register Bank Select 0. This bit selects Register Bank 0. 2OVOverﬂow ﬂag. This ﬂag is set by arithmetic operations. 1 USR USR. This is a user-deﬁnable ﬂag. 0PParity. If the Accumulator contains an odd number of 1s this bit is set to a logic 1 by

hardware. Otherwise, the state of this bit is a logic 0.

1998 Aug 26 16

Philips Semiconductors Product speciﬁcation

Low voltage 8-bit microcontroller with 6-kbyte embedded RAM

11 I/O FACILITIES

11.1 Ports

The SZF2002 has 24 I/O lines: ports P1, P3 and P4 of which ports P1 and P3 are bit addressed (P0 and P2 are always used as address/data bus). Ports 0 to 4 have the following alternative functions:

Port 0 Used internally. Port 1 Used for a number of special functions:

• Provides the inputs for the external interrupts: INT2 to INT8

• The I2C-bus interface: SCL and SDA

• Counter inputs: T2 and T2EX.

Port 2 Used internally. Port 3 Pins can be configured individually to provide:

• External interrupt request inputs: INT1 and INT0

• Counter input: T1 and T0

• UART input and output: RXD and TXD.

SZF2002

Port 4 Provides chip select for external data memory:

RAMCE.

To enable a port pin alternative function, the port bit latch in its SFR must contain a logic 1.

Each port consists of a latch (SFRs P0 to P4), an output driver and input buffer. Ports 1, 3 and 4 have internal pull-ups (except P1.6 and P1.7). Figure 8 shows that the strong transistor ‘p1’ is turned on for only 2 clock periods after a LOW-to-HIGH transition in the port latch. When on, it turns on ‘p3’ (a weak pull-up) through the inverter. This inverter and ‘p3’ form a latch which holds the logic 1. In Port 0 the pull-up ‘p1’ is only on when emitting logic 1s for external memory access.

11.2 Port conﬁguration

The port pins (except for P1.6 and P1.7) are configured as shown in Fig.8. This is a quasi-bidirectional I/O with pull-up. The strong booster pull-up ‘p1’ is turned on for one clock period after a LOW-to-HIGH transition in the port latch. All port pins will be set to HIGH during reset.

handbook, full pagewidth

from port latch

read port pin

input data

2 clock

periods

strong pull-up

INPUT

BUFFER

Fig.8 Port configuration.

1998 Aug 26 17

I/O pin

MBK456

Philips Semiconductors Product speciﬁcation

Low voltage 8-bit microcontroller with 6-kbyte embedded RAM

12 TIMER/EVENT COUNTERS

The SZF2002 contains three 16-bit timer/event counter registers; Timer 0, Timer 1 and Timer 2 which can perform the following functions:

• Measure time intervals and pulse duration

• Count events

• Generate interrupt requests.

In the ‘Timer’ operating mode the register increments every machine cycle. Since a machine cycle consists of 6 clock periods, the count rate is1⁄6f

In the ‘Counter’ operating mode, the register increments in response to a HIGH-to-LOW transition. Since it takes 2 machine cycles (12 clock periods) to recognize a HIGH-to-LOW transition, the maximum count rate is

⁄12f

. To ensure a given level is sampled, it should be

clk

held for at least one complete machine cycle.

12.1 Timer 0 and Timer 1

Timer 0 and Timer 1 can be programmed independently to operate in four modes:

Mode 0 8-bit timer or 8-bit counter each with divide-by-32

prescaler.

Mode 1 16-bit time-interval or event counter. Mode 2 8-bit time-interval or event counter with automatic

reload upon overflow.

Mode 3 Timer 0 establishes TL0 and TH0 as two

separate counters.

12.2 Timer 2

Timer 2 is a 16-bit timer/up-down counter that can operate (like Timer 0 and 1) either as a timer or as an event counter. These functions are selected by the state of the C/T2 bit in the T2CON register; see Section 12.3.

Three operating modes are available: Capture, Auto-reload and Baud Rate Generator, which also are selected via the T2CON register.

12.2.1 C Figure 9 shows the Capture mode. Two options in this

mode may be selected by the EXEN2 bit in T2CON:

• If EXEN2 = 0, then Timer 2 is a 16-bit timer or counter that sets the Timer 2 overflow bit (TF2) on overflow, this can be used to generate an interrupt.

APTURE MODE

clk

SZF2002

• If EXEN2 = 1, Timer 2 operates as already described but with the additional feature that a HIGH-to-LOW transition at external input T2EX causes the current value in TL2 and TH2 to be captured into registers RCAP2L and RCAP2H respectively. In addition, the transition at T2EX causes the EXF2 bit in T2CON to be set; this may also be used to generate an interrupt.

12.2.2 A

Figure 10 shows the Auto-reload mode.

• Counting up (DCEN = 0) In the Auto-reload mode and counting up, registers

RCAP2L/RCAP2H are used to hold a reload value for TL2 /TH2 when Timer 2 rolls over. By setting/clearing bit EXEN2 in T2CON the external trigger input pin T2EX can be enabled/disabled. If EXEN2 = 0, then Timer 2 is a 16-bit timer/counter which upon overflow sets TF2, and reloads TL2/TH2 with the reload value held in RCAP2L/RCP2H. If EXEN2 = 1, then Timer 2 performs as above, but with the added feature that a HIGH-to-LOW transition at pin T2EX causes the current Timer 2 value (TL2/TH2 data) to be reloaded with the value held in RCAP2L/RAP2H, and bit EXF2 in T2CON to be set.

Timer 2 interrupt will be set if EXF2 is set or TF2 is set.

• Counting up (DCEN = 1 and T2EX = 1). In this mode Timer 2 will count up. When the timer overflows (FFFFH state), TF2 bit will be set. This will reload TL2 and TH2 with the contents of T2CAPL and T2CAPH, respectively. Also bit EXF2 will be toggled. Bit EXF2 can be used as the 17th bit if desired.

Timer 2 interrupt will be set only if TF2 is set.

• Counting down (DCEN = 1 and T2EX = 0.In this mode Timer 2 will be counting down. Underflow will occur when the contents of TL2/TH2 matches the contents of RCAP2L/RCAP2H. A Timer 2 roll-over from 0000H to FFFFH is not considered as an underflow. Upon underflow, bit TF2 will be set and registers TL2/TH2 will be loaded with FFFFH. In addition, an underflow will cause bit EXF2 to toggle, such that it can be used as the 17th bit if desired.

Timer 2 interrupt will be set only if TF2 is set.

12.2.3 B

The Baud Rate Generator mode is selected when RCLK0 = 1 or TCLK0 = 1 or RCLK1 = 1 or TCLK1 = 1. It will be described in conjunction with the serial port (UART); see Section 17.3.2.

UTO-RELOAD MODE

AUD RATE GENERATOR MODE

1998 Aug 26 18

Philips Semiconductors Product speciﬁcation

Low voltage 8-bit microcontroller with 6-kbyte embedded RAM

handbook, full pagewidth

clk

T2 PIN

T2EX PIN

C/T2 = 0

C/T2 = 1

transition

detector

control

TR2

capture

control

EXEN2

TL2

(8 BITS)

RCAP2L RCAP2H

TH2

(8 BITS)

TF2

EXF2

MGM136

SZF2002

Timer 2

interrupt

handbook, full pagewidth

clk

T2EX PIN

T2 PIN

C/T2 = 0

C/T2 = 1

transition

detector

Fig.9 Timer 2 in Capture mode.

control

EXEN2

control

TR2

reload

TL2

(8 BITS)

RCAP2L RCAP2H

(8 BITS)

TH2

TF2

EXF2

MGM137

Timer 2

interrupt

Fig.10 Timer 2 in Auto-reload mode.

1998 Aug 26 19

Philips Semiconductors Product speciﬁcation

Low voltage 8-bit microcontroller with

SZF2002

6-kbyte embedded RAM

12.3 Timer/Counter 2 Control Register (T2CON) Table 6 Timer/Counter 2 Control Register (SFR address C8H)

76543210

TF2 EXF2 RCLK0 TCLK0 EXEN2 TR2 C/

Table 7 Description of T2CON bits

BIT SYMBOL DESCRIPTION

7 TF2 Timer 2 overﬂow ﬂag. Set by a Timer 2 underﬂow or overﬂow and must be cleared by

software. TF2 will not be set when in either the Baud Rate generation mode or Clock out mode.

6 EXF2 Timer 2 external ﬂag. Set when either a capture or reload is caused by a negative

transition on T2EX and when EXEN2 = 1. In Auto-reload mode it is toggled on an underﬂow or overﬂow. Cleared by software.

5 RCLK0 Receive clock 0 ﬂag. When set, causes the UART to use Timer 2 overﬂow pulses.

RCLK0 = 0, causes Timer 1 overﬂow pulses to be used.

4 TCLK0 Transmit clock 0 ﬂag. When set, causes the UART to use Timer 2 overﬂow pulses.

TCLK0 = 0, causes Timer 1 overﬂow pulses to be used.

3 EXEN2 Timer 2 external enable ﬂag. When set, allows a capture or reload to occur, together

with an interrupt, as a result of a negative transition on input T2EX (if in Capture mode or Auto-reload mode with DCEN reset). If in Auto-reload mode and DCEN is set, this bit has no inﬂuence. In the other modes EXF2 is set and an interrupt is generated on a HIGH-to-LOW transition on T2EX pin. In all modes EXEN2 = 0, causes Timer 2 to

ignore events at T2EX. 2 TR2 Timer 2 start/stop control. When TR2 = 1, Timer 2 is started. 1C/

0 CP/

T2 Timer or counter select for Timer 2. C/T2 = 0, selects the internal timer with a clock

frequency of1⁄6f

triggered.

RL2 Capture/Reload ﬂag. Selection of Capture or Auto-reload mode.

. C/T2 = 1, selects the external event counter; negative edge

clk

T2 CP/RL2

1998 Aug 26 20

Philips Semiconductors Product speciﬁcation

Low voltage 8-bit microcontroller with

SZF2002

6-kbyte embedded RAM

12.4 Timer/Counter 2 Mode Register (T2MOD) Table 8 Timer/Counter 2 Mode Register (SFR address C9H)

76543210

−−RCLK1 TCLK1 − T2RD T2OE DCEN

Description of T2MOD bits

BIT SYMBOL DESCRIPTION

7 − These 2 bits are reserved. 6 − 5 RCLK1 Receive Clock 1 ﬂag. Reserved for future UART2. When set, causes the UART to use

Timer 2 overﬂow pulses. RCLK1 = 0, causes Timer 1 overﬂow pulses to be used. 4 TCLK1 Transmit Clock 1 ﬂag. Reserved for future UART2. When set, causes the UART to use

Timer 2 overﬂow pulses. TCLK1 = 0, causes Timer 1 overﬂow pulses to be used. 3 − This bit is reserved. 2 T2RD Timer 2 Read ﬂag. This bit is set by hardware if following a TL2 read and before a TH2

read, TH2 is incremented. It is reset on the trailing edge of the next TL2 read. 1 T2OE Timer 2 Output Enable. When set, output is activated to output a clock at the T2 pin

(Clock output mode). 0 DCEN Down Count Enable. When set, this allows Timer 2 to be conﬁgured as an up/down

counter.

Table 9 Timer 2 operating modes; note 1

RCLK0 + TCLK0 + RCLK1 + TCLK1 CP/

0 0 0 X 16-bit Auto-reload 0 1 0 X 16-bit Capture 1 X X X Baud Rate Generator

Note

1. X = don’t care

RL2 T2OE C/T2 MODE

1998 Aug 26 21

Philips Semiconductors Product speciﬁcation

Low voltage 8-bit microcontroller with 6-kbyte embedded RAM

12.5 Watchdog Timer (T3)

In addition to Timer 2 and the standard timers, a Watchdog Timer (consisting of an 11-bit prescaler and an 8-bit timer) is also available.

The Watchdog Timer is controlled by the Watchdog Enable Register (WDTKEY). When WDTKEY = 55H, the timer is disabled and the Power-down mode is enabled. Otherwise, the timer is enabled and the Power-down mode is disabled. In the Idle mode the Watchdog Timer and reset circuitry remain active.

The Watchdog Timer is shown in Fig.11. The timer frequency is derived from the clock frequency

using the formula shown below:

timer

------------------------------------------ -

When a timer overflow occurs, the microcontroller is reset. To prevent a system reset the timer must be reloaded in time by the application software.

clk

62048×()T3×

SZF2002

If the processor suffers a hardware/software malfunction, the software will fail to reload the timer.This failure will produce a reset upon overflow thus preventing the processor running out of control.

The Watchdog Timer can only be reloaded if the condition flag WLE (PCON.4) has been previously set by software. At the moment the counter is loaded the condition flag is automatically cleared. After reset the Watchdog Timer is off. The Watchdog Timer is started by loading a value into T3.

The time interval between the timer reloading and the occurrence of a reset is dependent upon the reloaded value. The time interval is derived from the clock and the value programmed into T3 and may be calculated as shown below:

reload

For example, this time period may range from 2 to 500 ms when using a clock frequency f

256 T3–()

----------------------------f

timer

= 6 MHz.

clk

handbook, full pagewidth

SFR WDTKEY

INTERNAL BUS

overflow

internal

reset

LOADEN

PCON.1

MGM141

RST

write

PRESCALER

11-BIT

CLEAR

TIMER T3 (8-BIT)

LOAD

LOADEN

CLEAR

WLE PD

PCON.4

INTERNAL BUS

clk

Fig.11 Functional diagram of the Watchdog Timer (T3).

1998 Aug 26 22

Philips Semiconductors Product speciﬁcation

Low voltage 8-bit microcontroller with 6-kbyte embedded RAM

13 PULSE WIDTH MODULATED OUTPUT

One Pulse Width Modulated output channel PWM is provided which outputs pulses of programmable length and interval. The repetition frequency is defined by an 8-bit prescaler (PWMP) that generates the clock for the counter. The 8-bit counter counts modulo 255, i.e. from 0 to 254 inclusive. The value held in the 8-bit counter is compared to the contents of the register PWM. If a new prescaler value is written in register PWMP the 8-bit counter finishes uninterrupted, and the new prescaler value is used in the next count cycle.

Provided the contents of this register are greater than the counter value, the PWM output is set HIGH. If the contents of register PWMP are equal to, or less than the counter value, the PWM output is set LOW.

The pulse-width-ratio is therefore defined by the contents of register PWM. The pulse-width-ratio will be in the range

255

⁄

0to

and may be programmed in increments of1⁄

255

SZF2002

The repetition frequency (f by:

PWM

For f

----------------------------------------------------------------1( PWMP) 255×+ 2×

= 12 MHz, the above formula gives a repetition

clk

frequency range of 92 Hz to 23.5 kHz. By loading the PWM register with either 00H or FFH, the

PWM output can be retained at a constant LOW or HIGH level respectively. When loading FFH into the PWM register, the 8-bit counter will never actually reach this value.

The PWM output pin is not shared with any other function.

) at the PWM output is given

PWM

handbook, full pagewidth

I N T E R N A

L B

U S

clk

PWMP

DIVIDE-BY-2

PWM

8-BIT COMPARATOR

8-BIT COUNTER

OUTPUT BUFFER

Fig.12 Functional diagram of Pulse Width Modulated output (PWM).

PWM

MGM140

1998 Aug 26 23

+ 53 hidden pages