Philips SCN68681C1N40, SCN68681E1F40 Datasheet

INTEGRATED CIRCUITS

SCN68681

Dual asynchronous receiver/transmitter (DUART)

Product specification Supersedes data of 1995 May 01 IC19 Data Handbook

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1998 Sep 04

Philips Semiconductors Product specification

SCN68681Dual asynchronous receiver/transmitter (DUART)

DESCRIPTION

The Philips Semiconductors SCN68681 Dual Universal Asynchronous Receiver/Transmitter (DUART) is a single-chip MOS-LSI communications device that provides two independent full-duplex asynchronous receiver/transmitter channels in a single package. It is compatible with other S68000 family devices, and can also interface easily with other microprocessors. The DUART can be used in polled or interrupt driven systems.

The operating mode and data format of each channel can be programmed independently. Additionally, each receiver and transmitter can select its operating speed as one of eighteen fixed baud rates, a 16X clock derived from a programmable counter/timer, or an external 1X or 16X clock. The baud rate generator and counter/timer can operate directly from a crystal or from external clock inputs. The ability to independently program the operating speed of the receiver and transmitter make the DUART particularly attractive for dual-speed channel applications such as clustered terminal systems.

Each receiver is quadruply buffered to minimize the potential of receiver overrun or to reduce interrupt overhead in interrupt driven systems. In addition, a flow control capability is provided to disable a remote DUART transmitter when the buffer of the receiving device is full.

Also provided on the SCN68681 are a multipurpose 6-bit input port and a multipurpose 8-bit output port. These can be used as general purpose I/O ports or can be assigned specific functions (such as clock inputs or status/interrupt outputs) under program control.

FEA TURES

•S68000 bus compatible

•Dual full-duplex asynchronous receiver/transmitter

•Quadruple buffered receiver data registers

•Programmable data format

– 5 to 8 data bits plus parity – Odd, even, no parity or force parity – 1, 1.5 or 2 stop bits programmable in 1/16-bit increments

•Programmable baud rate for each receiver and transmitter

selectable from:

– 22 fixed rates: 50 to 115.2k baud – Non-standard rates to 115.2kb – Non-standard user-defined rate derived from programmable

counter/timer

– External 1X or 16X clock

•16-bit programmable Counter/Timer

•Parity, framing, and overrun error detection

•False start bit detection

•Line break detection and generation

•Programmable channel mode

– Normal (full-duplex) – Automatic echo – Local loopback – Remote loopback

•Multi-function programmable 16-bit counter/timer

•Multi-function 6-bit input port

– Can serve as clock or control inputs – Change-of-state detection on four inputs – 100kΩ typical pull-up resistors

•Multi-function 8-bit output port

– Individual bit set/reset capability – Outputs can be programmed to be status/interrupt signals

•Versatile interrupt system

– Single interrupt output with eight maskable interrupting

conditions

– Interrupt vector output on interrupt acknowledge – Output port can be configured to provide a total of up to six

separate wire-ORable interrupt outputs

•Maximum data transfer rates:

1X - 1MB/sec, 16X - 125kB/sec

•Automatic wake-up mode for multidrop applications

•Start-end break interrupt/status

•Detects break which originates in the middle of a character

•On-chip crystal oscillator

•Single +5V power supply

•Commercial and industrial temperature ranges available

•DIP and PLCC packages

ORDERING INFORMATION

COMMERCIAL INDUSTRIAL

DESCRIPTION

40-Pin Ceramic Dual In-Line Package (cerdip) Not available SCN68681E1F40 0590B 40-Pin Plastic Dual In-Line Package (DIP) SCN68681C1N40 SCN68681E1N40 SOT129-1 44-Pin Plastic Leaded Chip Carrier (PLCC) SCN68681C1A44 SCN68681E1A44 SOT187-2

1998 Sep 04 853–1083 19970

VCC = +5V +5%,

= 0°C to +70°C

VCC = +5V +10%,

TA = 40°C to +85°C

DWG #

Philips Semiconductors Product specification

SCN68681Dual asynchronous receiver/transmitter (DUART)

PIN CONFIGURATIONS

IP3

IP1

IP0

R/WN

DTACKN

RxDB TxDB

OP1

OP3 OP5 OP7

D1 D3 D5

GND

1 2 3

4 5

6 7

8 9

DIP

11 12

13 14 15 16 17 18

40 39 38

37 36

35 34

33 32 31 30 29

28 27 26 25 24 23

22 2120

IP4 IP5

IACKN IP2

CSN RESETN

X2 X1/CLK RxDA TxDA OP0

OP2 OP4 OP6 D0 D2 D4

D6 INTRN

1 NC 16 OP5 31 OP2 2 A1 17 OP7 32 OP0 3 IP3 18 D1 33 TxDA 4A2 19D3 34NC 5 IP1 20 D5 35 RxDA 6 A3 21 D7 36 X1/CLK 7 A4 22 GND 37 X2 8 IP0 23 NC 38 RESETN 9 R/WN 24 INTRN 39 CSN 10 DTACKN 25 D6 40 IP2 11 RxDB 26 D4 41 IACKN 12 NC 27 D2 42 IP5 13 TxDB 28 D0 43 IP4

14 OP1 29 OP6 44 V 15 OP3 30 OP4

PLCC

PIN/FUNCTION

SD00107

Figure 1. Pin Configurations

ABSOLUTE MAXIMUM RATINGS

SYMBOL

T T

STG

Operating ambient temperature range Storage temperature range -65 to +150 °C All voltages with respect to ground

PARAMETER RATING UNIT

See Note 4 °C

-0.5 to +6.0 V

NOTES:

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not implied.

2. For operating at elevated temperatures, the device must be derated based on +150

C maximum junction temperature.

3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.

4. Parameters are valid over specified temperature range. See Ordering information table for applicable operating temperature range and V supply range.

1998 Sep 04

Philips Semiconductors Product specification

SCN68681Dual asynchronous receiver/transmitter (DUART)

BLOCK DIAGRAM

D0–D7

R/WN

DTACKN

CSN

A1–A4

RESETN

INTRN

IACKN

BUS BUFFER

OPERATION CONTROL

ADDRESS

DECODE

R/W CONTROL

INTERRUPT CONTROL

IMR ISR IVR

TIMING

BAUD RATE

GENERATOR

CLOCK

SELECTORS

CONTROL

TIMING

INTERNAL DATABUS

CHANNEL A

TRANSMIT

HOLDING REG

TRANSMIT

SHIFT REGISTER

RECEIVE

HOLDING REG (3)

RECEIVE

SHIFT REGISTER

MR1, 2

CRA SRA

CHANNEL B (AS ABOVE)

INPUT PORT

CHANGE OF

STATE

DETECTORS (4)

IPCR

ACR

TxDA

RxDA

TxDB

RxDB

IP0-IP5

X1/CLK

COUNTER/

TIMER

XTAL OSC

CSRA

CSRB

ACR

CTLR CTLR

OUTPUT PORT

FUNCTION

SELECT LOGIC

OPCR

OPR

OP0-OP7

GND

SD00108

Figure 2. Block Diagram

1998 Sep 04

Philips Semiconductors Product specification

SCN68681Dual asynchronous receiver/transmitter (DUART)

PIN DESCRIPTION

SYMBOL TYPE NAME AND FUNCTION

D0-D7 I/O Data Bus: Bidirectional 3-State data bus used to transfer commands, data and status between the DUART and the

CSN I Chip Select: Active-Low input signal. When Low, data transfers between the CPU and the DUART are enabled on

R/WN I Read/Write: A High input indicates a read cycle and a Low input indicates a write cycle, when a cycle is initiated by

A1-A4 I Address Inputs: Select the DUART internal registers and ports for read/write operations. RESETN I Reset: A Low level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), initializes the IVR to hex 0F, puts

DTACKN O Data Transfer Acknowledge: Three-state active Low output asserted in write, read, or interrupt cycles to indicate

INTRN O Interrupt Request: Active-Low, open-drain, output which signals the CPU that one or more of the eight maskable

IACKN I Interrupt Acknowledge: Active-Low input indicating an interrupt acknowledge cycle. In response, the DUART will

X1/CLK I Crystal 1: Crystal connection or an external clock input. A crystal of a clock the appropriate frequency (nominally

X2 I Crystal 2: Crystal connection. See Figure 9. If a crystal is not used it is best to keep this pin not connected although

RxDA I Channel A Receiver Serial Data Input: The least significant bit is received first. “Mark” is High, “space” is Low. RxDB I Channel B Receiver Serial Data Input: The least significant bit is received first. “Mark” is High, “space” is Low. TxDA O Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the

TxDB O Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the

OP0 O Output 0: General purpose output or Channel A request to send (RTSAN, active-Low). Can be deactivated

OP1 O Output 1: General purpose output or Channel B request to send (RTSBN, active-Low). Can be deactivated

OP2 O Output 2: General purpose output, or Channel A transmitter 1X or 16X clock output, or Channel A receiver 1X clock

OP3 O Output 3: General purpose output or open-drain, active-Low counter/timer output or Channel B transmitter 1X clock

OP4 O Output 4: General purpose output or Channel A open-drain, active-Low, RxRDYA/FFULLA output. OP5 O Output 5: General purpose output or Channel B open-drain, active-Low, RxRDYB/FFULLB output. OP6 O Output 6: General purpose output or Channel A open-drain, active-Low, TxRDYA output. OP7 O Output 7: General purpose output, or Channel B open-drain, active-Low, TxRDYB output. IP0 I Input 0: General purpose input or Channel A clear to send active-Low input (CTSAN). Pin has an internal V

IP1 I Input 1: General purpose input or Channel B clear to send active-Low input (CTSBN). Pin has an internal V

IP2 I Input 2: General purpose input, or Channel B receiver external clock input (RxCB), or counter/timer external clock

IP3 I Input 3: General purpose input or Channel A transmitter external clock input (TxCA). When the external clock is

IP4 I Input 4: General purpose input or Channel A receiver external clock input (RxCA). When the external clock is used

IP5 I Input 5: General purpose input or Channel B transmitter external clock input (TxCB). When the external clock is

GND I Ground:

CPU. D0 is the least significant bit.

D0-D7 as controlled by the R/WN, RDN and A1-A4 inputs. When High, places the D0-D7 lines in the 3-State condition.

assertion of the CSN input.

OP0-OP7 in the High state, stops the counter/timer, and puts Channel A and B in the inactive state, with the TxDA and TxDB outputs in the mark (High) state. Clears Test modes, sets MR pointer to MR1.

proper transfer of data between the CPU and the DUART.

interrupting conditions are true.

place the interrupt vector on the data bus and will assert DTACKN if it has an interrupt pending.

3.6864 MHz) must be supplied at all times. For crystal connections see Figure 9, Clock Timing.

it is permissible to ground it.

“mark” condition when the transmitter is disabled, idle or when operating in local loopback mode. “Mark” is High, “space” is Low.

‘mark’ condition when the transmitter is disabled, idle, or when operating in local loopback mode. ‘Mark’ is High, ‘space’ is Low.

automatically on receive or transmit.

output.

output, or Channel B receiver 1X clock output.

pull-up device supplying 1 to 4 A of current.

input. When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock. Pin has an internal V

pull-up device supplying 1 to 4 A of current.

used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an internal V pull-up device supplying 1 to 4 A of current.

by the receiver, the received data is sampled on the rising edge of the clock. Pin has an internal VCC pull-up device supplying 1 to 4 A of current.

used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an internal V pull-up device supplying 1 to 4 A of current.

I Power Supply: +5V supply input.

1998 Sep 04

Philips Semiconductors Product specification

SYMBOL

PARAMETER

TEST CONDITIONS

UNIT

µA

SCN68681Dual asynchronous receiver/transmitter (DUART)

DC ELECTRICAL CHARACTERISTICS T

= -40°C to +85°C, VCC = 5.0V ± 10%1, 2,

LIMITS

Min Typ Max

X1L

X1H

X2L

X2H

IOC I

Input low voltage 0.8 Input high voltage (except X1/CLK) Input high voltage (except X1/CLK)

5 4

2.5

Input high voltage (X1/CLK) 4 Output low voltage IOL = 2.4mA 0.4

Output high voltage (except o.d. outputs) Output high voltage (except o.d. outputs)

Input leakage current VIN = 0 to V Data bus 3-State leakage current VO = 0.4 to V

X1/CLK low input current VIN = 0, X2 grounded X1/CLK high input current VIN = VCC, X2 grounded

5 4

IOH = -400µA 2.4 V IOH = -400µA 2.9

VIN = 0, X2 floated

VIN = VCC, X2 floated

–10 10 –10 10

-4

-3

-1 0

-2

-1.5

0.2

3.5

0 0

mA mA

mA X2 low input current VIN = 0, X1/CLK floated -100 -30 0 µA X2 high input current VIN = VCC, X1/CLK floated 0 +30 100 µA

Open-collector output leakage current Power supply current 0°C to +70°C version

-40°C to +85°C version

VO = 0.4 to V

–10

150 175

µA

NOTES:

1. Parameters are valid over specified temperature range. See Ordering information table for applicable operating temperature range and V supply range.

2. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4V and 2.4V with a transition time of 20ns maximum. For X1/CLK this swing is between 0.4V and 4.4V . All time measurements are referenced at inpu t voltages of 0.8V and 2.0V as appropriate.

3. Typical values are at +25°C, typical supply voltages, and typical processing parameters.

< 0°C

4. T

5. T

> 0°C

1998 Sep 04

Philips Semiconductors Product specification

SYMBOL

PARAMETER

UNIT

SCN68681Dual asynchronous receiver/transmitter (DUART)

AC CHARACTERISTICS T

= -40°C to +85°C, VCC = 5.0V ± 10%

1, 2, 3, 4

LIMITS

Min Typ

Max

Reset Timing (See Figure 3)

RES

RESETN pulse width 200 ns

Bus Timing (See Figures 4, 5, 6)

RWS

RWH

CSW

CSD

DAL

DCR

DCW

DAH

DAT

CSC

A1-A4 setup time to CSN Low 10 ns A1-A4 hold time from CSN Low 100 ns RWN setup time to CSN High 0 ns RWN holdup time to CSN High 0 ns CSN High pulse width 90 ns

CSN or IACKN High from DTACKN Low 20 ns Data valid from CSN or IACKN Low 175 ns Data bus floating from CSN or IACKN High

100 ns Data setup time to CLK High 100 ns Data hold time from CSN High 20 ns DTACKN Low from read data valid 0 ns DTACKN Low (read cycle) from CLK High 125 ns DTACKN Low (write cycle) from CLK High 125 ns DTACKN High from CSN or IACKN High 100 ns DTACKN High impedance from CSN or IACKN High 125 ns

CSN or IACKN setup time to clock High 90 ns

Port Timing (See Figure 7)

Port input setup time to CSN Low 0 ns Port input hold time from CSN High 0 ns Port output valid from CSN High 400 ns

Interrupt Reset Timing (See Figure 8)

INTRN or OP3-OP7 when used as interrupts negated from:

Read RHR (RxRDY/FFULL interrupt) 300 ns Write THR (TxRDY interrupt) 300 ns

Reset command (delta break interrupt) 300 ns Stop C/T command (counter interrupt) 300 ns Read IPCR (input port change interrupt) 300 ns Write IMR (clear of interrupt mask bit) 300 ns

Clock Timing (See Figure 9)

CLK

CTC

X1/CLK High or Low time 100 ns

X1/CLK frequency 0 3.6864 4.0 MHz CTCLK High or Low time 100 ns CTCLK frequency 0 4.0 MHz RxC High or Low time 220 ns RxC frequency (16X)

(1X)

0 0

2.0

1.0 TxC High or Low time 220 ns TxC frequency (16X)

(1X)

0 0

2.0

1.0

MHz MHz

Transmitter Timing (See Figure 10)

TXD

TCS

TxD output delay from TxC external clock input on IP pin 350 ns Output delay from TxC low at OP pin to TxD data output 150 ns

Receiver Timing (See Figure 1 1)

RXS

RXH

RxD data setup time before RxC high at external clock input on IP pin 240 ns RxD data hold time after RxC high at external clock input on IP pin 200 ns

NOTES:

1. Parameters are valid over specified temp. range. See Ordering information table for applicable operating temp. and V

2. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4V and 2.4V with

supply range.

a transition time of 20ns maximum. For X1/CLK this swing is between 0.4V and 4.4V . All time measurements are referenced at input voltages of 0.8V and 2.0V as appropriate.

3. Typical values are at +25°C, typical supply voltages, and typical processing parameters.

4. Test conditions for outputs: C

5. This specification will impose maximum 68000 CPU CLK to 6MHz. Higher CPU CLK can be used if repeating bus reads are not performed.

= 150pF, except interrupt outputs. Test condition for interrupt outputs: CL = 50pF, R

= 2.7kΩ to VCC.

Consecutive write operations to the same command register require at least three edges of the X1 clock between writes.

6. This specification imposes a lower bound on CSN and IACKN Low, guaranteeing that it will be Low for at least 1 CLK period. This requirement is made on CSN only to insure assertion of DTACKN and not to guarantee operation of the part.

7. This spec is made only to insure that DTACKN is asserted with respect to the rising edge of the X1/CLK pin as shown in the timing diagram, not to guarantee operation of the part. If setup time is violated, DTACKN may be asserted as shown, or may be asserted 1 clock cycle later.

8. Operation to 0MHz is assured by design. Minimum test frequency is 2.0MHz.

1998 Sep 04

Philips Semiconductors Product specification

SCN68681Dual asynchronous receiver/transmitter (DUART)

BLOCK DIAGRAM

The SCN68681 DUART consists of the following eight major sections: data bus buffer, operation control, interrupt control, timing, communications Channels A and B, input port and output port. Refer to the Block Diagram.

Data Bus Buffer

The data bus buffer provides the interface between the external and internal data buses. It is controlled by the operation control block to allow read and write operations to take place between the controlling CPU and the DUART.

Operation Control

The operation control logic receives operation commands from the CPU and generates appropriate signals to internal sections to control device operation. It contains address decoding and read and write circuits to permit communications with the microprocessor via the data bus buffer. The DTACKN output is asserted during write and read cycles to indicate to the CPU that data has been latched on a write cycle, or that valid data is present on the bus on a read cycle.

Interrupt Control

A single active-Low interrupt output (INTRN) is provided which is activated upon the occurrence of any of eight internal events. Associated with the interrupt system are the Interrupt Mask Register (IMR) and the Interrupt Status Register (ISR), the Auditory Control Register(ACR) and the Interrupt Vector Register (IVR). The IMR may be programmed to select only certain conditions to cause INTRN to be asserted. The ISR can be read by the CPU to determine all currently active interrupting conditions. When IACKN is asserted, and the DUART has an interrupt pending, the DUART responds by placing the contents of the IVR register on the data bus and asserting DTACKN.

Outputs OP3-OP7 can be programmed to provide discrete interrupt outputs for the transmitter, receivers, and counter/timer.

Timing Circuits

The timing block consists of a crystal oscillator, a baud rate generator, a programmable 16-bit counter/timer, and four clock selectors. The crystal oscillator operates directly from a crystal connected across the X1/CLK and X2 inputs. If an external clock of the appropriate frequency is available, it may be connected to X1/CLK. The clock serves as the basic timing reference for the Baud Rate Generator (BRG), the counter/timer, and other internal circuits. A clock signal within the limits specified in the specifications section of this data sheet must always be supplied to the DUART. If an external is used instead of a crystal, X1 should be driven using a configuration similar to the one in Figure 9.

The baud rate generator operates from the oscillator or external clock input and is capable of generating 18 commonly used data communications baud rates ranging from 50 to 38.4k baud. The clock outputs from the BRG are at 16X the actual baud rate. The counter/timer can be used as a timer to produce a 16X clock for any other baud rate by counting down the crystal clock or an external clock. The four clock selectors allow the independent selection, for each receiver and transmitter, of any of these baud rates or external timing signal.

Counter/Timer (C/T)

The counter timer is a 16 bit programmable divider that operates one of three modes: Counter, T imer or Time Out mode. In all three modes it uses the 16-bit value loaded to the CTUR and CTLR registers. (Counter timer upper and lower preset registers).

•In the timer mode it generates a square wave.

•In the counter mode it generates a time delay.

•In the time out mode it monitors the receiver data flow and signals

data flow has paused. In the time out mode the receiver controls the starting/stopping of the C/T.

The counter operates as a down counter and sets its output bit in the ISR (Interrupt Status Register) each time it passes through 0. The output of the counter/timer may be seen on one of the OP pins or as an Rx or Tx clock.

The Timer/Counter is controlled with six (6) “commands”; Start C/T, Stop C/T, write C/T, preset registers, read C/T value, set or reset time out mode.

Please see the detail of the commands under the Counter/Timer register descriptions.

Communications Channels A and B

Each communications channel of the SCN68681 comprises a full-duplex asynchronous receiver/transmitter (DUART). The operating frequency for each receiver and transmitter can be selected independently from the baud rate generator, the counter timer, or from an external input.

The transmitter accepts parallel data from the CPU, converts it to a serial bit stream, inserts the appropriate start, stop, and optional parity bits and outputs a composite serial stream of data on the TxD output pin. The receiver accepts serial data on the RxD pin, converts this serial input to parallel format, checks for start bit, stop bit, parity bit (if any), or break condition and sends an assembled character to the CPU.

The input port pulse detection circuitry uses a 38.4kHz sampling clock derived from one of the baud rate generator taps. This results in a sampling period of slightly more than 25µs (assuming that the clock input is 3.6864MHz). The detection circuitry, in order to guarantee a true change in level has occurred, requires that two successive samples at the new logic level be observed. As a consequence, the minimum duration of the signal change is 25µs if the transition occurs coincident with the first sample pulse. The 50µs time refers to the situation in which the change of state is just missed and the first change of state is not detected until 25µs later.

Input Port

The inputs to this unlatched 6-bit port can be read by the CPU by performing a read operation at address H‘D’. A High input results in a logic 1 while a Low input results in a logic 0. D7 will always read as a logic 1 and D6 will reflect the level of IACKN. The pins of this port can also serve as auxiliary inputs to certain portions of the DUART logic.

Four change-of-state detectors are provided which are associated with inputs IP3, IP2, IP1 and IP0. A High-to-Low or Low-to-High transition of these inputs, lasting longer than 25 - 50µs, will set the corresponding bit in the input port change register. The bits are cleared when the register is read by the CPU. Any change-of-state can also be programmed to generate an interrupt to the CPU.

All the IP pins have a small pull-up device that will source 1 to 4 A of current from V

connections if they are not used.

Output Port

The 8-bit multipurpose output port can be used as a general purpose output port, in which case the outputs are the complements

. These pins do not require pull-up devices or

1998 Sep 04

Philips Semiconductors Product specification

SCN68681Dual asynchronous receiver/transmitter (DUART)

of the Output Port Register (OPR). OPR[n] = 1 results in OP[n] = Low and vice versa. Bits of the OPR can be individually set and reset. A bit is set by performing a write operation at address H’E’ with the accompanying data specifying the bits to be reset (1 = set, 0 = no change). Likewise, a bit is reset by a write at address H’F’ with the accompanying data specifying the bits to be reset (1 = reset, 0 = no change).

Outputs can be also individually assigned specific functions by appropriate programming of the Channel A mode registers (MR1A, MR2A), the Channel B mode registers (MR1B, MR2B), and the Output Port Configuration Register (OPCR).

Please note that these pins drive both high and low. HOWEVER when they are programmed to represent interrupt type functions (such as receiver ready, transmitter ready or counter/timer ready) they will be switched to an open drain configuration in which case an external pull-up device would be required.

OPERATION Transmitter

The SCN68681 is conditioned to transmit data when the transmitter is enabled through the command register. The SCN68681 indicates to the CPU that it is ready to accept a character by setting the TxRDY bit in the status register. This condition can be programmed to generate an interrupt request at OP6 or OP7 and INTRN. When a character is loaded into the Transmit Holding Register (THR), the above conditions are negated. Data is transferred from the holding register to transmit shift register when it is idle or has completed transmission of the previous character. The TxRDY conditions are then asserted again which means one full character time of buffering is provided. Characters cannot be loaded into the THR while the transmitter is disabled.

The transmitter converts the parallel data from the CPU to a serial bit stream on the TxD output pin. It automatically sends a start bit followed by the programmed number of data bits, an optional parity bit, and the programmed number of stop bits. The least significant bit is sent first. Following the transmission of the stop bits, if a new character is not available in the THR, the TxD output remains High and the TxEMT bit in the Status Register (SR) will be set to 1. Transmission resumes and the TxEMT bit is cleared when the CPU loads a new character into the THR. If the transmitter is disabled, it continues operating until the character currently being transmitted is completely sent out. The transmitter can be forced to send a continuous Low condition by issuing a send break command.

The transmitter can be reset through a software command. If it is reset, operation ceases immediately and the transmitter must be enabled through the command register before resuming operation. If CTS operation is enable, the CTSN input must be Low in order for the character to be transmitted. If it goes High in the middle of a transmission, the character in the shift register is transmitted and TxDA then remains in the marking state until CTSN goes Low. The transmitter can also control the deactivation of the RTSN output. If programmed, the RTSN output will be reset one bit time after the character in the transmit shift register and transmit holding register (if any) are completely transmitted, if the transmitter has been disabled.

Receiver

The SCN68681 is conditioned to receive data when enabled through the command register. The receiver looks for a High-to-Low (mark-to-space) transition of the start bit on the RxD input pin. If a transition is detected, the state of the RxD pin is sampled each 16X

clock for 7-1/2 clocks (16X clock mode) or at the next rising edge of the bit time clock (1X clock mode). If RxD is sampled High, the start bit is invalid and the search for a valid start bit begins again. If RxD is still Low, a valid start bit is assumed and the receiver continues to sample the input at one bit time intervals at the theoretical center of the bit, until the proper number of data bits and parity bit (if any) have been assembled, and one stop bit has been detected. The least significant bit is received first. The data is then transferred to the Receive Holding Register (RHR) and the RxRDY bit in the SR is set to a 1. This condition can be programmed to generate an interrupt at OP4 or OP5 and INTRN. If the character length is less than 8 bits, the most significant unused bits in the RHR are set to zero.

After the stop bit is detected, the receiver will immediately look for the next start bit. However, if a non-zero character was received without a stop bit (framing error) and RxD remains Low for one half of the bit period after the stop bit was sampled, then the receiver operates as if a new start bit transition had been detected at that point (one-half bit time after the stop bit was sampled).

The parity error, framing error, and overrun error (if any) are strobed into the SR at the received character boundary, before the RxRDY status bit is set. If a break condition is detected (RxD is Low for the entire character including the stop bit), a character consisting of all zeros will be loaded into the RHR and the received break bit in the SR is set to 1. The RxD input must return to high for two (2) clock edges of the X1 crystal clock for the receiver to recognize the end of the break condition and begin the search for a start bit. This will

usually require a high time of one X1 clock period or 3 X1 edges since the clock of the controller is not synchronous to the X1 clock.

Receiver FIFO

The RHR consists of a First-In-First-Out (FIFO) stack with a capacity of three characters. Data is loaded from the receive shift register into the topmost empty position of the FIFO. The RxRDY bit in the status register is set whenever one or more characters are available to be read, and a FFULL status bit is set if all three stack positions are filled with data. Either of these bits can be selected to cause an interrupt. A read of the RHR outputs the data at the top of the FIFO. After the read cycle, the data FIFO and its associated status bits (see below) are ‘popped’ thus emptying a FIFO position for new data.

Receiver Status Bits

In addition to the data word, three status bits (parity error, framing error, and received break) are also appended to each data character in the FIFO (overrun is not). Status can be provided in two ways, as programmed by the error mode control bit in the mode register. In the ‘character’ mode, status is provided on a character-by-character basis; the status applies only to the character at the top of the FIFO. In the ‘block’ mode, the status provided in the SR for these three bits is the logical-OR of the status for all characters coming to the top of the FIFO since the last ‘reset error’ command was issued. In either mode reading the SR does not affect the FIFO. The FIFO is ‘popped’ only when the RHR is read. Therefore the status register should be read prior to reading the FIFO.

If the FIFO is full when a new character is received, that character is held in the receive shift register until a FIFO position is available. If an additional character is received while this state exits, the contents of the FIFO are not affected; the character previously in the shift register is lost and the overrun error status bit (SR[4]) will be set-upon receipt of the start bit of the new (overrunning) character).

1998 Sep 04

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