Philips SCN2652AC2A44, SCN2652AC2F40, SCN2652AC2N40, SCN68652AC2A44, SCN68652AC2F40 Datasheet

INTEGRATED CIRCUITS

SCN2652/SCN68652

Multi-protocol communications controller
(MPCC)

Product specification
IC19 Data Handbook

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1995 May 01

Philips Semiconductors Product specification

SCN2652/SCN68652Multi-protocol communications controller (MPCC)

DESCRIPTION

The SCN2652/68652 Multi-Protocol Communications Controller
(MPCC) is a monolithic n-channel MOS LSI circuit that formats,
transmits and receives synchronous serial data while supporting
bit-oriented or byte control protocols. The chip is TTL compatible,
operates from a single +5V supply, and can interface to a processor
with an 8 or 16-bit bidirectional data bus.

APPLICATIONS

•Intelligent terminals

•Line controllers

•Network processors

•Front end communications

•Remote data concentrators

•Communication test equipment

•Computer to computer links

PIN CONFIGURATION

1

RxC

2

RxSI

3

S/F

4

RxA

5

RxDA

6

RxSA

7

RxE

8

GND

9
10
11
12

13

14
15
16
17
18

19

DIP

TOP VIEW

DB08

DB09

DB10

DB11

DB12
DB13

DB14
DB15

/W

R

A2
A1 A0

40CE

MM

39

TxC

38

TxSQ

37

TxE

36

TxU

35

TxBE

34

TxA

33

RESET

32

V

CC

DB00

31

DB01

30

DB02

29

DB03

28

DB04

27
26

DB05

25

DB06

24

DB07

23

DBEN

22

BYTE

2120

FEA TURES

•DC to 2Mbps data rate

•Bit-oriented protocols (BOP): SDLC, ADCCP, HDLC

•Byte-control protocols (BCP): DDCMP, BISYNC (external CRC)

•Programmable operation

– 8 or 16-bit tri-state data bus
– Error control – CRC or VRC or none
– Character length – 1 to 8 bits for BOP or 5 to 8 bits for BCP
– SYNC or secondary station address comparison for BCP-BOP
– Idle transmission of SYNC/FLAG or MARK for BCP-BOP

•Automatic detection and generation of special BOP control

sequences, i.e., FLAG, ABORT, GA

•Zero insertion and deletion for BOP

•Short character detection for last BOP data character

•SYNC generation, detection, and stripping for BCP

•Maintenance mode for self-testing

•TTL compatible

•Single +5V supply

INDEX

CORNER

NOTE: DB00 is least significant bit, highest number
(that is, DB15, A2) is most significant bit.

6

7

17

18

Pin Function Pin Function

1NC 23NC
2CE 24A0
3 RxC 25 BYTE
4 RxSI 26 DBEN
5 S/F 27 DB07
6 RxA 28 DB06
7 RxDA 29 DB05
8 RxSA 30 DB04
9 RxE 31 DB03
10 GND 32 DB02
11 DB08 33 DB01
12 NC 34 NC
13 DB09 35 DB00

14 DB10 36 V
15 DB11 37 RESET
16 DB12 38 TxA
17 DB13 39 TxBE
18 DB14 40 TxU
19 DB15 41 TxE
20 R
21 A2 43 TxC
22 A1 44 MM

1

PLCC

TOP VIEW

/W 42 TxSQ

40

39

29

28

CC

SD00057

Figure 1. Pin Configuration

1995 May 01 853-1068 15179

2

Philips Semiconductors Product specification

SCN2652/SCN68652Multi-protocol communications controller (MPCC)

ORDERING CODE

VCC = 5V +5%

PACKAGES

Commercial

0°C to +70°C

Industrial

-40°C to +85°C

40-Pin Ceramic Dual In-Line Package (DIP) SCN2652AC2F40 / SCN68652AC2F40 0590B
40-Pin Plastic Dual In-Line Package (DIP) SCN2652AC2N40 / SCN68652AC2N40 Contact Factory SOT129-1
44-Pin Square Plastic Lead Chip Carrier (PLCC) SCN2652AC2A44 / SCN68652AC2A44 Contact Factory SOT187-2

DWG #

ABSOLUTE MAXIMUM RATINGS

SYMBOL

T
T
V

A
STG

CC

Operating ambient temperature
Storage temperature –65 to +150 °C
All inputs with respect to GND

1

PARAMETER RATING UNIT

2

3

Note 4 °C

–0.3 to +7 V

NOTES:

1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or at any other condition above those indicated in the operation sections of this specification
is not implied.

2. For operating at elevated temperatures the device must be derated based on +150

°

C maximum junction temperature.

3. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.

4. Parameters are valid over operating temperature range unless otherwise specified. See ordering code table for applicable temperature
range and operating supply range.

BLOCK DIAGRAM

DB15–

DB00

RESET

MM

DATA

BUS

BUFFER

PARAMETER CONTROL

16

16 BITS

SYNC/ADDRESS

REGISTER

RECEIVER

DATA/STATUS

REGISTER

PCSAR

RDSR

8 BITS

PARAMETER

CONTROL
REGISTER

TRANSMITTER

DATA/STATUS

REGISTER

PCR

TDSR

V

CC

GND

1995 May 01

A2–A0

BYTE

R

CE

DBEN

/W

RxE

RxA
RxDA
RxSA

TxE

TxA

TxBE

TxU

S/F

READ/
WRITE
LOGIC

AND

CONTROL

INTERNAL
BUS

RECEIVER

LOGIC AND

CONTROL

Figure 2. Block Diagram

3

16

RxC RxSI TxC TxSO

16

TRANSMITTER

LOGIC AND

CONTROL

SD00058

Philips Semiconductors Product specification

SCN2652/SCN68652Multi-protocol communications controller (MPCC)

PIN DESCRIPTION

MNEMONIC PIN NO. TYPE NAME AND FUNCTION

DB15–DB00

A2–A0 19–21 I

BYTE 22 I
CE 1 I Chip Enable: A high input permits a data bus operation when DBEN is activated.

R/W 18 I

DBEN 23 I

RESET 33 I Reset: A high level initializes all internal registers (to zero) and timing.
MM 40 I

RxE 8 I

RxA 5 O

RxDA* 6 O

RxC 2 I
S/F 4 O SYNC/FLAG: S/F is asserted for one RxC clock time when a SYNC or FLAG character is detected.
RxSA* 7 O
RxSI 3 I Receiver Serial Input: RxSI is the received serial data. Mark = ‘1’, space = ‘0’.

TxE 37 I

TxA 34 O

TxBE* 35 O

TxU* 36 O

TxC 39 I
TxSO 38 O Transmitter Serial Output: TxSO is the transmitted serial data. Mark = ‘1’, space = ‘0’.

V

CC

GND 9 I Ground: 0V reference ground.

*Indicates possible interrupt signal

17–10
24–31

32 I +5V: Power supply.

Data Bus: DB07–DB00 contain bidirectional data while DB15–DB08 contain control and status
information to or from the processor. Corresponding bits of the high and low order bytes can be wire

I/O

OR’ed onto an 8-bit bus. The data bus is floating if either CE or DBEN are low.
Address Bus: A2–A0 select internal registers. The four 16-bit registers can be addressed on a word or

byte basis. See Register Address section.
Byte: Single byte (8-bit) data bus transfers are specified when this input is high. A low level specifies

16-bit data bus transfers.

Read/Write: R/W controls the direction of data bus transfer . When high, the data is to be loaded into the
addressed register. A low input causes the contents of the addressed register to be presented on the
data bus.

Data Bus Enable: After A2–A0, CE, BYTE and R/W are set up, DBEN may be strobed. During a read,
the 3-state data bus (DB) is enabled with information for the processor. During a write, the stable data is
loaded into the addressed register and TxBE will be reset if TDSR was addressed.

Maintenance Mode: MM internally gates TxSO back to RxSI and TxC to RxC for off line diagnostic
purposes. The RxC and RxSI inputs are disabled and TxSO is high when MM is asserted.

Receiver Enable: A high level input permits the processing of RxSI data. A low level disables the
receiver logic and initializes all receiver registers and timing.

Receiver Active: RxA is asserted when the first data character of a message is ready for the processor.
In the BOP mode this character is the address. The received address must match the secondary station
address if the MPCC is a secondary station. In BCP mode, if strip-SYNC (PCSAR13) is set, the first
non-SYNC character is the first data character; if strip-SYNC is zero, the character following the second
SYNC is the first data character. In the BOP mode, the closing FLAG resets RxA. In the BCP mode, RxA
is reset by a low level at RxE.

Receiver Data Available: RxDA is asserted when an assembled character is in RDSRL and is ready to
be presented to the processor. This output is reset when RDSRL is read.

Receiver Clock: RxC (1X) provides timing for the receiver logic. The positive going edge shifts serial
data into the RxSR from RxSI.

Receiver Status Available: RxSA is asserted when there is a zero to one transition of any bit in RDSR
except for RSOM. It is cleared when RDSRH is read.

Transmitter Enable: A high level input enables the transmitter data path between TDSRL and TxSO. At
the end of a message, a low level input causes TxSO = 1(mark) and TxA = 0 after the closing FLAG
(BOP) or last character (BCP) is output on TxSO.

Transmitter Active: TxA is asserted after TSOM (TDSR8) is set and TxE is raised. This output will reset
when TxE is low and the closing FLAG (BOP) or last character (BCP) has been output on TxSO.

Transmitter Buffer Empty: TxBE is asserted when theTDSR is ready to be loaded with new control
information or data. The processor should respond by loading theTDSR which resets TxBE.

Transmitter Underrun: TxU is asserted during a transmit sequence when the service of TxBE has been
delayed for one character time. This indicates the processor is not keeping up with the transmitter. Line
fill depends on PCSAR
falling edge of TxC.

Transmitter Clock: TxC (1X) provides timing for the transmitter logic. The positive going edge shifts
data out of the TxSR to TxSO.

. TxU is reset by RESET or setting of TSOM (TDSR8), synchronized by the

11

H

1995 May 01

4

Philips Semiconductors Product specification

These registers are used for character assembly (CSSR

,), y(),

SCN2652/SCN68652Multi-protocol communications controller (MPCC)

Table 1. Register Access

REGISTERS NO. OF BITS DESCRIPTION*

Addressable

PCSAR

Parameter control sync/
address register

16

PCR Parameter control register 8 RDSRH contains receiver status information.
RDSR Receive data/status register 16 RDSRL = RxDB contains the received assembled character.

TDSR Transmit data/status register 16

Non-Addressable

CCSR Control character shift register 8
HSR Holding shift register 16
RxSR Receiver shift register 8
TxSR Transmitter shift register 8

RxCRC

TxCRC

Receiver CRC accumulation
register

Transmitter CRC generation
register

16

16

NOTES:

*H = High byte – bits 15–8
L = Low byte – bits 7–0

Table 2. Error Control

CHARACTER DESCRIPTION

FCS Frame check sequence is transmitted/received

BCC Block check character is transmitted/received as

as 16 bits following the last data character of a
BOP message. The divisor is usually
CRC–CCITT (X

16

+ X12 + X5 + 1) with dividend
preset to 1’s but can be other wise determined
by ECM. The inverted remainder is transmitter as
the FCS.

two successive characters following the last data
character of a BCP message. The polynomial is
CRC–16 (X

16

+ X15 + X2 + 1) or CRC–CCITT
with dividend preset to 0’s (as specified by
ECM). The true remainder is transmitted as the
BCC.

PCSARH and PCR contain parameters common to the
receiver and transmitter. PCSARL contains a programmable
SYNC character (BCP) or secondary station address (BOP).

TDSRH contains transmitter command and status
information. TDSRL = TxDB contains the character to be
transmitted

HSR, RxSR), disassembly (TxSR), and CRC
accumulation/generation (RxCRC, TxCRC).

Table 3. Special Characters

OPERATION BIT PATTERN FUNCTION

BOP

FLAG 01111110 Frame message
ABORT 11111111 generation Terminate communication

01111111 detection
GA 01111111
Address (PCSARL)

1

BCP

SYNC

(PCSARL) or

2

(TxDB)

generation

NOTES:

1. ( ) = contents of.

2. For IDLE = 0 or 1 respectively.

Terminate loop mode
repeater function

Secondary station address

Character synchronization

,

APAPCSAR

PCR

RDSR

TDSR

NOTE:

Refer to Register Formats for mnemonics and description.

1995 May 01

RERR

TERR15NOT DEFINED

15

PROTO14SS/GA13SAM12IDLE

15 14 13 12 11

TxCL

15

14 13

A B C

14 13

T

R

x

x

C

L

E

12

11

RAB/

ROR

GA

TGA12TABORT11TEOM

Figure 3. Short Form Register Bit Formats

11

10

98

E C M

10 9 8

C

10 9 8

10 9 8

RxCL

L

E

REOM

5

76543210

S/AR

RxDBRSOM

TxDBTSOM

SD00059

Philips Semiconductors Product specification

SCN2652/SCN68652Multi-protocol communications controller (MPCC)

RxSI

XMITTER

MM

S/F

NOTES:

1. Detected in SYNC FF and 7 MS bits of CCSR.

2. In BOP mode, a minimum of two data characters must be received to turn the receiver active.

FROM

M
U
X

SEL

SYNC

FF

1-BIT

DELAY

CCSR (8)

SYNC/FLAG

COMPARATOR

BCP

PARITY (BCP)

RESET

RxE

RxA

RxDA
RxSA

ZERO (BOP)

DELETION

LOGIC

LOGIC

RxCRC ACC

1

BOP

M
U
X

Figure 4. MPCC Receiver Data Path

8 8

HSR (16)

ZERO
DELETION
CONTROL

CRC–16 (BCP) OR

CCRC–CCITT

(BOP)

RECEIVER
CONTROL

LOGIC

RxC

BCP . CRC
BOP . CRC
BCP . CRC

BOP

.

CRC

M
U

X

CRC–16 = 0

COMPARATOR

CRC–CCIT = F0B8

TO

RDSR

RxSR (8)

L

RERR

SD00060

FROM

OR PCSAR

TDSAR

L

RESET

TxE
TxA

TxBE

TxU

NOTES:

1. TxCRC selected if TEOM = 1 and the last data character has been shifted out of TxSR.

2. In BCP parity selected will be generated after each character is shifted out of TxSR.

TRANS­MITTER

CONTROL

LOGIC

TxC

TXSR (8)

TXCRC ACC (16)

CRC–16 OR CRC–CCITT

FLAG ABORT GA

(SYNC)

L

CONTROL
CHARACTER
GENERATOR

Figure 5. MPCC Transmitter Data Path

SEL

SYNC

FF

1 BIT

DELAY

M

U
X

1, 2

BOP

ZERO

INSERTION

LOGIC

BCP

PARITY

GENERATION

TxSO

ZERO
INSERTION
CONTROL

SD00088

1995 May 01

6

Philips Semiconductors Product specification

SCN2652/SCN68652Multi-protocol communications controller (MPCC)

FUNCTIONAL DESCRIPTION

The MPCC can be functionally partitioned into receiver logic,
transmitter logic, registers that can be read or loaded by the
processor, and data bus control circuitry. The register bit formats are
shown in Figure 3 while the receiver and transmitter data paths are
depicted in Figures 4 and 3.

RECEIVER OPERATION
General

After initializing the parameter control registers (PCSAR and PCR),
the RxE input must be set high to enable the receiver data path. The
serial data on the RxSI is synchronized and shifted into an 8-bit
Control Character Shift Register (CCSR) on the rising edge of RxC.
A comparison between CCSR contents and the FLAG (BOP) or
SYNC (BCP) character is made until a match is found. At that time,
the S/F output is asserted for one RxC time and the 16-bit Holding
Shift Register (HSR) is enabled. The receiver then operates as
described below.

BOP Operation

A flowchart of receiver operation in BOP mode appears in Figure 6.
Zero deletion (after five ones are received) is implemented on the
received serial data so that a data character will not be interpreted
as a FLAG, ABORT, or GA. Bits following the FLAG are shifted
through the CCSR, HSR, and into the Receiver Shift Register
(RxSR). A character will be assembled in the RxSR and transferred
to the RDSR
RxDA output will be asserted and the processor must take the
character no later than one RxC time after the next character is
assembled in the RxSR. If not, an overrun (RDSR11 = 1) will occur
and succeeding characters will be lost.

The first character following the FLAG is the secondary station
address. If the MPCC is a secondary station (PCSAR
contents of RxSR are compared with the address stored in
PCSAR
for the station; the RxA output is asserted, the character is loaded
into RDSR
(RSOM) is set. No match indicates that another station is being
addressed and the receiver searches for the next FLAG.

If the MPCC is a primary station, (PCSAR
address check is made; RxA is asserted and RSOM is set once the
first non-FLAG character has been loaded into RDSR
has been asserted. Extended address field can be supported by
software if PCSAR

When the 8 bits following the address character have been loaded
into RDSR
The processor should read this 8-bit character and interpret it as the
Control field.

Received serial data that follows is read and interpreted as the
information field by the processor. It will be assembled into character
lengths as specified by PCR
time a character has been transferred into RDSR
when RDSR
when RxSA is asserted. This occurs on a zero to one transition of
any bit in RDSR
except RSOM are cleared when RDSRH is read. The processor

for presentation to the processor. At that time the

L

= 1), the

12

. A match indicates the forthcoming message is intended

L

, RxDA is asserted and the Receive Start of Message bit

L

= 0), no secondary

12

and RxDA

L

= 0.

12

and RxDA has been asserted, RSOM will be cleared.

L

. As before, RxDA is asserted each

8–10

is read by the processor. RDSRH should only be read

L

except for RSOM. RxSA and all bits in RDSR

H

and is cleared

L

H

should check RDSR
set, then RDSR

12–15

each time RxSA is asserted. If RDSR9 is

9–15

should be examined.

Receiver character length may be changed dynamically in response
to RxDA: read the character in RxDB and write the new character
length into RxCL. The character length will be changed on the next
receiver character boundary . A received residual (short) character
will be transferred into RxDB after the previous character in RxDB
has been read, i.e. there will not be an overrun. In general the last
two characters are protected from overrun.

The CRC–CCITT, if specified by PCSAR

, is accumulated in

8–10

RxCRC on each character following the FLAG. When the closing
FLAG is detected in the CCSR, the received CRC is in the 16-bit
HSR. At that time, the Receive End of Message bit (REOM) will be
set; RxSA and RxDA will be asserted. The processor should read
the last data character in RDSR
RDSR

. If RDSR15 = 1, there has been a transmission error; the

9–15

accumulated CRC–CCITT is incorrect. If RDSR

and the receiver status in

L

≠ 0, last data

12–14

character is not of prescribed length. Neither the received CRC nor
closing FLAG are presented to the processor. The processor may
drop RxE or leave it active at the end of the received message.

RxBCP Operation

The operation of the receiver in BCP mode is shown in Figure 7.
The receiver initially searches for two successive SYNC characters,
of length specified by PCR
The next non-SYNC character or next SYNC character, if stripping is
not specified (PCSAR

13

enables the receiver data path. Once enabled, all characters are
assembled in RxSR and loaded into RDSR
character is available in RDSR
transition of any bit in RDSR
or RDSR

are read respectively.

H

If CRC–16 error control is specified by PCSAR
must determine the last character received prior to the CRC field.
When that character is loaded into RDSR
the received CRC will be in CCSR and HSR
transmission error, the processor must read the receiver status
(RDSR

) and examine RDSR15. This bit will be set for one

H

character time if an error free message has been received. If
RDSR

= 0, the CRC–16 is in error. The state of RDSR15 in BCP

15

CRC mode does not set RxSA. Note that this bit should be
examined only at the end of a message. The accumulated CRC will
include all characters starting with the first non-SYNC character if
PCSAR
PCSAR

= 1, or the character after the opening two SYNCs if

13

= 0. This necessitates external CRC generation/checking

13

when supporting IBM’s
BISYNC. This can be accomplished using the Philips

Semiconductors SCN2653 Polynomial Generator/Checker. See
Typical Applications.

If VRC has been selected for error control, parity (odd or even) is
regenerated on each character and checked when the parity bit is
received. A discrepancy causes RDSR
asserted. This must be sensed by the processor. The received parity
bit is stripped before the character is presented to the processor.

When the processor has read the last character of the message, it
should drop RxE which disables the receiver logic and initializes all
receiver registers and timing.

, that match the contents of PCSARL.

8–10

= 0), causes RxA to be asserted and

. RxDA is active when a

. RxSA is active on a 0 to 1

L

. The signals are cleared when RDSRl

H

L

, the processor

8–10

and RxDA is asserted,

L

. To check for a

L

to be set and RxSA to be

15

1995 May 01

7

Philips Semiconductors Product specification

SCN2652/SCN68652Multi-protocol communications controller (MPCC)

PROCESSOR

FOR ONE RxC

BIT TIME

RxA = 1

RSOM = 1

FOR ONE

CHARACTER

TIME

RxE = 1

S/F = 1

START OF
MESSAGE

INITIALIZE PCSAR, PCR

RxE
= 1?

FLAG

IN CCSR*

?

FLAG

IN CCSR*

?

ASSEMBLE CHARACTER

IN RxSR. ZERO DELETION,

ACCUMULATE CRC IF

SPECIFIED

IS

NO

IT 1st
CHARACTER
AFTER FLAG

?

YES

SEC.

STATION

MODE

?

NO
(PCSAR

RxSR → RxDB

YES

YES

NO

(PCSAR

NO

NO

YES

SECONDARY
STATION
ADDRESS

YES

= 1)

12

= 0)

12

A

* TEST MADE

EVERY RxC TIME

(1) OVERRUN (ROVRN)

CAUSES LOSS OF
SUBSEQUENT
CHARACTERS

IS

CHARACTER

= PCSAR

L

?

YES

NO

RxDA = 1

(PROCESSOR

SHOULD

READ RxDB)

(PROCESSOR SHOULD

READ AND EXAMINE

RDSR

H

ROVRN, ABC, RERR)

S/F = 1 FOR ONE RxC

RXSA = 1

– REOM, RAB/GA,

BIT TIME

REOM = 1, RxA = 0

RECEIVER

STATUS BIT 0 → 1

EXCEPT RSOM

IN CCSR*

Figure 6. BOP Receive

TRANSMITTER OPERATION
General

After the parameter control registers (PCSAR and PCR) have been
initialized, TxSO is held at mark until TSOM (TDSR
is raised. Then, transmitter operation depends on protocol mode.

1995 May 01

) is set and TxE

8

?

YES

FLAG

?

YES – END OF MESSAGE

NO

NO

TxBOP Operation

Transmitter operation for BOP is shown in Figure 8. A FLAG is sent
after the processor sets the Transmit Start of Message bit (TSOM)
and raises TxE. The FLAG is used to synchronize the message that
follows. TxA will also be asserted. When TxBE is asserted by the

8

RxE → 0

?

YES

A

SD00061

NO

Philips Semiconductors Product specification

SCN2652/SCN68652Multi-protocol communications controller (MPCC)

MPCC, the processor should load TDSR
the message. TSOM should be cleared at the same time TDSR

with the first character of

L

is

L

loaded (16-bit data bus) or immediately thereafter (8-bit data bus).
FLAGS are sent as long as TSOM = 1. For counting the number of
FLAGs, the processor should reassert TSOM in response to the
assertion of TxBE.All succeeding characters are loaded into TDSR
by the processor when TxBE = 1. Each

character is serialized in TxSR and transmitted on TxSO. Internal
zero insertion logic stuffs a “0” into the serial bit stream after five
successive “1s” are sent. This insures a data character will not
match a FLAG, ABORT, or GA reserved control character. As each
character is transmitted, the Frame Check Sequence (FCS) is
generated as specified by Error Control Mode (PCSAR
FCS should be the CRC–CCITT polynomial (X

16

+ X12 + X5 + 1)

8–10

). The

preset to 1s. If an underrun occurs (processor is not keeping up with
the transmitter), TxU and TERR (TDSR

) will be asserted with

15

ABORT or FLAG used as the TxSO line fill depending on the state
of IDLE (PCSAR

). The processor must set TSOM to reset the

11

underrun condition. To retransmit the message, the processor
should proceed with the normal start of message sequence.

A residual character of 1 to 7 bits may be transmitted at the end of
the information field. In response to TxBE, write the residual
character length into TxCL and load TxDB with the residual
character. Dynamic alteration of character length should be done in
exactly the same sequence. The character length will be changed
on the next transmit character boundary.

After the last data character has been loaded into TDSR
to TxSR (TxBE = 1), the processor should set TEOM (TDSR

and sent

L

). The

9

MPCC will finish transmitting the last character followed by the FCS
and the closing FLAG. The processor should clear TEOM and drop
TxE when the next TxBE is asserted. This corresponds to the start
of closing FLAG transmission. When TxE has been dropped. TxA
will be low 1 1/2 bit times after the last bit of the closing FLAG has
been transmitted. TxSO will be marked after the closing FLAG has
been transmitted.

If TxE and TEOM are high, the transmitter continues to send
FLAGs. The processor may initiate the next message by resetting
TEOM and setting TSOM, or by loading TDSR

with a data

L

character and then simply resetting TSOM (without setting TSOM).

TxBCP Operation

Transmitter operation for BCP mode is shown in Figure 9. TxA will
be asserted after TSOM = 1 and TxE is raised. At that time SYNC
characters are sent from PCSAR
as TSOM = 1. TxBE is asserted at the start of transmission of the
first SYNC character. For counting the number of SYNCs, the
processor should reassert TSOM in response to the assertion of
TxBE. When TSOM = 0 transmission is from TDSR
loaded with characters from the processor each time TxBE is
asserted. If this loading is delayed for more than one character time,
an underrun results: TxU and TERR are asserted and the

TxSO line fill depend on IDLE (PCSAR
TSOM and retransmit the message to recover. This is not
compatible with IBM’s BISYNC, so that the user must not underrun
when supporting that protocol.

or TDSRL (IDLE = 0 or 1) as long

L

, which must be

L

). The processor must set

11

CRC–16, if specified by PCSAR
character transmitted from TDSR

, is generated on each

8–10

when TSOM =0. The processor

L

must set TEOM = 1 after the last data character has been sent to
TxSR (TxBE = 1). The MPCC will finish transmitting the last data
character and the CRC–16 field before sending SYNC characters

L

which are transmitted as long as TEOM = 1. If SYNCs are not
desired after CRC–16 transmission, the processor should clear
TEOM and lower TxE when the TxBE corresponding to the start of
CRC–16 transmission is asserted. When TEOM = 0, the line is
marked and a new message may be initiated by setting TSOM and
raising TxE.

If VRC is specified, it is generated on each data character and the
data character length must not exceed 7 bits. For software LRC or
CRC, TEOM should be set only if SYNC’s are required at the end of
the message block.

SPECIAL CASE: The capability to transmit 16 spaces is provided
for line turnaround in half duplex mode or for a control recovery
situation. This is achieved by setting TSOM and TEOM, clearing
TEOM when TxBE = 1, and proceeding as required.

PROGRAMMING

Prior to initiating data transmission or reception, PCSAR and PCR
must be loaded with control information from the processor. The
contents of these registers (see Register Format section) will
configure the MPCC for the user’s specific data communication
environment. These registers should be loaded during power-on
initialization and after a reset operation. They can be changed at any
time that the respective transmitter or receiver is disabled.

The default value for all registers is zero. This corresponds to BOP,

primary station mode, 8-bit character length, FCS = CRC–CCITT
preset to 1s.

For BOP mode the character length register (PCR) may be set to
the desired values during system initialization. The address and
control fields will automatically be 8-bits. If a residual character is to
be transmitted, TxCL should be changed to the residual character
length prior to transmission of that character.

DATA BUS CONTROL

The processor must set up the MPCC register address (A2–A0),
chip enable (CE), byte select (BYTE), and read/write (R
before each data bus transfer operation.

During a read operation (R

/W = 0), the leading edge of DBEN will
initiate an MPCC read cycle. The addressed register will place its
contents on the data bus. If BYTE = 1, the 8-bit byte is placed on
DB15–08 or DB07–00 depending on the H/L status of the register
addressed. Unused bits in RDSR

are zero. If BYTE = 0, all 16 bits

L

(DB15–00) contain MPCC information. The trailing edge of DBEN
will reset RxDA and/or RxSA if RDSR

or RDSRH is addressed

L

respectively.
DBEN acts as the enable and strobe so that the MPCC will not

begin its internal read cycle until DBEN is asserted.
During a write operation (R

and/or DB

prior to the leading edge of DBEN. The stable data

07–00

/W = 1), data must be stable on DB

is strobed into the addressed register by DBEN. TxBE will be
cleared if the addressed register was TDSR

or TDSRL.

H

/W) inputs

15–08

1995 May 01

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