Philips SCN2661AC1A28, SCN2661BA1F28, SCN2661BC1A28, SCN2661BC1F28, SCN2661BC1N28 Datasheet

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Philips Semiconductors Product specification

SCN2661/SCN68661

Enhanced programmable communications interface (EPCI)

1994 Apr 27 853-1070 12793

DESCRIPTION

The Philips Semiconductors SCN2661 EPCI is a universal synchronous/asynchronous data communications controller chip that is an enhanced version of the SCN2651. It interfaces easily to all 8-bit and 16-bit microprocessors and may be used in a polled or interrupt driven system environment. The SCN2661 accepts programmed instructions from the microprocessor while supporting many serial data communications disciplines —synchronous and asynchronous — in the full- or half-duplex mode. Special support for BISYNC is provided.

The EPCI serializes parallel data characters received from the microprocessor for transmission. Simultaneously, it can receive serial data and convert it into parallel data characters for input to the microcomputer.

The SCN2661 contains a baud rate generator which can be programmed to either accept an external clock or to generate internal transmit or receive clocks. Sixteen different baud rates can be selected under program control when operating in the internal clock mode. Each version of the EPCI (A, B, C) has a different set of baud rates.

FEATURES

•Synchronous operation

– 5- to 8-bit characters plus parity – Single or double SYN operation – Internal or external character synchronization – Transparent or non-transparent mode – Transparent mode DLE stuffing (Tx) and detection (Rx) – Automatic SYN or DLE-SYN insertion SYN, DLE and DLESYN

stripping

– Odd, even, or no parity – Local or remote maintenance loopback mode – Baud rate: DC to 1Mbps (1X clock)

•Asynchronous operation

– 5- to 8-bit characters plus parity – 1, 1-1/2 or 2 stop bits transmitted – Odd, even, or no parity – Parity, overrun and framing error detection – Line break detection and generation – False start bit detection – Automatic serial echo mode (echoplex) – Local or remote maintenance loopback mode – Baud rate: DC to 1Mbps

(1X clock) DC to 62.5kbps (16X clock) DC to 15.625kbps (64X clock)

OTHER FEATURES

•Internal or external baud rate clock

•3 baud rate sets

•16 internal rates for each set

•Double-buffered transmitter and receiver

PIN CONFIGURATIONS

D1 D0

RxC/BKDET DTR

RTS DSR

RESET BRCLK TxD TxEMT

/DSCHG CTS

DCD TxRDYRxRDY

R/W

TxC

/XSYNC

GND

RxD

DIP

PLCC

INDEX

CORNER

TOP VIEW

NOTE:

Pin Functions the same as 28-pin DIP.

28 27 26 25 24 23 22 21 20 19 18 17 16 15

1 2 3 4 5 6 7 8

9 10 11 12 13 14

1812

4 1

SD00077

•Dynamic character length switching

•Full- or half-duplex operation

•TTL compatible inputs and outputs

•RxC and TxC pins are short-circuit protected

•Single +5V power supply

•No system clock required

APPLICATIONS

•Intelligent terminals

•Network processors

•Front-end processors

•Remote data concentrators

•Computer-to-computer links

•Serial peripherals

•BISYNC adaptors

Philips Semiconductors Product specification

SCN2661/SCN68661

Enhanced programmable communications interface (EPCI)

1994 Apr 27

ORDERING CODE

VCC = +5V +5%

PACKAGES

Commercial

0°C to +70°C

Industrial

-40°C to +85°C

DWG #

28-Pin Ceramic Dual In-Line Package (cerdip) 0.6” Wide

SCN2661BC1F28 SCN2661CC1F28

SCN2661BA1F28 SCN2661CA1F28

0589B

28-Pin Plastic Dual In-Line Package (DIP) 0.6” Wide

SCN2661AC1N28 SCN2661BC1N28

SCN2661CC1N28

Contact Factory SOT117-2

28-Pin Plastic Lead Chip Carrier (PLCC)

SCN2661AC1A28 SCN2661BC1A28 SCN2661CC1A28

Contact Factory SOT261-3

BLOCK DIAGRAM

DATA BUS

D0–D7

RESET

R/W

DATA BUS

BUFFER

OPERATION CONTROL

MODE REGISTER 1

BAUD RATE

GENERATOR

AND

CLOCK CONTROL

SNE/DLE CONTROL

SYN 1 REGISTER SYN 2 REGISTER

DLE REGISTER

TRANSMITTER

TRANSMIT DATA

TxD

MODE REGISTER 2

COMMAND REGISTER

STATUS REGISTER

BRCLK

TxC/SYNC

RxC/BKDET

DSR

MODEM

CONTROL

DCD CTS RTS DTR

TxEMT/*

DSCHG

HOLDING REGISTER

TRANSMIT

SHIFT REGISTER

TxRDY*

RECEIVE DATA

RECEIVE

RECEIVER

RxD

RxRDY

HOLDING REGISTER

SHIFT REGISTER

NOTES:

* Open–drain output pin.

SD00078

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER RATING UNIT

Operating ambient temperature

Note 4 °C

STG

Storage temperature -65 to +150 °C All voltages with respect to ground

-0.5 to +6.0

NOTES:

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operation section of this specification is not implied.

2. For operating at elevated temperatures, the device must be derated based on +150°C maximum function temperature.

3. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effect of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.

4. Over recommended free-air operating temperature range and supply voltage range unless otherwise specified. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

Philips Semiconductors Product specification

SCN2661/SCN68661

Enhanced programmable communications interface (EPCI)

1994 Apr 27

DC ELECTRICAL CHARACTERISTICS

1, 2, 3

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

Min Typ Max

UNIT

Input voltage

Low High

2.0

0.8

V V

Output voltage

Low High

IOL = 2.2mA

= -400µA 2.4

0.4

V V

Input leakage current VIN = 0 to 5.5V 10 µA

3-State output leakage current

Data bus high Data bus low

VO = 4.0V

VO = 0.45V

µA µA

Power supply current 150 mA

NOTES:

1. Over recommended free-air operating temperature range and supply voltage range unless otherwise specified. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

2. All voltages measurements are referenced to ground. All time measurements are at the 50% level for inputs (except t

BRH

and t

BRL

) and at

0.8V and 2.0V for outputs. Input levels swing between 0.4V and 2.4V , with a transition time of ≤ 20ns maximum.

3. Typical values are at +25°C, typical supply voltages and typical processing parameters.

4. INTR

, TxRDY, RxRDY and TxEMT/DSCHG outputs are open-drain.

CAPACITANCE TA = 25°C, V

= 0V

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

Min Typ Max

UNIT

Capacitance

OUT

I/O

Input Output Input/Output

= 1MHz

Unmeasured pins tied to ground

20 20 20

pF pF pF

Philips Semiconductors Product specification

SCN2661/SCN68661

Enhanced programmable communications interface (EPCI)

1994 Apr 27

AC ELECTRICAL CHARACTERISTICS

1, 2, 3

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

Min Typ Max

UNIT

Pulse width

RES

Reset Chip enable

1000

250

ns ns

Setup and hold time

RXS

RXH

Address setup Address hold R

/W control setup

/W control hold Data setup for write Data hold for write RX data setup RX data hold

10 10 10 10

150

10 300 350

ns ns ns ns ns ns ns ns

CED

Data delay time for read Data bus floating time for read CE to CE delay

= 150pF

600

200 100

ns ns ns

Input clock frequency

BRG

R/T

Baud rate generator (2661A, B) Baud rate generator (2661C) TxC

or RxC

1.0

1.0 dc

4.9152

5.0688

4.9202

5.0738

1.0

MHz MHz MHz

Clock width

BRH

BRL

R/TH

R/TL

Baud rate High (2661A, B) Baud rate High (2661C) Baud rate Low (2661A, B) Baud rate Low (2661C) TxC

or RxC High

TxC

or RxC Low

75 70 75 70

480 480

ns ns ns ns ns ns

TXD

TCS

TxD delay from falling edge of TxC Skew between TxD changing and falling edge of TxC

output

= 150pF

650 ns

NOTES:

2. All voltages measurements are referenced to ground. All time measurements are at the 50% level for inputs (except t

BRH

and t

BRL

) and at

0.8V and 2.0V for outputs. Input levels swing between 0.4V and 2.4V , with a transition time of ≤ 20ns maximum.

3. Typical values are at +25°C, typical supply voltages and typical processing parameters.

4. Parameter applies when internal transmitter clock is used.

5. Under test conditions of 5.0688MHz f

BRG

(68661) and 4.9152MHz f

BRG

(68661A, B), t

BRH

and t

BRL

measured at VIH and VIL, respectively.

6. In asynchronous local loopback mode, using 1X clock, the following parameters apply: f

R/T

= 0.83MHz max and t

R/TL

= 700ns min.

7. See AC load conditions.

BLOCK DIAGRAM

The EPCI consists of six major sections. These are the transmitter, receiver, timing, operation control, modern control and SYN/DLE control. These sections communicate with each other via an internal data bus and an internal control bus. The internal data bus interfaces to the microprocessor data bus via a data bus buffer.

Operation Control

This functional block stores configuration and operation commands from the CPU and generates appropriate signals to various internal sections to control the overall device operation. It contains read and write circuits to permit communications with the microprocessor via the data bus and contains mode registers 1 and 2, the command register, and the status register. Details of register addressing and protocol are presented in the EPCI programming section of this data sheet.

Timing

The EPCI contains a Baud Rate Generator (BRG) which is programmable to accept external transmit or receive clocks or to divide an external clock to perform data communications. The unit can generate 16 commonly used baud rates, any one of which can be selected for full-duplex operation. See Table 1.

Receiver

The receiver accepts serial data on the RxD pin, converts this serial input to parallel format, checks for bits or characters that are unique to the communication technique and sends an “assembled” character to the CPU.

Transmitter

The transmitter accepts parallel data from the CPU, converts it to a serial bit stream, inserts the appropriate characters or bits (based on

Philips Semiconductors Product specification

SCN2661/SCN68661

Enhanced programmable communications interface (EPCI)

1994 Apr 27

the communication technique) and outputs a composite serial stream of data on the TxD output pin.

Modem Control

The modern control section provides interfacing for three input signals and three output signals used for “handshaking” and status indication between the CPU and a modem.

SYN/DLE Control

This section contains control circuitry and three 8-bit registers storing the SYN1, SYN2, and DLE characters provided by the CPU. These registers are used in the synchronous mode of operation to provide the characters required for synchronization, idle fill and data transparency.

Table 1. Baud Rate Generator Characteristics

68661A (BRCLK = 4.9152MHz)

MR23–20

BAUD RATE

ACTUAL FREQUENCY

16X CLOCK

PERCENT

ERROR

DIVISOR

0000 50 0.8kHz — 6144 0001 75 1.2 — 4096 0010 110 1.7598 –0.01 2793 0011 134.5 2.152 — 2284 0100 150 2.4 — 2048 0101 200 3.2 — 1536 0110 300 4.8 — 1024 0111 600 9.6 — 512 1000 1050 16.8329 0.196 292 1001 1200 19.2 — 256 1010 1800 28.7438 –0.19 171 1011 2000 31.9168 –0.26 154 1100 2400 38.4 — 128 1101 4800 76.8 — 64 1110 9600 153.6 — 32

1111 19200 307.2 — 16

68661B (BRCLK = 4.9152MHz)

MR23–20

BAUD RATE

ACTUAL FREQUENCY

16X CLOCK

PERCENT

ERROR

DIVISOR

0000 45.5 0.7279kHz 0.005 6752 0001 50 0.8 — 6144 0010 75 1.2 — 4096 0011 110 1.7598 –0.01 2793 0100 134.5 2.152 — 2284 0101 150 2.4 — 2048 0110 300 4.8 — 1024 0111 600 9.6 — 512 1000 1200 19.2 — 256 1001 1800 28.7438 –0.19 171 1010 2000 31.9168 –0.26 154 1011 2400 38.4 — 128 1100 4800 76.8 — 64 1101 9600 153.6 — 32 1110 19200 307.2 — 16

1111 38400 614.4 — 8

Philips Semiconductors Product specification

SCN2661/SCN68661

Enhanced programmable communications interface (EPCI)

1994 Apr 27

68661C (BRCLK = 5.0688MHz)

MR23–20

BAUD RATE ACTUAL FREQUENCY 16X CLOCK PERCENT ERROR DIVISOR

0000 50 0.8kHz — 6336 0001 75 1.2 — 4224 0010 110 1.76 — 2880 0011 134.5 2.1523 0.016 2355 0100 150 2.4 — 2112 0101 300 4.8 — 1056 0110 600 9.6 — 528 0111 1200 19.2 — 264 1000 1800 28.8 — 176 1001 2000 32.081 0.253 158 1010 2400 38.4 — 132 1011 3600 57.6 — 88 1100 4800 76.8 — 66 1101 7200 115.2 — 44 1110 9600 153.6 — 33

1111 19200 316.8 3.125 16

NOTE: 16X clock is used in asynchronous mode. In synchronous mode, clock multiplier is 1X and BRG can be used only for TxC.

OPERATION

The functional operation of the 68661 is programmed by a set of control words supplied by the CPU. These control words specify items such as synchronous or asynchronous mode, baud rate, number of bits per character, etc. The programming procedure is described in the EPCI programming section of the data sheet.

After programming, the EPCI is ready to perform the desired communications functions. The receiver performs serial to parallel conversion of data received from a modem or equivalent device. The transmitter converts parallel data received from the CPU to a serial bit stream. These actions are accomplished within the framework specified by the control words.

Receiver

The 68661 is conditioned to receiver data when the DCD input is Low and the RxEN bit in the commands register is true. In the asynchronous mode, the receiver looks for High-to-Low (mark to space) transition of the start bit on the RxD input line. If a transition is detected, the state of the RxD line is sampled again after a delay of one-half of a bit-time. If RxD is now high, the search for a valid start bit is begun again. If RxD is still Low, a valid start bit is assumed and the receiver continues to sample the input line at one bit time intervals until the proper number of data bits, the parity bit, and one stop bit have been assembled. The data are then transferred to the receive data holding register, the RxRDY bit in the status register is set, and the RxRDY

output is asserted. If the character length is less than 8 bits, the High order unused bits in the holding register are set to zero. The parity error, framing error, and overrun error status bits are strobed into the status register on the positive going edge of RxC

corresponding to the received character boundary. If the stop bit is present, the receiver will immediately begin its search for the next start bit. If the stop bit is absent (framing error), the receiver will interpret a space as a start bit if it persists into the next bit timer interval. If a break condition is detected (RxD is Low for the entire character as well as the stop bit), only one character consisting of all zeros (with the FE status bit SR5 set) will be transferred to the holding register. The RxD input must return to a High condition before a search for the next start bit begins.

Pin 25 can be programmed to be a break detect output by appropriate setting of MR27-MR24. If so, a detected break will cause that pin to go High. When RxD returns to mark for one RxC time, pin 25 will go low. Refer to the Break Detection Timing Diagram.

When the EPCI is initialized into the synchronous mode, the receiver first enters the hunt mode on a 0 to 1 transition of RxEN (CR2). In this mode, as data are shifted into the receiver shift register a bit at a time, the contents of the register are compared to the contents of the SYN1 register. If the two are not equal, the next bit is shifted in and the comparison is repeated. When the two registers match, the hunt mode is terminated and character assembly mode begins. If single SYN operation is programmed, the SYN DETECT status bit is set. If double SYN operation is programmed, the first character assembled after SYN1 must be SYN2 in order for the SYN DETECT bit to be set. Otherwise, the EPCI returns to the hunt mode. (Note that the sequence SYN1-SYN1-SYN2 will not achieve synchronization.) When synchronization has been achieved, the EPCI continues to assemble characters and transfer then to the holding register, setting the RxRDY status bit and asserting the RxRDY

output each time a character is transferred. The PE and OE status bits are set as appropriate. Further receipt of the appropriate SYN sequence sets the SYN DETECT status bit. If the SYN stripping mode is commanded, SYN characters are not transferred to the holding register. Note that the SYN characters used to establish initial synchronization are not transferred to the holding register in any case.

External jam synchronization can be achieved via pin 9 by appropriate setting of MR27-MR24. When pin 9 is an XSYNC input, the internal SYN1, SYN1–SYN2, and DLE–SYN1 detection is disabled. Each positive going signal on XSYNC will cause the receiver to establish synchronization on the rising edge of the next RxC pulse. Character assembly will start with the RxD input at this edge. XSYNC may be lowered on the next rising edge of RxD. This external synchronization will cause the SYN DETECT status bit to be set until the status register is read. Refer to XSYNC timing diagram.

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