Philips SCC2692AC1N28, SCC2692AC1N40, SCC2692AE1A44, SCC2692AE1B44, SCC2692AE1N28 Datasheet

INTEGRATED CIRCUITS

SCC2692

Dual asynchronous receiver/transmitter
(DUART)

Product specification
Supersedes data of 1998 Feb 19
IC19 Data Handbook

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1998 Sep 04

Philips Semiconductors Product specification

SCC2692Dual asynchronous receiver/transmitter (DUART)

DESCRIPTION

The Philips Semiconductors SCC2692 Dual Universal
Asynchronous Receiver/Transmitter (DUART) which is compatible
with the SCN2681. It is a single-chip CMOS-LSI communications
device that provides two full-duplex asynchronous
receiver/transmitter channels in a single package. It interfaces
directly with microprocessors and may be used in a polled or
interrupt driven system.

The operating mode and data format of each channel can be
programmed independently. Additionally, each receiver and
transmitter can select its operating speed as one of eighteen fixed
baud rates, a 16X clock derived from a programmable counter/timer,
or an external 1X or 16X clock. The baud rate generator and
counter/timer can operate directly from a crystal or from external
clock inputs. The ability to independently program the operating
speed of the receiver and transmitter make the DUART particularly
attractive for dual-speed channel applications such as clustered
terminal systems.

Each receiver is quadruply buffered to minimize the potential of
receiver over-run or to reduce interrupt overhead in interrupt driven
systems. In addition, a flow control capability is provided to disable a
remote DUART transmitter when the receiver buffer is full.

Also provided on the SCC2692 are a multipurpose 7-bit input port
and a multipurpose 8-bit output port. These can be used as general
purpose I/O ports or can be assigned specific functions (such as
clock inputs or status/interrupt outputs) under program control.

FEA TURES

•Dual full-duplex asynchronous receiver/transmitters

•Quadruple buffered receiver data register

•Programmable data format

– 5 to 8 data bits plus parity
– Odd, even, no parity or force parity
– 1, 1.5 or 2 stop bits programmable in 1/16-bit increments

•16-bit programmable Counter/Timer

•Programmable baud rate for each receiver and transmitter

selectable from:

– 22 fixed rates: 50 to 115.2k baud
– Non-standard rates to 115.2Kb

– Non-standard user-defined rate derived from programmable

counter/timer

– External 1X or 16X clock

•Parity, framing, and overrun error detection

•False start bit detection

•Line break detection and generation

•Programmable channel mode

– Normal (full-duplex)
– Automatic echo
– Local loopback
– Remote loopback
– Multidrop mode (also called ‘wake-up’ or ‘9-bit’)

•Multi-function 7-bit input port

– Can serve as clock or control inputs
– Change of state detection on four inputs
– Inputs have typically >100k pull-up resistors

•Multi-function 8-bit output port

– Individual bit set/reset capability
– Outputs can be programmed to be status/interrupt signals

•Versatile interrupt system

– Single interrupt output with eight maskable interrupting

conditions

– Output port can be configured to provide a total of up to six

separate wire-ORable interrupt outputs

•Maximum data transfer rates: 1X – 1MB/sec, 16X – 125kB/sec

•Automatic wake-up mode for multidrop applications

•Start-end break interrupt/status

•Detects break which originates in the middle of a character

•On-chip crystal oscillator

•Power down mode

•Receiver timeout mode

•Commercial and industrial temperature range versions

•TTL compatible

•Single +5V power supply

ORDERING INFORMATION

COMMERCIAL INDUSTRIAL

DESCRIPTION

40-Pin Plastic Dual In-Line Package (DIP)
28-Pin Plastic Dual In-Line Package (DIP)
44-Pin Plastic Leaded Chip Carrier (PLCC) Package SCC2692AC1A44 SCC2692AE1A44 SOT187-2
44–Pin Plastic Quad Flat Pack (PQFP) SCC2692AC1B44 SCC2692AE1B44 SOT307–2

NOTE:

1. For availability, please contact factory.

1998 Sep 04 853–0895 19971

1
1

VCC = +5V +10%,

TA = 0 to +70°C

SCC2692AC1N40 SCC2692AE1N40 SOT129-1
SCC2692AC1N28 SCC2692AE1N28 SOT117-1

2

VCC = +5V +10%,
TA = -40 to +85°C

DWG #

Philips Semiconductors Product specification

P

SCC2692Dual asynchronous receiver/transmitter (DUART)

A0

IP3

A1

IP1

A2

A3

IP0

WRN

RDN
RxDB
TxDB

OP1

OP3
OP5
OP7

D1
D3
D5

D7

GND

28
27
26
25
24

23
22
21
20
19
18

17

16
15

INDEX

CORNER

V

CC

IP2
CEN

RESET
X2

X1/CLK
RxDA
TxDA
OP0
D0
D2

D4

D6
INTRNGND

6

7

17

18

PIN/FUNCTION PIN/FUNCTION

1NC 23NC
2 A0 24 INTRN
3 IP3 25 D6
4A1 26D4
5 IP1 27 D2
6A2 28D0
7 A3 29 OP6
8 IP0 30 OP4
9 WRN 31 OP2
10 RDN 32 OP0
11 RXDB 33 TXDA
12 NC 34 NC
13 TXDB 35 RXDA
14 OP1 36 X1/CLK
15 OP3 37 X2
16 OP5 38 RESET
17 OP7 39 CEN
18 D1 40 IP2
19 D3 41 IP6
20 D5 42 IP5
21 D7 43 IP4
22 GND 44 V

1

PLCC

TOP VIEW

40

28

CC

39

29

44

1

11

12

TOP VIEW

PIN/FUNCTION PIN/FUNCTION

1 A3 23 N/C
2 IP0 24 OP6
3 WRN 25 OP4
4 RDN 26 OP2
5 RxDB 27 OP0
6 TxDB 28 TxDA
7 OP1 29 RxDA
8 OP3 30 X1/CLK
9 OP5 31 X2
10 OP7 32 RESET
11 N/C 33 CEN
12 D1 34 IP2
13 D3 35 IP6
14 D5 36 IP5
15 D7 37 IP4
16 GND 38 V
17 GND 39 V
18 INTRN 40 A0
19 D6 41 IP3
20 D4 42 A1
21 D2 43 IP1
22 D0 44 A2

PQFP

34

22

SD00131

33

23

CC
CC

1
2
3

4
5

6
7

8
9

10

DIP

11
12

13
14
15
16
17
18

19

40
39
38

37
36

35
34

33
32
31
30
29

28
27
26
25
24
23

22
2120

V

CC

IP4
IP5

IP6
IP2

CEN
RESET

X2
X1/CLK
RxDA
TxDA
OP0

OP2
OP4
OP6
D0
D2
D4

D6
INTRN

WRN

RDN

RxDB

TxDB

OP1

A0

1

A1

2

A2

3

A3

4
5

6
7

DIP

8
9

D1

10

D3

11

D5

12

D7

13
14

Figure 1. Pin Configurations

ABSOLUTE MAXIMUM RATINGS

SYMBOL

T

V

T

A

STG

CC

V

S

Operating ambient temperature range
Storage temperature range -65 to +150 °C
Voltage from VCC to GND
Voltage from any pin to GND

1

PARAMETER RATING UNIT

2

3

3

Note 4 °C

-0.5 to +7.0 V

-0.5 to VCC +0.5 V
Package power dissipation DIP28 1.22 W
Package power dissipation DIP40 2.97 W

D

Package power dissipation PLCC44 2.66 W
Package power dissipation PQFP44 2.08 W
Derating factor above 25°C DIP28 19 mW/°C
Derating factor above 25°C DIP40 24 mW/°C
Derating factor above 25°C PLCC44 21 mW/°C
Derating factor above 25°C PQFP44 17 mW/°C

NOTES:

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not
implied.

2. For operating at elevated temperatures, the device must be derated.

3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.

4. Parameters are valid over specified temperature range.

1998 Sep 04

3

Philips Semiconductors Product specification

SCC2692Dual asynchronous receiver/transmitter (DUART)

BLOCK DIAGRAM

D0–D7

RDN

WRN

CEN

A0–A3

RESET

INTRN

8

BUS BUFFER

OPERATION CONTROL

ADDRESS

4

DECODE

R/W CONTROL

INTERRUPT CONTROL

IMR
ISR

TIMING

BAUD RATE

GENERATOR

CLOCK

SELECTORS

CONTROL

TIMING

INTERNAL DATABUS

CHANNEL A

TRANSMIT

HOLDING REG

TRANSMIT

SHIFT REGISTER

RECEIVE

HOLDING REG (3)

RECEIVE

SHIFT REGISTER

MRA1, 2

CRA
SRA

CHANNEL B
(AS ABOVE)

INPUT PORT

CHANGE OF

STATE

DETECTORS (4)

IPCR

ACR

TxDA

RxDA

TxDB

RxDB

7

IP0-IP6

X1/CLK

X2

COUNTER/

TIMER

XTAL OSC

CSRA

CSRB

ACR

U

CTLR
CTLR

Figure 2. Block Diagram

OUTPUT PORT

FUNCTION

SELECT LOGIC

OPCR

OPR

8

OP0-OP7

V

CC

GND

SD00132

1998 Sep 04

4

Philips Semiconductors Product specification

SYMBOL

TYPE

NAME AND FUNCTION

SCC2692Dual asynchronous receiver/transmitter (DUART)

PIN DESCRIPTION

APPLICABLE
40,44 28

D0-D7 X X I/O Data Bus: Bidirectional 3-State data bus used to transfer commands, data and status between the

CEN X X I Chip Enable: Active-Low input signal. When Low, data transfers between the CPU and the DUART

WRN X X I Write Strobe: When Low and CEN is also Low, the contents of the data bus are loaded into the
RDN X X I Read Strobe: When Low and CEN is also Low, causes the contents of the addressed register to be

A0-A3 X X I Address Inputs: Select the DUART internal registers and ports for read/write operations.

RESET X X I Reset: A High level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OP0-OP7 in

INTRN X X O Interrupt Request: Active-Low, open-drain, output which signals the CPU that one or more of the

X1/CLK X X I Crystal 1: Crystal connection or an external clock input. A crystal of a clock the appropriate frequency

X2 X X I Crystal 2: Crystal connection. See Figure 7. If a crystal is not used it is best to keep this pin not
RxDA X X I Channel A Receiver Serial Data Input: The least significant bit is received first. “Mark” is High,
RxDB X X I Channel B Receiver Serial Data Input: The least significant bit is received first. “Mark” is High,
TxDA X X O Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is

TxDB X X O Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This output

OP0 X X O Output 0: General purpose output or Channel A request to send (RTSAN, active-Low). Can be
OP1 X X O Output 1: General purpose output or Channel B request to send (RTSBN, active-Low). Can be
OP2 X O Output 2: General purpose output, or Channel A transmitter 1X or 16X clock output, or Channel A
OP3 X O Output 3: General purpose output or open-drain, active-Low counter/timer output or Channel B
OP4 X O Output 4: General purpose output or Channel A open-drain, active-Low, RxRDYAN/FFULLAN output.

OP5 X O Output 5: General purpose output or Channel B open-drain, active-Low, RxRDYBN/FFULLBN output.
OP6 X O Output 6: General purpose output or Channel A open-drain, active-Low, TxRDYAN output.
OP7 X O Output 7: General purpose output, or Channel B open-drain, active-Low, TxRDYBN output.

IP0 X I Input 0: General purpose input or Channel A clear to send active-Low input (CTSAN). Pin has an

IP1 X I Input 1: General purpose input or Channel B clear to send active-Low input (CTSBN). Pin has an

IP2 X X I Input 2: General purpose input or counter/timer external clock input. Pin has an internal VCC pull-up

IP3 X I Input 3: General purpose input or Channel A transmitter external clock input (TxCA). When the

IP4 X I Input 4: General purpose input or Channel A receiver external clock input (RxCA). When the external

IP5 X I Input 5: General purpose input or Channel B transmitter external clock input (TxCB). When the

IP6 X I Input 6: General purpose input or Channel B receiver external clock input (RxCB). When the external

V

CC

X X I Power Supply: +5V supply input.

GND X X I Ground

DUART and the CPU. D0 is the least significant bit.
are enabled on D0-D7 as controlled by the WRN, RDN and A0-A3 inputs. When High, places the

D0-D7 lines in the 3-State condition.

addressed register. The transfer occurs on the rising edge of the signal.
presented on the data bus. The read cycle begins on the falling edge of RDN.

the High state, stops the counter/timer, and puts Channels A and B in the inactive state, with the TxDA
and TxDB outputs in the mark (High) state. Resets Test modes, MR pointer set to MR1.

eight maskable interrupting conditions are true.
(nominally 3.6864 MHz) must be supplied at all times. For crystal connections see Figure 7, Clock Timing.
connected although it is permissible to ground it.
“space” is Low.
“space” is Low.
held in the “mark” condition when the transmitter is disabled, idle or when operating in local loopback

mode. “Mark” is High, “space” is Low.

is held in the ‘mark’ condition when the transmitter is disabled, idle, or when operating in local
loopback mode. ‘Mark’ is High, ‘space’ is Low.

deactivated automatically on receive or transmit.
deactivated automatically on receive or transmit.
receiver 1X clock output.
transmitter 1X clock output, or Channel B receiver 1X clock output.

internal V

internal V

pull-up device supplying 1 to 4 A of current.

CC

pull-up device supplying 1 to 4 A of current.

CC

device supplying 1 to 4 A of current.

external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the
clock. Pin has an internal V

pull-up device supplying 1 to 4 A of current.

CC

clock is used by the receiver, the received data is sampled on the rising edge of the clock. Pin has an
internal V

pull-up device supplying 1 to 4 A of current.

CC

external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the
clock. Pin has an internal V

pull-up device supplying 1 to 4 A of current.

CC

clock is used by the receiver, the received data is sampled on the rising edge of the clock. Pin has an
internal V

pull-up device supplying 1 to 4 A of current.

CC

1998 Sep 04

5

Philips Semiconductors Product specification

PARAMETER

TEST CONDITIONS

UNIT

SYMBOL

PARAMETER

UNIT

SCC2692Dual asynchronous receiver/transmitter (DUART)

DC ELECTRICAL CHARACTERISTICS

SYM­BOL

V

IL

V

IH

V

IH

V

IH

V

OL

V

OH

I

IX1PD

I

ILX1

I

IHX1

I

OHX2

I

OHX2S

I

OLX2

I

OLX2S

Input low voltage 0.8 V
Input high voltage (except X1/CLK)
Input high voltage (except X1/CLK)
Input high voltage (X1/CLK) 0.8 V

Output low voltage
Output high voltage (except OD outputs)

X1/CLK input current - power down
X1/CLK input low current - operating VIN = 0 -75 0 µA

X1/CLK input high current - operating VIN = V
X2 output high current - operating

X2 output high short circuit current - operating V
X2 output low current - operating V
X2 output low short circuit current - operating and power down V

1, 2, 3

6
7

LIMITS

Min Typ Max

2.0 V

2.5 V

CC

I

= 2.4mA

4

OL

V

I

= -400µA

OH

V

= 0 to V

IN

V

= V

OUT

OUT

= 0, X1 = V

OUT

= VCC, X1 = V

OUT

CC

CC

, X1 = 0

CC

= 0, X1 = 0 -10 -1 mA

CC

CC

-0.5 V

CC

-10 +10 µA

0 75 µA
0 +75 µA

-75 0 µA
1 10 mA

0.4 V

V

Input leakage current:

I

I

I

OZH

I

OZL

I

ODL

I

ODH

I

CC

All except input port pins VIN = 0 to V
Input port pins VIN = 0 to V

Output off current high, 3-state data bus VIN = V

CC
CC

CC

-10 +10 µA

-20 +10 µA

10 µA

Output off current low , 3-state data bus VIN = 0V -10 µA
Open-drain output low current in off-state VIN = 0 -10 µA

Open-drain output high current in off-state VIN = V
Power supply current

5

CC

10 µA

Operating mode CMOS input levels 10 mA
Power down mode

8

CMOS input levels

10

2

A

NOTES:

1. Parameters are valid over specified temperature range.

2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 2.4V with a transition time of 5ns
maximum. For X1/CLK this swing is between 0.4V and 4.4V . All time measurements are referenced at input voltages of 0.8V and 2.0V and
output voltages of 0.8V and 2.0V , as appropriate.

3. Typical values are at +25°C, typical supply voltages, and typical processing parameters.

4. Test conditions for outputs: C

5. All outputs are disconnected. Inputs are switching between CMOS levels of V

6. T

> 0°C

A

7. T

< 0°C

A

8. See UART application note for 5µA.

= 150pF, except interrupt outputs. T est conditions for interrupt outputs: CL = 50pF, R

L

-0.2V and VSS + 0.2V.

CC

= 2.7KΩ to VCC.

L

AC CHARACTERISTICS

Reset Timing (See Figure 3)

t

RES

Bus Timing

t

AS

t

AH

t

CS

t

CH

t

RW

t

DD

t

DA

t

DF

t

DI

t

DS

t

DH

t

RWD

1998 Sep 04

1, 2, 4

LIMITS

Min Typ

3

Max

RESET pulse width 200 ns

5

(See Figure 4)

A0-A3 setup time to RDN, WRN Low 10 ns
A0-A3 hold time from RDN, WRN Low 100 ns
CEN setup time to RDN, WRN Low 0 ns
CEN hold time from RDN, WRN High 0 ns
WRN, RDN pulse width 225 ns
Data valid after RDN Low 175 ns
RDN Low to data bus active

7

15 ns
Data bus floating after RDN High 125 ns
RDN High to data bus invalid

7

20 ns
Data setup time before WRN High 100 ns
Data hold time after WRN High 20 ns
High time between reads and/or writes

5, 6

200 ns

6

Philips Semiconductors Product specification

SYMBOL

PARAMETER

UNIT

9

8

8

SCC2692Dual asynchronous receiver/transmitter (DUART)

AC CHARACTERISTICS (Continued)

1, 2, 4

LIMITS

Min Typ

3

Max

Port Timing5 (See Figure 5)

t

PS

t

PH

t

PD

Port input setup time before RDN Low 0 ns
Port input hold time after RDN High 0 ns
OPn output valid from WRN High 400 ns

Interrupt Timing (See Figure 6)

INTRN (or OP3-OP7 when used as interrupts) negated from:

Read RHR (RxRDY/FFULL interrupt) 300 ns
Write THR (TxRDY interrupt) 300 ns

t

IR

Reset command (break change interrupt) 300 ns
Stop C/T command (counter interrupt) 300 ns
Read IPCR (input port change interrupt) 300 ns
Write IMR (clear of interrupt mask bit) 300 ns

Clock Timing (See Figure 7)

t

CLK

f

CLK

t

CTC

f

CTC

t

RX

f

RX

10

X1/CLK frequency 0 3.6864 4 MHz
CTCLK (IP2) High or Low time 100 ns

X1/CLK High or Low time

8

CTCLK (IP2) frequency 0 4 MHz
RxC High or Low time 220 ns
RxC frequency (16X) 0 2 MHz

100 ns

(1X) 0 1 MHz

t

TX

f

TX

TxC High or Low time 220 ns
TxC frequency (16X) 0 1 MHz

(1X) 0 1 MHz

Transmitter T iming (See Figure 8)

t

TXD

t

TCS

TxD output delay from TxC external clock input on IP pin 350 ns
Output delay from TxC low at OP pin to TxD data output 0 150 ns

Receiver Timing (See Figure 9)

t

RXS

t

RXH

RxD data setup time before RxC high at external clock input on IP pin 240 ns
RxD data hold time after RxC high at external clock input on IP pin 200 ns

NOTES:

1. Parameters are valid over specified temperature range.

2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 2.4V with a transition time of 5ns
maximum. For X1/CLK this swing is between 0.4V and 4.4V . All time measurements are referenced at input voltages of 0.8V and 2.0V and
output voltages of 0.8V and 2.0V , as appropriate.

3. Typical values are at +25°C, typical supply voltages, and typical processing parameters.

4. Test conditions for outputs: C

5. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the ‘strobing’ input. CEN

= 150pF, except interrupt outputs. T est conditions for interrupt outputs: CL = 50pF, R

L

= 2.7KΩ to VCC.

L

and RDN (also CEN and WRN) are ORed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated
first terminates the cycle.

6. If CEN is used as the ‘strobing’ input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must
be negated for t

7. Guaranteed by characterization of sample units.

to guarantee that any status register changes are valid.

RWD

8. Minimum frequencies are not tested but are guaranteed by design.

9. 325ns maximum for T

10.Operation to 0MHz is assured by design. Minimum test frequency is 2.0MHz. Crystal frequencies 2 to 4 MHz.

> 70°C.

A

1998 Sep 04

7

Philips Semiconductors Product specification

SCC2692Dual asynchronous receiver/transmitter (DUART)

BLOCK DIAGRAM

The SCC2692 DUART consists of the following eight major sections:
data bus buffer, operation control, interrupt control, timing,
communications Channels A and B, input port and output port. Refer
to the Block Diagram.

Data Bus Buffer

The data bus buffer provides the interface between the external and
internal data buses. It is controlled by the operation control block to
allow read and write operations to take place between the controlling
CPU and the DUART.

Operation Control

The operation control logic receives operation commands from the
CPU and generates appropriate signals to internal sections to
control device operation. It contains address decoding and read and
write circuits to permit communications with the microprocessor via
the data bus buffer.

Interrupt Control

A single active-Low interrupt output (INTRN) is provided which is
activated upon the occurrence of any of eight internal events.
Associated with the interrupt system are the Interrupt Mask Register
(IMR) and the Interrupt Status Register (ISR). The IMR can be
programmed to select only certain conditions to cause INTRN to be
asserted. The ISR can be read by the CPU to determine all currently
active interrupting conditions.

Outputs OP3-OP7 can be programmed to provide discrete interrupt
outputs for the transmitter, receivers, and counter/timer.

TIMING CIRCUITS
Crystal Clock

The timing block consists of a crystal oscillator, a baud rate
generator, a programmable 16-bit counter/timer, and four clock
selectors. The crystal oscillator operates directly from a crystal
connected across the X1/CLK and X2 inputs. If an external clock of
the appropriate frequency is available, it may be connected to
X1/CLK. The clock serves as the basic timing reference for the Baud
Rate Generator (BRG), the counter/timer, and other internal circuits.
A clock signal within the limits specified in the specifications section
of this data sheet must always be supplied to the DUART.

If an external clock is used instead of a crystal, X1 should be driven
using a configuration similar to the one in Figure 7.

BRG

The baud rate generator operates from the oscillator or external
clock input and is capable of generating 23 commonly used data
communications baud rates ranging from 50 to 130.4K baud. A

3.6864MHz crystal or external clock must be used to get the

standard baud rate. The clock outputs from the BRG are at 16X the
actual baud rate. The counter/timer can be used as a timer to
produce a 16X clock for any other baud rate by counting down the
crystal clock or an external clock. The four clock selectors allow the
independent selection, for each receiver and transmitter, of any of
these baud rates or external timing signal.

Counter/Timer (C/T)

The counter timer is a 16 bit programmable divider that operates
one of three modes: Counter, T imer or Time Out mode. In all three
modes it uses the 16-bit value loaded to the CTUR and CTLR
registers. (Counter timer upper and lower preset registers).

•In the timer mode it generates a square wave.

•In the counter mode it generates a time delay.

•In the time out mode it monitors the receiver data flow and signals

data flow has paused. In the time out mode the receiver controls
the starting/stopping of the C/T.

The counter operates as a down counter and sets its output bit in
the ISR (Interrupt Status Register) each time it passes through 0.
The output of the counter/timer may be seen on one of the OP pins
or as an Rx or Tx clock.

The Timer/Counter is controlled with six (6) “commands”; Start C/T,
Stop C/T, write C/T, preset registers, read C/T value, set or reset
time out mode.

Please see the detail of the commands under the Counter/Timer
register descriptions.

Communications Channels A and B

Each communications channel of the SCC2692 comprises a
full-duplex asynchronous receiver/transmitter (UART). The operating
frequency for each receiver and transmitter can be selected
independently from the baud rate generator, the counter/timer , or
from an external input.

The transmitter accepts parallel data from the CPU, converts it to a
serial bit stream, inserts the appropriate start, stop, and optional
parity bits and outputs a composite serial stream of data on the TxD
output pin. The receiver accepts serial data on the RxD pin,
converts this serial input to parallel format, checks for start bit, stop
bit, parity bit (if any), or break condition and sends an assembled
character to the CPU.

Input Port

The inputs to this unlatched 7-bit port can be read by the CPU by
performing a read operation at address H’D’. A High input results in
a logic 1 while a Low input results in a logic 0. D7 will always read
as a logic 1. The pins of this port can also serve as auxiliary inputs
to certain portions of the DUART logic.

Four change-of-state detectors are provided which are associated
with inputs IP3, IP2, IP1 and IP0. A High-to-Low or Low-to-High
transition of these inputs, lasting longer than 25 - 50µs, will set the
corresponding bit in the input port change register. The bits are
cleared when the register is read by the CPU. Any change-of-state
can also be programmed to generate an interrupt to the CPU.

The input port pulse detection circuitry uses a 38.4KHz sampling
clock derived from one of the baud rate generator taps. This results
in a sampling period of slightly more than 25µs (this assumes that
the clock input is 3.6864MHz). The detection circuitry, in order to
guarantee that a true change in level has occurred, requires two
successive samples at the new logic level be observed. As a
consequence, the minimum duration of the signal change is 25µs if
the transition occurs “coincident with the first sample pulse”. The
50µs time refers to the situation in which the change-of-state is “just
missed” and the first change-of-state is not detected until 25µs later.
All the IP pins have a small pull-up device that will source 1 to 4 A
of current from V

connections if they are not used.

V

CC

Output Port

The output port pins may be controlled by the OPR, OPCR, MR and
CR registers. Via appropriate programming they may be just another
parallel port to external circuits, or they may represent many internal

. These pins do not require pull-up devices or

CC

1998 Sep 04

8

Philips Semiconductors Product specification

SCC2692Dual asynchronous receiver/transmitter (DUART)

conditions of the UART. When this 8-bit port is used as a general
purpose output, the pins so defined will assume the compliment of
the associated bit in the Output Port Register (OPR). OPR(n) = 1
results in OP(n) = Low and vice versa. Bits of the OPR can be
individually set and reset. A bit is set by performing a write operation
at address H’E’ with the accompanying data specifying the bits to be
reset (1 = set, 0 = no change). Likewise, a bit is reset by a write at
address H’F’ with the accompanying data specifying the bits to be
reset (1 = reset, 0 = no change).

Outputs can be also individually assigned specific functions by
appropriate programming of the Channel A mode registers (MR1A,
MR2A), the Channel B mode registers (MR1B, MR2B), and the
Output Port Configuration Register (OPCR).

Output ports are driven high on hardware reset. Please note that
these pins drive both high and low. HOWEVER when they are
programmed to represent interrupt type functions (such as receiver
ready, transmitter ready or counter/timer ready) they will be switched
to an open drain configuration in which case an external pull-up
device would be required.

OPERATION
Transmitter

The SCC2692 is conditioned to transmit data when the transmitter is
enabled through the command register. The SCC2692 indicates to
the CPU that it is ready to accept a character by setting the TxRDY
bit in the status register. This condition can be programmed to
generate an interrupt request at OP6 or OP7 and INTRN. When a
character is loaded into the Transmit Holding Register (THR), the
above conditions are negated. Data is transferred from the holding
register to transmit shift register when it is idle or has completed
transmission of the previous character. The TxRDY conditions are
then asserted again which means one full character time of buffering
is provided. Characters cannot be loaded into the THR while the
transmitter is disabled.

The transmitter converts the parallel data from the CPU to a serial
bit stream on the TxD output pin. It automatically sends a start bit
followed by the programmed number of data bits, an optional parity
bit, and the programmed number of stop bits. The least significant
bit is sent first. Following the transmission of the stop bits, if a new
character is not available in the THR, the TxD output remains High
and the TxEMT bit in the Status Register (SR) will be set to 1.
Transmission resumes and the TxEMT bit is cleared when the CPU
loads a new character into the THR.

If the transmitter is disabled, it continues operating until the
character currently being transmitted is completely sent out. The
transmitter can be forced to send a continuous Low condition by
issuing a send break command.

The transmitter can be reset through a software command. If it is
reset, operation ceases immediately and the transmitter must be
enabled through the command register before resuming operation.
If CTS operation is enable, the CTSN input must be Low in order for
the character to be transmitted. If it goes High in the middle of a
transmission, the character in the shift register is transmitted and
TxDA then remains in the marking state until CTSN goes Low. The
transmitter can also control the deactivation of the RTSN output.
If programmed, the RTSN output will be reset one bit time after the
character in the transmit shift register and transmit holding register

(if any) are completely transmitted, if the transmitter has been
disabled.

Receiver

The SCC2692 is conditioned to receive data when enabled through
the command register. The receiver looks for a High-to-Low
(mark-to-space) transition of the start bit on the RxD input pin. If a
transition is detected, the state of the RxD pin is sampled each 16X
clock for 7-1/2 clocks (16X clock mode) or at the next rising edge of
the bit time clock (1X clock mode). If RxD is sampled High, the start
bit is invalid and the search for a valid start bit begins again. If RxD
is still Low, a valid start bit is assumed and the receiver continues to
sample the input at one bit time intervals at the theoretical center of
the bit, until the proper number of data bits and parity bit (if any)
have been assembled, and one stop bit has been detected. The
least significant bit is received first. The data is then transferred to
the Receive Holding Register (RHR) and the RxRDY bit in the SR is
set to a 1. This condition can be programmed to generate an
interrupt at OP4 or OP5 and INTRN. If the character length is less
than 8 bits, the most significant unused bits in the RHR are set to
zero.

After the stop bit is detected, the receiver will immediately look for
the next start bit. However, if a non-zero character was received
without a stop bit (framing error) and RxD remains Low for one half
of the bit period after the stop bit was sampled, then the receiver
operates as if a new start bit transition had been detected at that
point (one-half bit time after the stop bit was sampled).

The parity error, framing error, and overrun error (if any) are strobed
into the SR at the received character boundary, before the RxRDY
status bit is set. If a break condition is detected (RxD is Low for the
entire character including the stop bit), a character consisting of all
zeros will be loaded into the RHR and the received break bit in the
SR is set to 1. The RxD input must return to high for two (2) clock
edges of the X1 crystal clock for the receiver to recognize the end of
the break condition and begin the search for a start bit. This will

usually require a high time of one X1 clock period or 3 X1
edges since the clock of the controller is not synchronous to
the X1 clock.

Receiver FIFO

The RHR consists of a First-In-First-Out (FIFO) stack with a
capacity of three characters. Data is loaded from the receive shift
register into the topmost empty position of the FIFO. The RxRDY bit
in the status register is set whenever one or more characters are
available to be read, and a FFULL status bit is set if all three stack
positions are filled with data. Either of these bits can be selected to
cause an interrupt. A read of the RHR outputs the data at the top of
the FIFO. After the read cycle, the data FIFO and its associated
status bits (see below) are ‘popped’ thus emptying a FIFO position
for new data.

Receiver Status Bits

In addition to the data word, three status bits (parity error, framing
error, and received break) are also appended to each data character
in the FIFO (overrun is not). Status can be provided in two ways, as
programmed by the error mode control bit in the mode register. In
the ‘character’ mode, status is provided on a character-by-character
basis; the status applies only to the character at the top of the FIFO.
In the ‘block’ mode, the status provided in the SR for these three bits
is the logical-OR of the status for all characters coming to the top of
the FIFO since the last ‘reset error’ command was issued. In either

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