Philips SC28L91 User Manual

INTEGRATED CIRCUITS

SC28L91

3.3 V or 5.0 V Universal Asynchronous Receiver/Transmitter (UART)

Product data sheet Supersedes data of 2000 Sep 22

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2004 Oct 21

Philips Semiconductors Product data sheet

3.3 V or 5.0 V Universal Asynchronous Receiver/Transmitter (UART)

DESCRIPTION

The SC28L91 is a new member of the IMPACT family of Serial Communications Controllers. It is a single channel UART operating at 3.3 V and 5.0 V V with software of the SC28L92 and previous UARTs offered by Philips. It is a new part that is similar to our previous one channel part but is vastly improved. The improvements being: 16 character receiver, 16 character transmit FIFOs, watch dog timer for the receiver, mode register 0 is added, extended baud rate, over all faster bus and data speeds, programmable receiver and transmitter interrupts and versatile I/O structure. (The previous one channel part, SCC2691, is NOT being discontinued.)

Pin programming will allow the device to operate with either the Motorola or Intel bus interface. Bit 3 of the MR0 register allows the device to operate in an 8-byte FIFO mode if strict compliance with an 8-byte FIFO structure is required.

The Philips Semiconductors SC28L91 Universal Asynchronous Receiver/Transmitter (UART) is a single-chip CMOS-LSI communications device that provides a full-duplex asynchronous receiver/transmitter channel in a single package. It interfaces directly with microprocessors and may be used in a polled or interrupt driven system with modem and DMA interface.

The operating mode and data format of the channel can be programmed independently. Additionally , the receiver and transmitter can select its operating speed as one of 28 fixed baud rates; a 16X clock derived from a programmable counter/timer, or an external 1X or 16X clock. The baud rate generator and counter/timer can operate directly from a crystal or from external clock inputs. The ability to independently program the operating speed of the receiver and transmitter make the UART particularly attractive for dual-speed channel applications such as clustered terminal systems.

The receiver and transmitter is buffered by 8 or 16 character FIFOs to minimize the potential of receiver overrun, transmitter underrun and to reduce interrupt overhead in interrupt driven systems. In addition, a flow control capability is provided via RTS/CTS signaling to disable a remote transmitter when the receiver buffer is full.

DMA interface is and other general purpose signals are provided on the SC28L91 via a multipurpose 7-bit input port and a multipurpose 8-bit output port. These can be used as general-purpose ports or can be assigned specific functions (such as clock inputs or status/interrupt outputs, FIFO conditions) under program control.

The SC28L91 is available in two package versions: a 44-pin PLCC and 44-pin plastic quad flat pack (PQFP).

FEATURES

•Member of IMP ACT family: 3.3 to 5.0 volt , –40°C to +85°C and

68K for 80xxx bus interface for all devices.

•A full-duplex independent asynchronous receiver/transmitter

•16 character FIFOs for each receiver and transmitter

•Pin programming selects 68K or 80xxx-bus interface

•Programmable data format

– 5 to 8 data bits plus parity – Odd, even, no parity or force parity – – 1, 1.5 or 2 stop bits programmable in 1/16-bit increments

, 8 or 16 byte FIFOs and is quite compatible

SC28L91

•16-bit programmable Counter/Timer

•Programmable baud rate for each receiver and transmitter

selectable from:

– 28 fixed rates: 50 to 230.4 k baud – Other baud rates to 1 MHz at 16X

– Programmable user-defined rates derived from a programmable

counter/timer

– External 1X or 16X clock

•Parity, framing, and overrun error detection

•False start bit detection

•Line break detection and generation

•Programmable channel mode

– Normal (full-duplex) – Automatic echo – Local loop back – Remote loop back – Multi-drop mode (also called ‘wake-up’ or ‘9-bit’)

•Multi-function 7-bit input port (includes IACKN)

– Can serve as clock or control inputs – Change of state detection on four inputs – Inputs have typically >100 kΩ pull-up resistors – Change of state detectors for modem control

•Multi-function 8-bit output port

– Individual bit set/reset capability – Outputs can be programmed to be status/interrupt signals – FIFO status for DMA interface

•Versatile interrupt system

– Single interrupt output with eight maskable interrupting

conditions

– Output port can be configured to provide a total of up to six

separate interrupt outputs that may be wire ORed.

– Each FIFO can be programmed for four dif ferent interrupt levels

– Watchdog timer for the receiver

•Maximum data transfer rates:

1X – 1 Mbit/s, 16X – 1 Mbit/s

•Automatic wake-up mode for multi-drop applications

•Start-end break interrupt/status with mid-character break detect.

•On-chip crystal oscillator

•Power-down mode

•Receiver time-out mode

•Single +3.3 V or +5 V power supply

2004 Oct 21

Philips Semiconductors Product data sheet

3.3 V or 5.0 V Universal Asynchronous Receiver/Transmitter (UART)

ORDERING INORMATION

Industrial VCC = +3.3 V ± 10 %, +5 V ± 10 %

Description

44-Pin Plastic Leaded Chip Carrier (PLCC) 44-Pin Plastic Quad Flat Pack (PQFP)

amb

SC28L91A1A SC28L91A1B

= –40 °C to +85 °C

SC28L91

Drawing Number

SOT187-2 SOT307-2

2004 Oct 21

Philips Semiconductors Product data sheet

3.3 V or 5.0 V Universal Asynchronous Receiver/Transmitter (UART)

PIN CONFIGURATION DIAGRAM 80XXX PIN CONFIGURA TION

44 34

Pin Function

1A3 2 IP0 3 WRN 4 RDN 5V

6 No Connection 7 OP1 8 OP3

9 OP5 10 OP7 11 I/M 12 D1 13 D3 14 D5 15 D7

PQFP

12 22

Pin Function

16 GND 17 GND 18 INTRN 19 D6 20 D4 21 D2 22 D0 23 NC 24 OP6 25 OP4 26 OP2 27 OP0 28 TxDA 29 RxDA 30 x1/clk

Pin Function

31 x2 32 RESET 33 CEN 34 IP2 35 IP6 36 IP5 37 IP4 38 V

39 V

40 A0 41 IP3 42 A1 43 IP1 44 A2

SD00698

Pin Function

1NC 2A0 3 IP3 4A1 5 IP1 6A2 7A3 8 IP0

9 WRN 10 RDN 11 V

12 I/M 13 No Connection 14 OP1 15 OP3

Pin Function

16 OP5 17 OP7 18 D1 19 D3 20 D5 21 D7 22 V 23 NC 24 INTRN 25 D6 26 D4 27 D2 28 D0 29 OP6 30 OP4

PLCC

SC28L91

Pin Function

31 OP2 32 OP0 33 TxDA 34 NC 35 RxDA 36 X1/CLK 37 X2 38 RESET 39 CEN 40 IP2 41 IP6 42 IP5 43 IP4 44 V

SD00699

Note: Pins marked “No Connection” must NOT be connected.

2004 Oct 21

Philips Semiconductors Product data sheet

3.3 V or 5.0 V Universal Asynchronous Receiver/Transmitter (UART)

PIN CONFIGURATION DIAGRAM 68XXX PIN CONFIGURA TION

44 34

Pin Function

1A3 2 IP0 3 R/WN 4 DACKN 5V

6 No Connection 7 OP1 8 OP3

9 OP5 10 OP7 11 I/M 12 D1 13 D3 14 D5 15 D7

PQFP

12 22

Pin Function

16 GND 17 GND 18 INTRN 19 D6 20 D4 21 D2 22 D0 23 NC 24 OP6 25 OP4 26 OP2 27 OP0 28 TxDA 29 RxDA 30 x1/clk

Pin Function

31 x2 32 RESETN 33 CEN 34 IP2 35 IACKN 36 IP5 37 IP4 38 V

39 V

40 A0 41 IP3 42 A1 43 IP1 44 A2

SD00700

Pin Function

1NC 2A0 3 IP3 4A1 5 IP1 6A2 7A3 8 IP0

9 R/WN 10 DACKN 11 V

12 I/M 13 No Connection 14 OP1 15 OP3

Pin Function

16 OP5 17 OP7 18 D1 19 D3 20 D5 21 D7 22 V 23 NC 24 INTRN 25 D6 26 D4 27 D2 28 D0 29 OP6 30 OP4

PLCC

SC28L91

Pin Function

31 OP2 32 OP0 33 TxDA 34 NC 35 RxDA 36 X1/CLK 37 X2 38 RESETN 39 CEN 40 IP2 41 IACKN 42 IP5 43 IP4 44 V

SD00701

Note: Pins marked “No Connection” must NOT be connected.

2004 Oct 21

Philips Semiconductors Product data sheet

3.3 V or 5.0 V Universal Asynchronous Receiver/Transmitter (UART)

D0–D7

RDN

WRN

CEN

A0–A3

RESET

INTRN

BUS BUFFER

OPERATION CONTROL

ADDRESS

DECODE

R/W CONTROL

INTERRUPT CONTROL

IMR ISR

DATA CHANNEL

16 BYTE TRANSMIT

FIFO

TRANSMIT

SHIFT REGISTER

16 BYTE RECEIVE

FIFO

WATCH DOG TIMER

RECEIVE SHIFT

CRA SRA

SC28L91

TxDA

RxDA

X1/CLK

TIMING

BAUD RATE

GENERATOR

CLOCK

SELECTORS

COUNTER/

TIMER

XTAL OSC

CSR ACR CTL CTU

CONTROL

TIMING

INTERNAL DATABUS

Figure 1. Block Diagram (80XXX mode)

INPUT PORT CHANGE OF

STATE

DETECTORS (4)

IPCR ACR

OUTPUT PORT

FUNCTION

SELECT LOGIC

OPCR

OPR

IP0-IP6

OP0-OP7

SD00702

2004 Oct 21

Philips Semiconductors Product data sheet

3.3 V or 5.0 V Universal Asynchronous Receiver/Transmitter (UART)

D0–D7

R/WN

IACKN

CEN

A0–A3

RESETN

INTRN

DACKN

BUS BUFFER

OPERATION CONTROL

ADDRESS

DECODE

R/W CONTROL

INTERRUPT CONTROL

IMR

ISR IVR

DATA CHANNEL

16 BYTE TRANSMIT

FIFO

TRANSMIT

SHIFT REGISTER

16 BYTE RECEIVE

FIFO

WATCH DOG TIMER

RECEIVE SHIFT

CRA SRA

SC28L91

TxDA

RxDA

X1/CLK

TIMING

BAUD RATE

GENERATOR

CLOCK

SELECTORS

COUNTER/

TIMER

XTAL OSC

CSR ACR CTL CTU

CONTROL

TIMING

INTERNAL DATABUS

Figure 2. Block Diagram (68XXX mode)

INPUT PORT CHANGE OF

STATE

DETECTORS (4)

IPCR

ACR

OUTPUT PORT

FUNCTION

SELECT LOGIC

OPCR

OPR

IP0-IP5

OP0-OP7

SD00703

2004 Oct 21

Philips Semiconductors Product data sheet

3.3 V or 5.0 V Universal Asynchronous Receiver/Transmitter (UART)

PIN CONFIGURATION FOR 80XXX BUS INTERFACE (INTEL)

Symbol

I/M I Bus Configuration: When high or not connected configures the bus interface to the Conditions shown in this table. D0–D7 I/O Data Bus: Bi-directional 3-State data bus used to transfer commands, data and status between the UART and the

CEN I Chip Enable: Active-Low input signal. When Low, data transfers between the CPU and the UART are enabled on

WRN I Write Strobe: When Low and CEN is also Low, the contents of the data bus is loaded into the addressed register. The

RDN I Read Strobe: When Low and CEN is also Low, causes the contents of the addressed register to be presented on the

A0–A3 I Address Inputs: Select the UART internal registers and ports for read/write operations. RESET I Reset: A High level clears internal registers (SR, IMR, ISR, OPR, OPCR), puts OP0–OP7 in the High state, stops the

INTRN O Interrupt Request: Active-Low, open-drain, output which signals the CPU that one or more of the eight maskable in-

X1/CLK I Crystal 1: Crystal or external clock input. A crystal or clock of the specified limits must be supplied at all times. When a

X2 O Crystal 2: Connection for other side of the crystal. When a crystal is used, a capacitor must be connected from this pin

RxD I Receiver Serial Data Input: The least significant bit is received first. “Mark” is High; “space” is Low. TxD O Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the “mark” condition

OP0 O Output 0: General-purpose output or request to send (RTSN, active-Low). Can be deactivated automatically on re-

OP1 O Output 1: General-purpose output. OP2 O Output 2: General-purpose output, or transmitter 1X or 16X clock output, or receiver 1X clock output. OP3 O Output 3: General-purpose output. OP4 O Output 4: General-purpose output or open-drain, active-Low, Rx interrupt ISR[1] output. DMA Control OP5 O Output 5: General-purpose output OP6 O Output 6: General-purpose output or open-drain, active-Low, Tx interrupt ISR[0] output. DMA Control OP7 O Output 7: General-purpose output. IP0 I Input 0: General-purpose input or clear to send active-Low input (CTSN). Has Change of State Dector. IP1 I Input 1: General-purpose input. Has Change of State Dector. IP2 I Input 2: General-purpose input or counter/timer external clock input. Has Change of State Dector. IP3 I Input 3: General-purpose input or transmitter external clock input (TxC). When the external clock is used by the trans-

IP4 I Input 4: General-purpose input or receiver external clock input (RxC). When the external clock is used by the receiver,

IP5 I Input 5: General-purpose input IP6 I Input 6: General-purpose input V

GND Pwr Ground

type

Pwr Power Supply: +3.3 V or +5 V supply input ± 10 %

Name and function

CPU. D0 is the least significant bit.

D0–D7 as controlled by the WRN, RDN and A0–A3 inputs. When High, places the D0–D7 lines in the 3-State condition.

transfer occurs on the rising edge of the signal.

data bus. The read cycle begins on the falling edge of RDN.

counter/timer, and puts the Channel in the inactive state, with the TxD outputs in the mark (High) state. Sets MR pointer to MR1. See Figure 4

terrupting conditions are true. This pin requires a pull-up device.

crystal is used, a capacitor must be connected from this pin to ground (see Figure 11).

to ground (see Figure 11). If X1/CLK is driven from an external source, this pin must be left open.

when the transmitter is disabled, idle or operating in local loop back mode. “Mark” is High; “space” is Low.

ceive or transmit.

mitter, the transmitted data is clocked on the falling edge of the clock. Has Change of State Dector.

the received data is sampled on the rising edge of the clock.

SC28L91

2004 Oct 21

Philips Semiconductors Product data sheet

3.3 V or 5.0 V Universal Asynchronous Receiver/Transmitter (UART)

PIN CONFIGURATION FOR 68XXX BUS INTERFACE (MOTOROLA)

ÁÁ

Symbol

I/M D0–D7

CEN

ÁÁ

R/WN IACKN

DACKN

ÁÁ

A0–A3 RESETN

ÁÁ

INTRN

X1/CLK

ÁÁ

RxD TxD

ÁÁ

OP0

OP1 OP2 OP3 OP4 OP5 OP6 OP7 IP0 IP1 IP2 IP3

IP4

ÁÁ

IP5 V

GND

type

I I/O

I I

I O

O O O O O O O I I I I

I Pwr Pwr

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Name and function Bus Configuration: When low configures the bus interface to the Conditions shown in this table. Data Bus: Bi-directional 3-State data bus used to transfer commands, data and status between the UART and the

CPU. D0 is the least significant bit. Chip Enable: Active-Low input signal. When Low, data transfers between the CPU and the UART are enabled on

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D0–D7 as controlled by the R/WN and A0–A3 inputs. When High, places the D0–D7 lines in the 3-State condition.

Read/Write: Input Signal. When CEN is low R/WN high input indicates a read cycle; when low indicates a write cycle. Interrupt Acknowledge: Active low input indicating an interrupt acknowledge cycle. Usually asserted by the CPU in

response to an interrupt request. When asserted places the interrupt vector on the bus and asserts DACKN. Data Transfer Acknowledge: A3-State active-low output asserted in a write, read, or interrupt acknowledge cycle to

indicate proper transfer of data between the CPU and the UART.

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Address Inputs: Select the UART internal registers and ports for read/write operations. Reset: A low level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OP0–OP7 in the High state,

stops the counter/timer, and puts the Channel in the inactive state, with the TxD outputs in the mark (High) state. Sets MR pointer to MR1. See Figure 4

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Interrupt Request: Active-Low, open-drain, output which signals the CPU that one or more of the eight maskable interrupting conditions are true. This pin requires a pullup.

Crystal 1: Crystal or external clock input. A crystal or clock of the specified limits must be supplied at all times. When a crystal is used, a capacitor must be connected from this pin to ground (see Figure 11).

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Crystal 2: Connection for other side of the crystal. When a crystal is used, a capacitor must be connected from this pin to ground (see Figure 11). If X1/CLK is driven from an external source, this pin must be left open.

Receiver Serial Data Input: The least significant bit is received first. “Mark” is High, “space” is Low. Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the ‘mark’ condition

when the transmitter is disabled, idle, or when operating in local loop back mode. ‘Mark’ is High; ‘space’ is Low.

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Output 0: General purpose output or request to send (RTSAN, active-Low). Can be deactivated automatically on receive or transmit.

Output 1: General-purpose output. Output 2: General purpose output or transmitter 1X or 16X clock output, or receiver 1X clock output. Output 3: General purpose output. Output 4: General purpose output or open-drain, active-Low , RxA interrupt ISR [1] output. DMA Control Output 5: General-purpose output. Output 6: General purpose output or open-drain, active-Low, TxA interrupt ISR[0] output. DMA Control Output 7: General-purpose output. Input 0: General purpose input or clear to send active-Low input (CTSAN). Has Change of State Dector. Input 1: General purpose input. Has Change of State Dector. Input 2: General-purpose input or counter/timer external clock input. Has Change of State Dector. Input 3: General purpose input or transmitter external clock input (TxC). When the external clock is used by the trans-

mitter, the transmitted data is clocked on the falling edge of the clock. Has Change of State Dector.

Input 4: General purpose input or receiver external clock input (RxC). When the external clock is used by the receiver,

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the received data is sampled on the rising edge of the clock.

Input 5: General purpose input. Power Supply: +3.3 or +5V supply input ±10%

Ground

SC28L91

2004 Oct 21

Philips Semiconductors Product data sheet

3.3 V or 5.0 V Universal Asynchronous Receiver/Transmitter (UART)

ABSOLUTE MAXIMUM RATINGS

Symbol

amb

stg

Derating factor above 25 °C (PLCC44) 19 mW/°C

NOTES:

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not implied.

2. For operating at elevated temperatures, the device must be derated based on +150°C maximum junction temperature.

3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.

4. Parameters are valid over specified temperature and voltage range.

Parameter Rating Unit

Operating ambient temperature range Storage temperature range –65 to +150 °C Voltage from VCC to GND Voltage from any pin to GND Package power dissipation (PLCC44) 2.4 W Package power dissipation (PQFP44) 1.78 W

Derating factor above 25 °C (PQFP44) 14 mW/°C

DC ELECTRICAL CHARACTERISTICS

= 5 V ± 10 %, T

Symbol

IX1PD

ILX1

IHX1

Parameter Conditions Min Typ Max Unit

Input low voltage 0.8 V Input high voltage (except X1/CLK) 2.4 1.5 V Input high voltage (X1/CLK) 0.8V Output low voltage

Output high voltage (except OD outputs) X1/CLK input current - power down X1/CLK input low current - operating VIN = 0 V –130 0 µA

X1/CLK input high current - operating VIN = V Input leakage current:

All except input port pins VIN = 0 V to V Input port pins

OZH

OZL

ODL

ODH

Output off current high, 3-State data bus VIN = V Output off current low , 3-State data bus VIN = 0 V –0.5 µA Open-drain output low current in off-state VIN = 0 V –0.5 µA Open-drain output high current in off-state VIN = V Power supply current

Operating mode CMOS input levels 7 25 mA Power down mode CMOS input levels ≤1 5

NOTES:

1. Parameters are valid over specified temperature and voltage range.

2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of 5 ns maximum. For X1/CLK, this swing is between 0.4 V and 0.8VCC. All time measurements are referenced at input voltages of 0.8 V and

2.0 V and output voltages of 0.8 V and 2.0 V , as appropriate.

3. Typical values are at +25 °C, typical supply voltages, and typical processing parameters.

4. Test conditions for outputs: C constant current source = 2.6 mA.

5. Input port pins have active pull-up transistors that will source a typical 2 µA from V Input port pins at V

6. All outputs are disconnected. Inputs are switching between CMOS levels of V

= –40 °C to +85 °C, unless otherwise specified.

amb

= 125 pF, except open drain outputs. Test conditions for open drain outputs: CL = 125 pF,

source 0.0 µA.

Note 4 °C

–0.5 to +7.0 V –0.5 to VCC +0.5 V

1, 2, 3

2.4 V

= 2.4 mA

= –400 µA

= 0 V to V

VIN = 0 V to V

CC CC

when the input pins are at VSS.

– 0.2 V and VSS + 0.2 V.

0.5 0.05 0.5 µA

0 130 µA

–0.5 0.05 +0.5 µA –8 0.05 +0.5 µA

0.2 0.4 V

– 0.5 V

SC28L91

0.5 µA

2004 Oct 21

Philips Semiconductors Product data sheet

3.3 V or 5.0 V Universal Asynchronous Receiver/Transmitter (UART)

DC ELECTRICAL CHARACTERISTICS

= 3.3 V ± 10 %, T

Symbol

IX1PD

ILX1

IHX1

Parameter Conditions Min Typ Max Unit

Input low voltage 0.65 0.2*V Input high voltage 0.8*V Output low voltage

Output high voltage (except OD outputs) X1/CLK input current - power down X1/CLK input low current - operating VIN = 0 V –80 0 µA

X1/CLK input high current - operating VIN = V Input leakage current:

All except input port pins VIN = 0 V to V Input port pins

OZH

OZL

ODL

ODH

Operating mode CMOS input levels 5 mA Power down mode CMOS input levels ≤1 5.0

NOTES:

1. Parameters are valid over specified temperature and voltage range.

2.0 V and output voltages of 0.8 V and 2.0 V , as appropriate.

3. Typical values are at +25 °C, typical supply voltages, and typical processing parameters.

4. Test conditions for outputs: C constant current source = 2.6 mA.

5. Input port pins have active pull-up transistors that will source a typical 2 µA from V Input port pins at V

6. All outputs are disconnected. Inputs are switching between CMOS levels of V

= –40 °C to +85 °C, unless otherwise specified.

amb

= 125 pF, except open drain outputs. Test conditions for open drain outputs: CL = 125 pF,

source 0.0 µA.

1, 2, 3

1.7 V

= 2.4 mA

= –400 µA

= 0 V to V

VIN = 0 V to V

CC CC

. All time measurements are referenced at input voltages of 0.8 V and

when the input pins are at VSS.

– 0.2 V and VSS + 0.2 V.

VCC – 0.5 VCC – 0.2 V –0.5 0.05 +0.5 µA

0 80 µA

–0.5 0.05 +0.5 µA –8 0.5 +0.5 µA

0.2 0.4 V

SC28L91

0.5 µA

2004 Oct 21

Philips Semiconductors Product data sheet

3.3 V or 5.0 V Universal Asynchronous Receiver/Transmitter (UART)

AC CHARACTERISTICS (5 VOL T)

= 5.0 V ± 10 %, T

Symbol

Parameter

Reset Timing (See Figure 4)

RES

Reset pulse width

Bus Timing5 (See Figure 5)

*AS

*AH

*CS

*CH

*RW

*DD

*DA

*DF

*DI

*DS

*DH

*RWD

A0–A3 setup time to RDN, WRN Low A0–A3 hold time from RDN, WRN low CEN setup time to RDN, WRN low CEN Hold time from RDN. WRN low WRN, RDN pulse width (Low time) Data valid after RDN low (125pF load. See Figure 3 for smaller loads.) RDN low to data bus active Data bus floating after RDN or CEN high RDN or CEN high to data bus invalid Data bus setup time before WRN or CEN high (write cycle) Data hold time after WRN high High time between read and/or write cycles

Port Timing5 (See Figure 9)

t t t

*PS *PH *PD

Port in setup time before RDN low (Read IP ports cycle) Port in hold time after RDN high OP port valid after WRN or CEN high (OPR write cycle)

Interrupt Timing (See Figure 10)

*IR

INTRN (or OP3–OP7 when used as interrupts) negated from:

Clock Timing (See Figure 11)

*CLK

*CTC

*RX

X1/CLK high or low time X1/CLK frequency C/T Clk (IP2) high or low time (C/T external clock input) C/T Clk (IP2) frequency8 (for higher speeds contact factory) RxC high or low time (16X) RxC Frequency (16X)(for higher speeds contact factory)

RxC Frequency (1x) t f

*TX *TX

TxC High or low time (16X)

TxC frequency (16X) (for higher speeds contact factory)

TxC frequency (1X)

Transmitter Timing, external clock (See Figure 12)

*TXD

*TCS

TxD output delay from TxC low (TxC input pin)

Output delay from TxC output pin low to TxD data output

= –40 °C to +85 °C, unless otherwise specified.

amb

Read RxFIFO (RxRDY/FFULL interrupt) Write TxFIFO (TxRDY interrupt) Reset Command (delta break change interrupt) Stop C/T command (Counter/timer interrupt Read IPCR (delta input port change interrupt) Write IMR (Clear of change interrupt mask bit(s))

(for higher speeds contact factory)

8, 9

1, 2, 3, 4

5, 7

Min

100

10 20 0 0 15

0 25 0 17

0 0

0.1 30 0 30 0 0 30

Typ

6 12

8 40

–12

–20 –20 40

40 40 40 40 40 40

3.686 10

40 6

SC28L91

Max

60 60 60 60 60 60

8.0

16 1

60 30

Unit

ns ns ns ns ns ns ns ns ns ns ns ns

ns ns ns

ns ns ns ns ns ns

ns MHz ns MHz ns MHz MHz ns MHz MHz

ns ns

2004 Oct 21

Philips Semiconductors Product data sheet

3.3 V or 5.0 V Universal Asynchronous Receiver/Transmitter (UART)

Typ

Symbol

Parameter Receiver Timing, external clock (See Figure 13)

*RXS

*RXH

68000 or Motorola bus timing (See Figures 6, 7, 8)

DCR

DCW

DAT

CSC

RxD data setup time to RxC high

RxD data hold time from RxC high

DACKN Low (read cycle) from X1 High

DACKN Low (write cycle) from X1 High

DACKN High impedance from CEN or IACKN High

CEN or IACKN setup time to X1 High for minimum DACKN cycle

NOTES:

1. Parameters are valid over specified temperature and voltage range.

2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of 5 ns maximum. For X1/CLK this swing is between 0.4 V and 0.8*V

2.0 V and output voltages of 0.8 V and 2.0 V , as appropriate.

. All time measurements are referenced at input voltages of 0.8 V and

3. Test conditions for outputs: CL = 125 pF, except open drain outputs. Test conditions for open drain outputs: C constant current source = 2.6 mA.

4. Typical values are the average values at +25 °C and 5 V.

5. Timing is illustrated and referenced to the WRN and RDN Inputs. Also, CEN may be the “strobing” input. CEN and RDN (also CEN and WRN) are ORed internally. The signal asserted last initiates the cycle and the signal negated first terminates the cycle.

6. Guaranteed by characterization of sample units.

7. If CEN is used as the “strobing” input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must be negated for t

8. Minimum frequencies are not tested but are guaranteed by design.

to guarantee that any status register changes are valid.

RWD

9. Clocks for 1X mode should maintain a 60/40 duty cycle or better.

= t

+ t

10.Minimum DACKN time is t while in the 68XXX mode. It is not necessary to wait for DACKN to insure the proper operation of the SC28C91. In all cases the data will be

DCR

DSC

+ two positive edges of the X1 clock. For faster bus cycles, the 80XXX bus timing may be used

DCR

written to the SC28L91 on the falling edge of DACKN or the rise of CEN. The fall of CEN initializes the bus cycle. The rise of CEN ends the bus cycle. DACKN low or CEN high completes the write cycle.

Min

50 50

40 40

15 15 8

= 125 pF,

SC28L91

Max

35 35 10

Unit

ns ns

ns ns ns ns

(ns)

NOTES:

Bus cycle times:

(80XXX mode): tDD + t (68XXX mode) = t

12 pF 100 pF

0 20 40 60 80 100 120 140 160 180 200 220 240

= 70 ns @ 5V, 40 ns @ 3.3 V + rise and fall time of control signals

RWD

+ t

CSC

+ 1 cycle of the X1 clock @ 5 V + rise and fall time of control signals

DAT

125 pF30 pF 230 pF

SD00684

Figure 3. Port Timing vs. Capacitive Loading at typical conditions

= 3.3 V @ +25 °C

5.0 V @ +25 °C

2004 Oct 21

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