Philips SC28L194C1A, SC28L194C1BE, SC28L194A1A Datasheet

 

SC28L194

Quad UART for 3.3V and 5V supply voltage

Preliminary specification Supersedes data of 1995 Dec 14 IC19 Data Handbook

1998 Sep 21

INTEGRATED CIRCUITS

Philips Semiconductors Preliminary specification

SC28L194Quad UART for 3.3V and 5V supply voltage

1998 Sep 21

DESCRIPTION

The Philips 28L194 Quad UART is a single chip CMOS-LSI communications device that provides 4 full-duplex asynchronous channels with significantly deeper 16 byte FIFOs, Automatic in-band flow control using Xon/Xoff characters defined by the user and address recognition in the Wake-up mode. Synchronous bus interface is used for all communication between host and QUART. It is fabricated in Philips state of the art CMOS technology that combines the benefits of low cost, high density and low power consumption.

The operating speed of each receiver and transmitter can be selected independently from one of 22 fixed baud rates, a 16X clock derived from one of two programmable baud rate counters or one of three external 16X clocks (1 available at 1x clock rate). The baud rate generator and counter can operate directly from a crystal or from seven other external or internal clock inputs. The ability to independently program the operating speed of the receiver and transmitter makes the Quad UART particularly attractive for dual speed full duplex channel applications such as clustered terminal systems. The receivers and transmitters are buffered with FIFOs of 16 characters to minimize the potential for receiver overrun and to reduce interrupt overhead. In addition, a handshaking capability and in-band flow control are provided to disable a remote UART transmitter when the receiver buffer is full or nearly so.

To minimize interrupt overhead an interrupt arbitration system is included which reports the context of the interrupting UART via direct access or through the modification of the interrupt vector. The context of the interrupt is reported as channel number, type of device interrupting (receiver COS etc.) and, for transmitters or receivers, the fill level of the FIFO.

The Quad UART provides a power down mode in which the oscillator is stopped but the register contents are maintained. This results in reduced power consumption of several orders of magnitudes. The Quad UART is fully TTL compatible when operating from a single +5V or 3.3V power supply. Operation at 3.3V or 5.0V is maintained with CMOS interface levels.

Uses

• Statistical Multiplexers

• Data Concentrators

– Packet-switching networks – Process Control – Building or Plant Control – Laboratory data gathering – ISDN front ends – Computer Networks – Point-of-Sale terminals

• Automotive, cab and engine controls

• Entertainment systems

– MIDDI keyboard control music systems – Theater lighting control

• Terminal Servers

– Computer-Printer/Plotter links

FEA TURES

• Single 3.3V and 5.0V power supply

• Four Philips industry standard full duplex UART channels

• Sixteen byte receiver FIFOs for each UART

• Sixteen byte transmit FIFOs for each UART

• In band flow control using programmable Xon/Xoff characters

• Flow control using CTSN RTSN hardware handshaking

• Automatic address detection in multi-drop mode

• Three byte general purpose character recognition

• Fast data bus, 15 ns data bus release time, 125 ns bus cycle time

• Programmable interrupt priorities

• Automatic identification of highest priority interrupt pending

• Global interrupt and control registers ease setup and interrupt

handling

• Vectored interrupts with programmable interrupt vector formats

– Interrupt vector modified with channel number – Interrupt vector modified with channel number and channel type – Interrupt vector not modified

•IACKN and DACKN signal pins

• Watch dog timer for each receiver (64 receive clock counts)

• Programmable Data Formats:

– 5 to 8 data bits plus parity – Odd, even force or no parity – 1, 1.5 or 2 stop bits

• Flexible baud rate selection for receivers and transmitters:

– 22 fixed rates; 50 - 230.4K baud or 100 to 460.8K baud – Additional non-standard rates to 500K baud with internal

generators

– Two reload-counters provide additional programmable baud

rate generation – External 1x or 16x clock inputs – Simplified baud rate selection

• 1 MHz 1x and 16x data rates full duplex all channels.

• Parity, framing and overrun error detection

• False start bit detection

• Line break detection and generation

• Programmable channel mode

– Normal(full duplex) – Diagnostic modes

automatic echo

local loop back

emote loop back

• Four I/O ports per UART for modem controls, clocks, RTSN, I/O,

etc. – All I/O ports equipped with “Change of State Detectors”

• Two global inputs and two global outputs for general purpose I/O

• Power down mode

• On chip crystal oscillator, 2-8 MHz

• TTL input levels. Outputs switch between full V

and V

• High speed CMOS technology

• 80-pin Low Profile Quad Flat Pack LQFP and 68-pin PLCC

Philips Semiconductors Preliminary specification

SC28L194Quad UART for 3.3V and 5V supply voltage

1998 Sep 21

ORDERING CODE

VCC = 3.3V ±10% VCC = 5V ±10%

PACKAGES

Industrial Industrial

DWG #

Industrial

-40°C to +85°C

Industrial

-40°C to +85°C

68-Pin Plastic Leaded Chip Carrier (PLCC) SC28L194A1A SC28L194A1A SOT188-3 80-Pin Plastic Low Profile Quad Flat Pack (LQFP) SC28L194A1BE SC28L194A1BE SOT315-1

PIN CONFIGURATIONS

161

27 43

21 40

68-Pin PLCC

TOP VIEW

80-Pin LQFP

TOP VIEW

SD00544

Figure 1. Pin Configurations

PINOUT - 68 PIN PACKAGE Pin Assignments

4 Vss_ic, 4 Vcc_i, 4 Vss_o, 2 Vcc_o, 2Vcc_c

Vss_ic

I/O0c

Vcc_c

I/O1c

Vcc_i

Vss_o

W_RN

I/O2c

VCC_O

I/O3c

CEN

RxDc

DACKN

TxDc

VSS_IC

I/O0a

RxDd

VCC_I

I/O1a

TxDd

I/O2a

Vcc_c

I/O3a

Vcc_i

IRQN

Vss_o

Vss_ic

IACKN

RxDa

RESETN

VSS_O

TxDa

Gin0

I/O0b

Gin1

I/O1b

I/O0d

Vcc_o

I/O1d

Vcc_i

I/O2d

Vss_ic

Gout0

I/O2b

I/O3d

I/O3b

Gout1

RxDb

Vss_o

SClk

TxDb

PINOUT - 80 PIN THIN PACKAGE Pin Assignments

4 Vss_ic, 4 Vcc_i, 4 Vss_o, 2 Vcc_o, 2Vcc_c

I/O1a

TxDd

ÁÁÁÁ

I/O2a

Vcc_c

ÁÁÁÁ

I/O3a

Vcc_i

ÁÁÁÁ

IRQN

Vss_o

Vss_ic

ÁÁÁÁ

IACKN

RxDa

RESETN

ÁÁÁÁ

Vss_o

TxDa

Gin0

I/O0b

Gin1

ÁÁÁÁ

I/O1b

I/O0d

61-62

ÁÁÁÁ

Vcc_o

I/O1d

ÁÁÁÁ

Vcc_i

I/O2d

ÁÁÁÁ

Vss_ic

Gout0

I/O2b

39-41

ÁÁÁÁ

I/O3b

I/O3d

ÁÁÁÁ

RxDb

Gout1

ÁÁÁÁ

TxDb

Vss_o

ÁÁÁÁ

SClk

I/O0c

Vss_ic

I/O1c

ÁÁÁÁ

Vcc_c

Vss_o

ÁÁÁÁ

Vcc_i

I/O2c

ÁÁÁÁ

W_RN

20-23

Vcc_o

ÁÁÁÁ

I/O3c

ÁÁÁÁ

CEN

RxDc

DACKN

TxDc

Vss_ic

ÁÁÁÁ

I/O0a

RxDd

Vcc_i

78-80

ÁÁÁÁ

NOTE: The Vss-ic and Vcc_i are for input and noise sensitive circuits. Sclk signals in the range of 3 to 6 ns and within TTL input levels may alter expected read or write functions. The Vss _o and Vcc _o pins are used for the high current drivers. De-coupling capacitors should be used as close to the device power pins as possible. Address bit A6 is not used. See “Host Interface” section.

Philips Semiconductors Preliminary specification

SC28L194Quad UART for 3.3V and 5V supply voltage

1998 Sep 21

Pin Description

MNEMONIC

ÁÁÁ

TYPE

DESCRIPTION

ÁÁÁÁ

SClk

ÁÁÁ

ÁÁ

БББББББББББББББББББББББББ

Host system clock. Used to time operations in the Host Interface and clock internal logic. Must be greater than twice the frequency of highest X1, Counter/Timer, TxC (1x) or RxC (1x) input frequency.

CEN

ÁÁÁ

Chip select: Active low. When asserted, allows I/O access to QUART registers by host CPU. W_RN signal indicates direction. (Must not be active in IACKN cycle)

A(7:0)

ÁÁÁ

Address lines (A[6] is NOT used. See “Host Interface” )

D(7:0)

ÁÁÁ

I/O

8-bit bi-directional data bus. Carries command and status information between 28L194 and the host CPU. Used to convey parallel data for serial I/O between the host CPU and the 28L194

ÁÁÁÁ

W_RN

ÁÁÁ

ÁÁ

БББББББББББББББББББББББББ

Write Read not control: When high indicates that the host CPU will write to a 28L194 register or transmit FIFO. When low, indicates a read cycle. 0 = Read; 1 = W rite

DACKN

ÁÁÁ

Data Acknowledge: Active low. When asserted, it signals that the last transfer of the D lines is complete.

Open drain requires a pull-up device.

ÁÁÁÁ

IRQN

ÁÁÁ

ÁÁ

БББББББББББББББББББББББББ

Interrupt Request: Active low. When asserted, indicates that the 28L194 requires service for pending interrupt(s). Open drain requires a pull-up device.

IACKN

ÁÁÁ

Interrupt Acknowledge: Active low. When asserted, indicates that the host CPU has initiated an interrupt acknowledge cycle. (Do not use CEN in an IACKN cycle)

TD(a-d)

ÁÁÁ

Transmit Data: Serial outputs from the 4 UARTs.

RD(a-d)

ÁÁÁ

Receive Data: Serial inputs to the 4 UARTs

I/O0(a-d)

ÁÁÁ

I/O

Input/Output 0: Multi-use input or output pin for the UART.

I/O1(a-d)

I/O

Input/Output 1: Multi-use input or output pin for the UART.

I/O2(a-d)

ÁÁÁ

I/O

Input/Output 2: Multi-use input or output pin for the UART.

I/O3(a-d)

ÁÁÁ

I/O

Input/Output 3: Multi-use input or output pin for the UART.

Gin(1:0)

ÁÁÁ

Global general purpose inputs, available to any/all channels.

Gout(1:0)

ÁÁÁ

Global general purpose outputs, available from any channel.

RESETN

ÁÁÁ

Master reset: Active Low. Must be asserted at power up and may be asserted at other times to reset and restart the system. See “Reset Conditions” at end of register map. Minimum width 10 SCLK.

X1/CCLK

ÁÁÁ

Crystal 1 or Communication Clock: This pin may be connected to one side of a 2-8 MHz crystal. It may alternatively be driven by an external clock in this frequency range. Standard frequency = 3.6864 MHz

ÁÁÁÁ

ÁÁÁ

ÁÁ

БББББББББББББББББББББББББ

Crystal 2: If a crystal is used, this is the connection to the second terminal. If a clock signal drives X1, this pin must be left unconnected.

Power Supplies

ÁÁÁ

16 pins total 8 pins for Vss, 8 pins for Vcc

NOTE:

1. Many output pins will have very fast edges, especially when lightly loaded (less than 20 pf). These edges may move as fast as 1 to 3 ns fall or rise time. The user must be aware of the possible generation of ringing and reflections on improperly terminated interconnections. See previous note on Sclk noise under pin assignments.

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

RATING

UNIT

amb

Operating ambient temperature range

See Note 3

°C

stg

Storage temperature range

-65 to +150

°C

Voltage from VDD to V

-0.5 to +7.0

Voltage from any pin to V

-0.5 to VCC + 0.5

Package Power Dissipation (PLCC)

2.87

Package Power Dissipation (LQFP)

Derating factor above 25°C (PLCC package)

mW/°C

Derating factor above 25°C (LQFP package)

mW/°C

NOTES:

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the Operation Section of this specification is not implied.

2. For operating at elevated temperatures, the device must be derated based on +150°C maximum junction temperature.

3. Parameters are valid over specified temperature range. See Ordering Information table for applicable temperature range and operating supply range.

4. This product includes circuitry specifically designed for the protewction of its internal devices from damaging effects of excessive static charge.

Philips Semiconductors Preliminary specification

SC28L194Quad UART for 3.3V and 5V supply voltage

1998 Sep 21

BLOCK DIAGRAM

Block Diagram SC28L194

HOST INTERFACE

TIMING AND BAUD RATE

GENERATOR

INTERRUPT ARBITRATION

I/O PORT TIMING AND

INTERFACE

FULL DUPLEX UART CHANNEL

INPUT BUFFERS AND OUTPUT DRIVERS

DATA DRIVERS AND MODEM INTERFACE

SD00524

Figure 2. Block Diagram

As shown in the block diagram, the Quad UART consists of an interrupt arbiter, host interface, timing blocks and four UART channel blocks. The four channels blocks operate independently, interacting only with the timing, host I/F and interrupt blocks.

FUNCTIONAL DESCRIPTION

The SC28L194 is composed of several functional blocks:

• Synchronous host interface block

• A timing block consisting of a common baud rate generator

making 22 industry standard baud rates and 2 16-bit counters used for non-standard baud rate generation

• 4 identical independent full duplex UART channel blocks

• Interrupt arbitration system evaluating 24 contenders

• I/O port control section and change of state detectors.

CONCEPTUAL OVERVIEW Host Interface

The Host interface is comprised of the signal pins CEN, W/RN, IACKN, DACKN, IRQN Sclk and provides all the control for data transfer between the external and internal data buses of the host and the QUART. The host interface operates in a synchronous mode with the system (Sclk) which has been designed for a nominal operating frequency of 33 MHz. The interface operates in either of two modes; synchronous or asynchronous to the Sclk However the bus cycle within the QUART always takes place in four Sclk cycles after CEN is recognized. These four cycles are the C1, C2, C3, C4 periods shown in the timing diagrams. DACKN always occurs in the C4 time and occurs approximately 18 ns after the rising edge of C4.

Addressing of the various functions of the QUART is through the address bus A(7:0). T o maintain upward compatibility with the SC28L/C198 Octart the 8 bit address is still defined as such. However A(6) is NOT used and is internally connected to Vss (ground). The pin is, therefore, not included in the pin diagram. The address space is controlled by A(5:0) and A(7). A[7], in a general sense, is used to separate the data portion of the circuit from the control portion.

Asynchronous bus cycle

The asynchronous mode requires one bus cycle of the chip select (CEN) for each read or write to the chip. No more action will occur on the bus after the C4 time until CEN is returned high.

Synchronous bus cycle

In the synchronous mode a read or write will be done every four cycles of the Sclk. CEN does not require cycling but must remain low to keep the synchronous accesses active. This provides a burst mode of access to the chip.

In both cases each read or write operation(s) will be completed in four (4) Sclk cycles. The difference in the two modes is only that the asynchronous mode will not begin another bus cycle if the CEN remains active after the four internal Sclk have completed. Internally the asynchronous cycle will terminate after the four periods of Sclk regardless of how long CEN is held active

In all cases the internal action will terminate at the withdrawal of CEN. Synchronous CEN cycles shorter than multiples of four Sclk cycles minus 1 Sclk and asynchronous CEN cycles shorter than four Sclk cycles may cause short read or write cycles and produce corrupted data transfers.

Timing Circuits

The timing block consists of a crystal oscillator, a fixed baud rate generator (BRG), a pair of programmable 16 bit register based counters. A buffer for the System Clock generates internal timing for processes not directly concerned with serial data flow.

Crystal Oscillator

The crystal oscillator operates directly from a crystal, tuned between

1.0 and 8.0 MHz, connected across the X1/CCLK and X2 inputs with a minimum of external components. BRG values listed for the clock select registers correspond to a 3.6864 MHz crystal frequency. Use of a 7.3728 MHz crystal will double the Communication Clock frequencies.

An external clock in the 100 KHz to 10 MHz frequency range may be connected to X1/CCLK. If an external clock is used instead of a crystal, X1/CCLK must be driven and X2 left floating. The X1 clock serves as the basic timing reference for the baud rate generator (BRG) and is available to the BRG timers. The X1 oscillator input

Philips Semiconductors Preliminary specification

SC28L194Quad UART for 3.3V and 5V supply voltage

1998 Sep 21

may be left unused if the internal BRG is not used and the X1 signal is not selected for any counter input.

Sclk - System Clock

A clock frequency, within the limits specified in the electrical specifications, must be supplied for the system clock Sclk. To ensure the proper operation of internal controllers, the Sclk frequency provided, must be strictly greater than twice the frequency of X1 crystal clock, or any external 1x data clock input. The system clock serves as the basic timing reference for the host interface and other internal circuits.

Baud Rate Generator BRG

The baud rate generator operates from the oscillator or external X1/CCLK clock input and is capable of generating 22 commonly used data communications baud rates ranging from 50 to 230.4K baud. These common rates may be doubled (up to 460.8 and 500K baud) when faster clocks are used on the X1/X2 clock inputs. (See Receiver and Transmitter Clock Select Register descriptions.) All of these are available simultaneously for use by any receiver or transmitter. The clock outputs from the BRG are at 16X the actual baud rate.

BRG Counters (Used for random baud rate generation)

The two BRG Timers are programmable 16 bit dividers that are used for generating miscellaneous clocks. These clocks may be used by any or all of the receivers and transmitters in the Octart or output on the general purpose output pin GPO.

Each timer unit has eight different clock sources available to it as described in the BRG Timer Control Register. (BRGTCR). Note that the timer run and stop controls are also contained in this register. The BRG Timers generate a symmetrical square wave whose half period is equal in time to the division of the selected BRG Timer clock source by the number loaded to the BRG Timer Reload Registers ( BRGTRU and BRGTRL). Thus, the output frequency will be the clock source frequency divided by twice the value loaded to the BRGTRU and BRGTRL registers. This is the result of counting down once for the high portion of the output wave and once for the low portion.

Whenever the these timers are selected via the receiver or transmitter Clock Select register their output will be configured as a 16x clock for the respective receiver or transmitter. Therefore one needs to program the timers to generate a clock 16 times faster than the data rate. The formula for calculating ’n’, the number loaded to the BRGTRU and BRGTRL registers, is shown below.

n 



BRG Timer Input frequency

2  16  desired baud rate



–1

Note: ’n’ may assume values of 0 and 1. In previous Philips data communications controllers these values were not allowed.

The BRG timer input frequency is controlled by the BRG Timer control register (BRGTCR)

The frequency generated from the above formula will be at a rate 16 times faster than the desired baud rate. The transmitter and receiver state machines include divide by 16 circuits which provide the final frequency and provide various timing edges used in the qualifying the serial data bit stream. Often this division will result in a non-integer value; 26.3 for example. One may only program integer numbers to a digital divider. There for 26 would be chosen. If 26.7

was the result of the division then 27 would be chosen. This gives a baud rate error of 0.3/26.3 or 0.3/26.7. which yields a percentage error of 1.14% or 1.12% respectively; well within the ability of the asynchronous mode of operation.

One should be cautious about the assumed benign effects of small errors since the other receiver or transmitter with which one is communicating may also have a small error in the precise baud rate. In a “clean” communications environment using one start bit, eight data bits and one stop bit the total difference allowed between the transmitter and receiver frequency is approximately 4.6%. Less than eight data bits will increase this percentage.

Channel Blocks

There are four channel blocks, each containing an I/O port control, a data format control, and a single full duplex UART channel consisting of a receiver and a transmitter with their associated 16 byte FIFOs. Each block has its own status register, interrupt status and interrupt mask registers and their interface to the interrupt arbitration system.

A highly programmable character recognition system is also included in each block. This system is used for the Xon/Xoff flow control and the multi-drop (”9 bit mode”) address character recognition. It may also be used for general purpose character recognition.

Four I/O pins are provided for each channel. These pins are configured individually to be inputs or outputs. As inputs they may be used to bring external data to the bus, as clocks for internal functions or external control signals. Each I/O pin has a “Change of State” detector. The change detectors are used to signal a change in the signal level at the pin (Either 0 to 1 or 1 to 0) The level change on these pins must be stable for 25 to 50 Us (two edges of the 38.4 KHz baud rate clock) before the detectors will signal a valid change. These are typically used for interface signals from modems to the QUART and from there to the host. See the description of the “UART channel” under detailed descriptions below.

Character Recognition

Character recognition is specific to each of the four UARTs. Three programmable characters are provided for the character recognition for each channel. The three are general purpose in nature and may be set to only cause an interrupt or to initiate some rather complex operations specific to “Multi-drop” address recognition or in-band Xon/Xoff flow control.

Character recognition is accomplished via CAM memory. The Content Addressable Memory continually examines the incoming data stream. Upon the recognition of a control character appropriate bits are set in the Xon/Xoff Interrupt Status Register (XISR) and Interrupt Status Register (ISR). The setting of these bit(s) will initiate any of the automatic sequences or and/or an interrupt that may have enabled via the MR0 register.

The characters of the recognition system are not controlled by the software or hardware reset. They do not have a pre-defined “reset value”. They may, however, be loaded by a “Gang White” or “Gang Load” command as described in the “Xon Xoff Characters” paragraph.

Note: Character recognition is further described in the

Minor Modes

of Operation.

Philips Semiconductors Preliminary specification

SC28L194Quad UART for 3.3V and 5V supply voltage

1998 Sep 21

Interrupt Control

The interrupt system determines when an interrupt should be asserted thorough an arbitration (or bidding) system. This arbitration is exercised over the several systems within the QUART that may generate an interrupt. These will be referred to as “interrupt sources”. There are 64 in all. In general the arbitration is based on the fill level of the receiver FIFO or the empty level of the transmitter FIFO. The FIFO levels are encoded into a four bit number which is concatenated to the channel number and source identification code. All of this is compared (via the bidding or arbitration process) to a user defined “threshold”. When ever a source exceeds the numerical value of the threshold the interrupt will be generated.

At the time of interrupt acknowledge (IACKN) the source which has the highest bid (not necessarily the source that caused the interrupt to be generated) will be captured in a “Current Interrupt Register” (CIR). This register will contain the complete definition of the interrupting source: channel, type of interrupt (receiver, transmitter, change of state, etc.), and FIFO fill level. The value of the bits in the CIR are used to drive the interrupt vector and global registers such that controlling processor may be steered directly to the proper service routine. A single read operation to the CIR provides all the information needed to qualify and quantify the most common interrupt sources.

The interrupt sources for each channel are listed below.

• Transmit FIFO empty level for each channel

• Receive FIFO Fill level for each channel

• Change in break received status for each channel

• Receiver with error for each channel

• Change of state on channel input pins

• Receiver Watch-dog Time out Event

• Xon/Xoff character recognition

• Address character recognition

Associated with the interrupt system are the interrupt mask register (IMR) and the interrupt status register (ISR) resident in each UART. Programming of the IMR selects which of the above sources may enter the arbitration process. Only the bidders in the ISR whose associated bit in the IMR is set to one (1) will be permitted to enter the arbitration process. The ISR can be read by the host CPU to determine all currently active interrupting conditions. For convenience the bits of the ISR may be masked by the bits of the IMR. Whether the ISR is read unmasked or masked is controlled by the setting of bit 6 in MR1.

Global Registers

The “Global Registers”, 19 in all, are driven by the interrupt system. These are not real hardware devices. They are defined by the content of the CIR (Current Interrupt Register) as a result of an interrupt arbitration. In other words they are indirect registers contained in the Current Interrupt Register (CIR) which the CIR uses to point to the source and context of the QUART sub circuit presently causing an interrupt. The principle purpose of these “registers” is improving the efficiency of the interrupt service.

The global registers and the CIR update procedure are further described in the

Interrupt Arbitration

system

I/O Ports

Each of the four UART blocks contains an I/O section of four ports. These ports function as a general purpose post section which services the particular UART they are associated with. External clocks are input and internal clocks are output through these ports.

Each of the four pins has a change of state detector which will signal a change (0 to 1 or 1 to 0) at the pin. The change of state detectors are individually enabled and may be set to cause and interrupt.

These pins will normally be used for flow control hand-shaking and the interface to a modem. Their control is further described in

I/O

Ports

section and the I/OPCR register.

DET AILED DESCRIPTIONS RECEIVER AND TRANSMITTER

The Quad UART has four full duplex asynchronous receiver/transmitters. The operating frequency for the receiver and transmitter can be selected independently from the baud rate generator, the counter , or from an external input. Registers that are central to basic full-duplex operation are the mode registers (MR0, MR1 and MR2), the clock select registers (RxCSR and TxCSR), the command register (CR), the status register (SR), the transmit holding register (TxFIFO), and the receive holding register (RxFIFO).

Transmitter

The transmitter accepts parallel data from the CPU and converts it to a serial bit stream on the TxD output pin. It automatically sends a start bit followed by the programmed number of data bits, an optional parity bit, and the programmed number of stop bits. The least significant bit is sent first. Each character is always “framed” by a single start bit and a stop bit that is 9/16 bit time or longer. If a new character is not available in the TxFIFO, the TxD output remains high, the “marking” position, and the TxEMT bit in the SR is set to 1.

Transmitter Status Bits

The SR (Status Register, one per UART) contains two bits that show the condition of the transmitter FIFO. These bits are TxRDY and TxEMT. TxRDY means the TxFIFO has space available for one or more bytes; TxEMT means The TxFIFO is completely empty and the last stop bit has been completed. TxEMT can not be active without TxRDY also being active. These two bits will go active upon initial enabling of the transmitter . They will extinguish on the disable or reset of the transmitter.

Transmission resumes and the TxEMT bit is cleared when the CPU loads at least one new character into the TxFIFO. The TxRDY will not extinguish until the TxFIFO is completely full. The TxRDY bit will always be active when the transmitter is enabled and there is at lease one open position in the TxFIFO.

The transmitter is disabled by reset or by a bit in the command register (CR). The transmitter must be explicitly enabled via the CR before transmission can begin. Note that characters cannot be loaded into the TxFIFO while the transmitter is disabled, hence it is necessary to enable the transmitter and then load the TxFIFO. It is not possible to load the TxFIFO and then enable the transmission.

Note the difference between transmitter disable and transmitter reset. The reset is affected by either software or hardware. When reset, the transmitter stops transmission immediately. The transmit data output will be driven high, transmitter status bits set to zero and any data remaining in the TxFIFO will be discarded.

The transmitter disable is controlled by the Tx Enable bit in the command register. Setting this bit to zero will not stop the transmitter immediately, but will allow it to complete any tasks presently underway. It is only when the last character in the TxFIFO and its stop bit(s) have been transmitted that the transmitter will go to its disabled state. While the transmitter enable/disable bit in the command register is at zero, the TxFIFO will not accept any additional characters.

Philips Semiconductors Preliminary specification

SC28L194Quad UART for 3.3V and 5V supply voltage

1998 Sep 21

Transmission of “Break”

Transmission of a break character is often needed as a synchronizing condition in a data stream. The “break” is defined as a start bit followed by all zero data bits by a zero parity bit (if parity is enabled) and a zero in the stop bit position. The forgoing is the minimum time to define a break. The transmitter can be forced to send a break (continuous low condition) by issuing a start break command via the CR. This command does not have any timing associated with it. Once issued the TxD output will be driven low (the spacing condition) and remain there until the host issues a command to “stop break” via the CR or the transmitter is issued a software or hardware reset. In normal operation the break is usually much longer than one character time.

1x and 16x modes, Transmitter

The transmitter clocking has two modes: 16x and 1x. Data is always sent at the 1x rate. However the logic of the transmitter may be operated with a clock that is 16 times faster than the data rate or at the same rate as the data i.e. 1x. All clocks selected internally for the transmitter (and the receiver) will be 16x clocks. Only when an external clock is selected may the transmitter logic and state machine operate in the 1x mode. The 1x or 16x clocking makes little difference in transmitter operation. (this is not true in the receiver) In the 16X clock mode the transmitter will recognize a byte in the TxFIFO within 1/16 to 2/16 bit time and thus begin transmission of the start bit; in the 1x mode this delay may be up to 2 bit times.

Transmitter FIFO

The transmitter buffer memory is a 16 byte by 8 bit ripple FIFO. The host writes characters to this buffer. This buffer accepts data only when the transmitter is enabled. The transmitter state machine reads them out in the order they were received and presents them to the transmitter shift register for serialization. The transmitter adds the required start, parity and stop bits as required the MR2 register programming. The start bit (always one bit time in length) is sent first followed by the least significant bit (LSB) to the most significant bit (MSB) of the character, the parity bit (if used) and the required stop bit(s).

Logic associated with the FIFO encodes the number of empty positions available in a four bit value.. This value is concatenated with the channel number and type interrupt type identifier and presented to the interrupt arbitration system. The encoding of the “positions empty” value is always 1 less than the number of available positions. Thus, an empty TxFIFO will bid with the value or 15; when full it will not bid at all; one position empty bids with the value 0. A full FIFO will not bid since a character written to it will be lost

Normally a TxFIFO will present a bid to the arbitration system when ever it has one or more empty positions. The MR0[5:4] allow the user to modify this characteristic so that bidding will not start until one of four levels (empty, 3/4 empty, 1/2 empty, not full) have been reached. As will be shown later this feature may be used to make slight improvements in the interrupt service efficiency . A similar system exists in the receiver.

Receiver

The receiver accepts serial data on the RxD pin, converts the serial input to parallel format, checks for start bit, stop bit, parity bit (if any),framing error or break condition, and presents the assembled character and its status condition to the CPU via the RxFIFO. Three status bits are FIFOed with each character received. The RxFIFO is really 11 bits wide; eight data and 3 status. Unused FIFO bits for character lengths less than 8 bits are set to zero. It is important to

note that receiver logic considers the entire message to be contained within the start bit to the stop bit. It is not aware that a message may contain many characters. The receiver returns to its idle mode at the end of each stop bit! As described below it immediately begins to search for another start bit which is normally, of course, immediately forth coming.

1x and 16x Mode, Receiver

The receiver operates in one of two modes; 1x and 16x. Of the two, the 16x is more robust and the preferred mode. Although the 1x mode may allow a faster data rate is does not provide for the alignment of the receiver 1x data clock to that of the transmitter. This strongly implies that the 1x clock of the remote transmitter is available to the receiver; the two devices are physically close to each other.

The 16x mode operates the receiver logic at a rate 16 times faster than the 1x data rate. This allows for validation of the start bit, validation of level changes at the receiver serial data input (RxD), and a stop bit length as short as 9/16 bit time. Of most importance in the 16x mode is the ability of the receiver logic to align the phase of the receiver 1x data clock to that of the transmitter with an accuracy of less than 1/16 bit time.

When the receiver is enabled ( via the CR register) it begins looking for a high to low (mark to space) transition on the RxD input pin. If a transition is detected, an internal counter running at 16 times the data rate is reset to zero. If the RxD remains low and is still low when the counter reaches a count of 7 the receiver will consider this a valid start bit and begin assembling the character. If the RxD input returns to a high state the receiver will reject the previous high to low (mark to space) transition on the RxD input pin. This action is the “validation” of the start bit and also establishes the phase of the receiver 1x clock to that of the transmitter The counter operating at 16x the data rate is the generator for the 1x data rate clock. With the phase of the receiver 1x clock aligned to the falling of the start bit (and thus aligned to the transmitter clock) AND with a valid start bit having been verified the receiver will continue receiving bits by sampling the RxD input on the rising edge of the 1x clock that is being generated by the above mentioned counter running 16 times the data rate. Since the falling edge of the 1x clock was aligned to falling edge of the start bit then the rising of the clock will be in the “center” of the bit cell.

This action will continue until a full character has been assembled. Parity, framing, and stop bit , and break status is then assembled and the character and its status bits are loaded to the RxFIFO At this point the receiver has finished its task for that character and will immediately begin the search for another start bit.

Receiver Status Bits

There are five (5) status bits that are evaluated with each byte (or character) received: received break, framing error, parity error, overrun error, and change of break. The first three are appended to each byte and stored in the RxFIFO. The last two are not necessarily related to the a byte being received or a byte that is in the RxFIFO. They are however developed by the receiver state machine.

The “received break” will always be associated with a zero byte in the RxFIFO. It means that zero character was a break character and not a zero data byte. The reception of a break condition will always set the “change of break” (see below) status bit in the Interrupt Status Register(ISR).

A framing error occurs when a non zero character was seen and that character has a zero in the stop bit position.

Philips Semiconductors Preliminary specification

SC28L194Quad UART for 3.3V and 5V supply voltage

1998 Sep 21

The parity error indicates that the receiver generated parity was not the same as that sent by the transmitter.

The overrun error occurs when the RxFIFO is full, the receiver shift register is full and another start bit is detected. At this moment the receiver has 17 valid characters and the start bit of the 18th has been seen. At this point the host has approximately 7/16 bit time to read a byte from the RxFIFO or the overrun condition will be set and the 18th character will overrun the 17th and the 19th the 18th and so on until an open position in the RxFIFO is seen. The meaning of the overrun is that data has been lost. Data in the RxFIFO remains valid. The receiver will begin placing characters in the RxFIFO as soon as a position becomes vacant.

Note: Precaution must be taken when reading an overrun FIFO. There will be 16 valid characters. Data will begin loading as soon as the first character is read. The 17

th.

character will have been received as valid but it will not be known how many characters were lost between the two characters of the 16

th.

and 17

th.

reads of the

RxFIFO The “Change of break” means that either a break has been detected

or that the break condition has been cleared. This bit is available in the ISR. The beginning of a break will be signaled by the break change bit being set in the ISR AND the received break bit being set in the SR. At the termination of the break condition only the change of break in the ISR will be set. After the break condition is detected the termination of the break will only be recognized when the RxD input has returned to the high state for two successive edges of the 1x clock; 1/2 to 1 bit time.

The receiver is disabled by reset or via CR commands. A disabled receiver will not interrupt the host CPU under any circumstance in the normal mode of operation. If the receiver is in the multi-drop or special mode, it will be partially enabled and thus may cause an interrupt. Refer to section on Wake-Up and minor modes and the register description for MR1 for more information.

Receiver FIFO

The receiver buffer memory is a 16 byte ripple FIFO with three status bits appended to each data byte. (The FIFO is then 16 11 bit “words”). The receiver state machine gathers the bits from the receiver shift register and the status bits from the receiver logic and writes the assembled byte and status bits to the RxFIFO. Logic associated with the FIFO encodes the number of filled positions for presentation to the interrupt arbitration system. The encoding is always 1 less than the number of filled positions. Thus, a full RxFIFO will bid with the value or 15; when empty it will not bit at all; one position occupied bids with the value 0. An empty FIFO will not bid since no character is available. Normally RxFIFO will present a bid to the arbitration system when ever it has one or more filled positions. The MR2[3:2 bits allow the user to modify this characteristic so that bidding will not start until one of four levels (one or more filled, 1/2 filled, 3/4 filled, full) have been reached. As will be shown later this feature may be used to make slight improvements in the interrupt service efficiency . A similar system exists in the transmitter.

RxFIFO Status: Status Reporting Modes

The description below applies to the upper three bits in the “Status Register” These three bits are not “in the status register”; They are part of the RxFIFO. The three status bits at the top of the RxFIFO are presented as the upper three bits of the status register included in each UART.

The error status of a character , as reported by a read of the SR (status register upper three bits) can be provided in two ways, as

programmed by the error mode control bit in the mode register: “Character mode” or the “Block Mode”. The block mode may be further modified (via a CR command) to set the status bits as the characters enter the FIFO or as they are read from the FIFO.

In the ’character’ mode, status is provided on a character by character basis as the characters are read from the RxFIFO: the “status” applies only to the character at the top of the RxFIFO - The next character to be read.

In the ’block’ mode, the status provided in the SR for these three bits is the logical OR of the status for all characters coming to the top of the RxFIFO, since the last reset error command was issued. In this mode each of the status bits stored in the RxFIFO are passed through a latch as they are sequentially read. If any of the characters has an error bit set then that latch will set and remain set until reset with an “Reset Error” command from the command register or a receiver reset. The purpose of this mode is indicating an error in the data block as opposed to an error in a character

The latch used in the block mode to indicate “problem data” is usually set as the characters are read out of the RxFIFO. Via a command in the CR the latch may be configured to set the latch as the characters are pushed (loaded to) the RxFIFO. This gives the advantage of indicating “problem data” 16 characters earlier.

In either mode, reading the SR does not affect the RxFIFO. The RxFIFO is ’popped’ only when the RxFIFO is read. Therefore, the SR should be read prior to reading the corresponding data character.

If the RxFIFO is full when a new character is received, that character is held in the receive shift register until a RxFIFO position is available. At this time there are 17 valid characters in the RxFIFO. If an additional character is received while this state exists, the contents of the RxFIFO are not affected: the character previously in the shift register is lost and the overrun error status bit, SR[4], will be set upon receipt of the start bit of the new (overrunning) character.

I/O Ports

Each of the four UARTs includes four I/O ports equipped with “change of state” detectors. The pins are individually programmable for an input only function or one of three output functions. These functions are controlled by the “I/O Port Configuration Register (I/OPCR)) They will normally be used for the RTSN-CTSN, DTR hardware signals, RxD or TxD input or output clocks or switch inputs as well as data out put from the I/OPIOR register.

It is important to note that the input circuits are always active. That is the signal on a port, whether it is derived from an internal or external source is always available to the internal circuits associated with an input on that port.

The “Change of State” (COS) detectors are sensitive to both a 1 to 0 or a 0 to 1 transition. The detectors are controlled by the internal

38.4 KHz baud rate and will signal a change when a transition has been stable for two rising edges of this clock. Thus a level on the I/O ports must be stable for 26 s to 52 s. Defining a port as an output will disable the COS detector at that port. The condition of the four I/O pins and their COS detectors is available at any time in the IPR (Input Port Register)

The control of data and COS enable for these ports is through the I/OPIOR register. This is a read/write register and gives individual control to the enabling of the change of state detectors and also to the level driven by I/O pins when programmed to drive the logic level written to the four lower bits of the I/OPIOR. A read of this register will indicate the data on the pin at the time of the read and the state of the enabled COS detectors.

Philips Semiconductors Preliminary specification

SC28L194Quad UART for 3.3V and 5V supply voltage

1998 Sep 21

General Purpose Pins

In addition to the I/O ports for each UART four other ports are provided which service the entire chip. Two are dedicated as inputs and two are as outputs. The Gin1 and Gin0 are the input pins; Gout0 and Gout1 the outputs. These ports are multiplexed to nearly every functional unit in the chip. See the registers which describe the multitude of connections available for these pins. The Gout0 and Gout1 pins are highly multiplexed outputs and are controlled by four (4) registers: GPOSR, GPOR, GPOC and GPOD. The Gin0 and Gin1 pins are available to the receivers and transmitters, BRG counters and the Gout0 and Gout1 pins.

Global Registers

GIBCR The byte count of the interrupting FIFO GICR Channel number of the interrupting channel GITR Type identification of interrupting channel GRxFIFO Pointer to the interrupting receiver FIFO GTxFIFO Pointer to the interrupting transmitter FIFO

A read of the GRxFIFO will give the content of the RxFIFO that presently has the highest bid value. The purpose of this system is to enhance the efficiency of the interrupt system. The global registers and the CIR update procedure are further described in the

Interrupt

Arbitration

system

Character Recognition

The character recognition circuits are basically designed to provide general purpose character recognition. Additional control logic has been added to allow for Xon/Xoff flow control and for recognition of the address character in the multi-drop or “wake-up” mode. This logic also allows for the generation of an interrupts in either the general purpose recognition mode or the specific conditions mentioned above.

Xon Xoff Characters

The programming of these characters is usually done individually. However a method has been provided to write to all of registers in one operation. There are “Gang Load” and a “Gang Write” commands provided in the channel A Command Register. When these commands are executed all registers are programmed with the same characters. The “write” command loads a used defined character; the ’load” command loads the standard Xon/Xoff characters. Xon is x’11; Xof f x’13’. Any enabling of the Xon/Xoff functions will use the contents of the Xon and Xoff character registers as the basis on which recognition is predicated.

Multi-drop or Wake-up or 9-bit Mode

This mode is used to address a particular UART among a group connected to the same serial data source. Normally it is accomplished by redefining the meaning of the parity bit such that it indicates a character as address or data. While this method is fully supported in the SC28L194 it also supports recognition of the character itself. Upon recognition of its address the receiver will be enabled and data pushed onto the RxFIFO.

Further the Address recognition has the ability, if so programmed, to disable (not reset) the receiver when an address is seen that is not recognized as its own. The particular features of “Auto Wake and Auto Doze” are described in the detail descriptions below.

Note: Care should be taken in the programming of the character recognition registers. Programming x’00, for example, may result in a break condition being recognized as a control character. This will be further complicated when binary data is being processed.

Character Stripping

The MR0 register provides for stripping the characters used for character recognition. Recall that the character recognition may be conditioned to control several aspects of the communication. However this system is first a character recognition system. The status of the various states of this system are reported in the XISR and ISR registers. The character stripping of this system allows for the removal of the specified control characters from the data stream: two for the Xon /Xoff and one for the Wake-up. Via control in the MR0 register these characters may be discarded (stripped) from the data stream when the recognition system “sees” them or they may be sent on the RxFIFO. Whether they are stripped or not the recognition will process them according to the action requested: flow control, Wake-up, interrupt generation, etc. Care should be exercised in programming the stripping option if noisy environments are encountered. If a normal character was corrupted to an Xoff character turned off the transmitter and it was then stripped, then the stripping action could make it difficult to determine the cause of transmitter stopping.

Interrupt Arbitration and IRQN Generation

Interrupt arbitration is the process used to determine that an interrupt request should be presented to the host. The arbitration is carried out between the “Interrupt Threshold” and the “sources” whose interrupt bidding is enabled by the IMR. The interrupt threshold is part of the ICR (Interrupt Control Register) and is a value programmed by the user. The “sources” present a value to the interrupt arbiter. That value is derived from four fields: the channel number, type of interrupt source, FIFO fill level, and programmable value. Only when one or more of these values exceeds the threshold value in the interrupt control register will the interrupt request (IRQN) be asserted.

Following assertion of the IRQN the host will either assert IACKN(Interrupt Acknowledge) or will use the command to “Update the CIR”. At the time either action is taken the CIR will capture the value of the source that is prevailing in the arbitration process. (Call this value the winning bid)

The value in the CIR is the central quantity that results from the arbitration. It contains the identity of the interrupting channel, the type of interrupt in that channel (RxD, TxD, COS etc.) the fill levels of the RxD or TxD FIFOs and , in the case of an RxD interrupt an indicator of error data or good data. It also drives the Global Registers associated with the interrupt. Most importantly it drives

the modification of the Interrupt Vector.

The arbitration process is driven by the Sclk. It scans the 10 bits of the arbitration bus at the Sclk rate developing a value for the CIR every 22 Sclk cycles. New arbitration values presented to the arbitration block during an arbitration cycle will be evaluated in the next arbitration cycle.

For sources other than receiver and transmitters the user may set the high order bits of an interrupt source’s bid value, thus tailoring the relative priority of the interrupt sources. The priority of the receivers and transmitters is controlled by the fill level of their respective FIFOs. The more filled spaces in the RxFIFO the higher the bid value; the more empty spaces in the TxFIFO the higher its priority. Channels whose programmable high order bits are set will

Philips Semiconductors Preliminary specification

SC28L194Quad UART for 3.3V and 5V supply voltage

1998 Sep 21

be given interrupt priority higher than those with zeros in their high order bits , thus allowing increased flexibility. The transmitter and receiver bid values contain the character counts of the associated FIFOs as high order bits in the bid value. Thus, as a receiver’s RxFIFO fills, it bids with a progressively higher priority for interrupt service. Similarly, as empty space in a transmitter’s TxFIFO increases, its interrupt arbitration priority increases.

IACKN Cycle, Update CIR

When the host CPU responds to the interrupt, it will usually assert the IACKN signal low. This will cause the QUART to generate an IACKN cycle in which the condition of the interrupting device is determined. When IACKN asserts, the last valid interrupt number is captured in the CIR. The value captured presents most of the important details of the highest priority interrupt at the moment the IACKN (or the “Update CIR” command) was asserted.

The Quad UART will respond to the IACKN cycle with an interrupt vector. The interrupt vector may be a fixed value, the content of the Interrupt Vector Register, or ,when “Interrupt Vector Modification is enabled via ICR, it may contain codes for the interrupt type and/or interrupting channel. This allows the interrupt vector to steer the interrupt service directly to the proper service routine. The interrupt value captured in the CIR remains until another IACKN cycle occurs or until an “Update CIR” command is given to the QUART. The interrupting channel and interrupt type fields of the CIR set the current “interrupt context” of the QUART. The channel component of the interrupt context allows the use of Global Interrupt Information registers that appear at fixed positions in the register address map. For example, a read of the Global RxFIFO will read the channel B RxFIFO if the CIR interrupt context is channel b receiver. At another time read of the GRxFIFO may read the channel D RxFIFO (CIR holds a channel D receiver interrupt) and so on. Global registers exist to facilitate qualifying the interrupt parameters and for writing to and reading from FIFOs without explicitly addressing them.

The CIR will load with x’00 if IACKN or Update CIR is asserted when the arbitration circuit is NOT asserting an interrupt. In this condition there is no arbitration value that exceeds the threshold value.

Polling

Many users prefer polled to interrupt driven service where there are a large number of fast data channels and/or the host CPU’s other interrupt overhead is low. The Quad UART is functional in this environment.

The most efficient method of polling is the use of the “update CIR” command (with the interrupt threshold set to zero) followed by a read of the CIR. This dummy write cycle will perform the same CIR capture function that an IACKN falling edge would accomplish in an interrupt driven system. A subsequent read of the CIR, at the same address, will give information about an interrupt, if any. If the CIR contains 0s, no interrupt is awaiting service. If the value is non-zero, the fields of the CIR may be decoded for type, channel and character count information. Optionally , the global interrupt registers may be read for particular information about the interrupt status or use of the global RxD and TxD registers for data transfer as appropriate. The interrupt context will remain in the CIR until another update CIR command or an IACKN cycle is initiated by the host

CPU occurs. The CIR loads with x’00 if Update CIR is asserted when the arbitration circuit has NOT detected arbitration value that exceeds the threshold value.

Traditional methods of polling status registers may also be used. They of course are less efficient but give the most variable and quickest method of changing the order in which interrupt sources are evaluated and interrogated.

Enabling and Activating Interrupt Sources

An interrupt source becomes enabled when its interrupt capability is set by writing to the Interrupt Mask Register, IMR. An interrupt source can never generate an IRQN or have its “bid” or interrupt number appear in the CIR unless the source has been enabled by the appropriate bit in an IMR.

An interrupt source is active if it is presenting its bid to the interrupt arbiter for evaluation. Most sources have simple activation requirements. The watch-dog timer, break received, Xon/Xoff or Address Recognition and change of state interrupts become active when the associated events occur and the arbitration value generated thereby exceeds the threshold value programmed in the ICR (Interrupt Control Register).

The transmitter and receiver functions have additional controls to modify the condition upon which the initiation of interrupt “bidding” begins: the TxINT and RxINT fields of the MR0 and MR2 registers. These fields can be used to start bidding or arbitration when the RxFIFO is not empty, 50% full, 75% full or 100% full. For the transmitter it is not full, 50% empty, 75% empty and empty.

Example: To increase the probability of transferring the contents of a nearly full RxFIFO, do not allow it to start bidding until 50% or 75% full. This will prevent its relatively high priority from winning the arbitration process at low fill levels. A high threshold level could accomplish the same thing, but may also mask out low priority interrupt sources that must be serviced. Note that for fast channels and/or long interrupt latency times using this feature should be used with caution since it reduces the time the host CPU has to respond to the interrupt request before receiver overrun occurs.

Setting Interrupt Priorities

The bid or interrupt number presented to the interrupt arbiter is composed of character counts, channel codes, fixed and programmable bit fields. The interrupt values are generated for various interrupt sources as shown in the table below: The value represented by the bits 9 to 3 in the table below are compared against the value represented by the “Threshold. The “Threshold” ,bits 6 to 0 of the ICR (Interrupt Control Register), is aligned such that bit 6 of the threshold is compared to bit 9 of the interrupt value generated by any of the sources. When ever the value of the interrupt source is greater than the threshold the interrupt will be generated.

The channel number arbitrates only against other channels. The threshold is not used for the channel arbitration. This results in channel D having the highest arbitration number. The decreasing order is D-to-A. If all other parts of an arbitration are equal then the channel number will determine which channel will dominate in the arbitration process.

Philips Semiconductors Preliminary specification

SC28L194Quad UART for 3.3V and 5V supply voltage

1998 Sep 21

T able 1. Interrupt Arbitration Priority

Type

Bits 2:0

Receiver w/o error

RxFIFO Byte Count -1

Channel No

Receiver w/ error

RxFIFO Byte Count -1

Channel No

Transmitter

TxFIFO Byte Count -1

Channel No

Change of Break

Programmed Field

Channel No

Change of State

Programmed Field

Channel No

Xon/Xoff

Programmed Field

Channel No

Address Recognition

Programmed Field

Channel No

Receiver Watch-dog

RxFIFO Byte Count -1

As RxFIFO Above

Channel No

Threshold

Bits 6:0 of Interrupt Control Register

000

Note several characteristics of the above table in bits 6:3. These bits contain the identification of the bidding source as indicated below:

x001 Receiver without error x101 Receiver with error xx00 Transmitter 0010 Change of Break 0110 Change of State on I/O Ports 0111 Xon/Xoff Event 0011 Address Recognition

The codes form bits 6:3 drive part of the interrupt vector modification and the Global Interrupt Type Register. The codes are unique to each source type and Identify them completely. The channel numbering progresses from “a” to “d” as the binary numbers 000 to 011 and identify the interrupting channel uniquely. As the channels arbitrate “d” will have the highest bidding value and “a” the lowest

Note that the transmitter byte count is off-set from that of the receiver by one bit. This is to give the receiver more authority in the arbitration since and over-run receiver corrupts the message but an under-run transmitter is not harmful. This puts some constraints on how the threshold value is selected. If a threshold is chosen that has its MSB set to one then a transmitter can never generate an interrupt! Of course the counter point to this is the desire to set the interrupt threshold high so interrupts occur only when a maximum or near maximum number of characters may be transferred.

To give some control over this dilemma control bits have been provided in the MR0 and MR2 registers of each channel to individually control when a receiver or transmitter may interrupt. The use of these bits will prevent a receiver or a transmitter from entering the arbitration process even though its FIFO fill level is above that indicated by the threshold value set. The bits in the MR0 and MR2 register are named TxINT (MR0[5:4]) and RxINT (MR2[3:2])

Watch-Dog Timer

The watch-dog is included in the table above to show that it affects the arbitration. It does not have an identity of its own. A barking watch-dog will prevent any other source type from entering the arbitration process except enabled receivers. The threshold is effectively set to zero when any watch-dog times out. The receivers arbitrate among them selves and the one with the highest fill level will win the process. Note that the receiver wining the bid may not be the one that caused the watch-dog to bark.

The fields labeled “Programmed Field” are the contents of the Bidding Control Registers, BCRs, for these sources. Setting these bits to high values can elevate the interrupt importance of the sources they represent to values almost as high as a full receiver. For example a COS event may be very important when it represents

the DSR (Data Set Ready) signal from the modem. In this case its arbitration value should be high. Once the DSR is recognized then its arbitration value could be reduced or turned off.

There is a single arbiter interrupt number that is not associated with any of the UART channels. It is the “Threshold V alue” and is comprised of 7 bits from the Interrupt Control Register, ICR, and three zeros in the channel field. It is only when one or more of the

enabled interrupt sources generates a arbitration value larger than the threshold value that the IRQN will be asserted. When

the threshold bidding value is larger than any other bidding value then the IRQN will be withdrawn. In this condition, when nothing is interrupting, the CIR will be loaded with zeros if the IRQN is asserted or “Update CIR” command is issued. Because the channels are numbered from 0 to 3 ( A to D) channel 3 will win the bid when all other parts of the bid are equal.

Note: Based on the xx00 coding for the transmitter (as shown in Table 1 above), a transmitter will not win a bid in the situation where the Count Field = 0 unless the threshold value is equal to or less than 0000011. A single empty slot is left in the TxFIFO, or a single filled slot in the RxFIFO will bid with a byte count value of zero.

MODES OF OPERATION Major Modes

Four major modes of operation (normal, auto echo, local loop back and remote loop back) are provided and are controlled by MR2[7:6]. Three of these may be considered diagnostic. See the MR2 register description.

The normal mode is the usual mode for data I/O operation. Most reception and transmission will use the normal mode.

In the auto echo mode, the transmitter automatically re-transmits any character captured by the channel’s receiver. The receiver 1x clock is used for the transmitter. This mode returns the received data back to the sending station one bit time delayed from its departure. Receiver to host communication is normal. Host to transmitter communication has no meaning.

In the local loop back mode (used for diagnostic purposes) the transmitter is internally connected to the receiver input. The transmitter 1x clock used for the receiver. The RxD input pin is ignored and the transmitter TxD output pin is held high. This configuration allows the transmitter to send data to the receiver without any external parameters to affect the transmission of data. All status bits, interrupt conditions and processor interface operate normally . It is recommended that this mode be used when initially verifying processor to UART interface. The

Philips Semiconductors Preliminary specification

SC28L194Quad UART for 3.3V and 5V supply voltage

1998 Sep 21

communication between the transmitter and receiver is entirely within the UART - it is essentially “talking to itself”.

The remote loop back mode (also used for diagnostic purposes) is similar to auto echo except that the characters are not sent to the local CPU, nor is the receiver status updated. The received data is sent directly to the transmitter where it is sent out on the TxD output. The received data is not sent to the receive FIFO and hence the host will not normally be participating in any diagnostics.

Minor Modes

The minor modes provide additional features within the major modes. In general the minor modes provide a reduction in the control burden and a less stringent interrupt latency time for the host processor. These modes could be invoked in all of the major modes.. However it may not be reasonable in many situations.

Watch-dog Timer Time-out Mode

Each receiver in the Quad UART is equipped with a watch-dog timer that is enabled by the “Watch-dog Timer Enable Register (WTER). The watch-dog “barks” (times out) if 64 counts of the receiver clock (64 bit times) elapse with no RxFIFO activity. RxFIFO events are a read of the RxFIFO or GRxFIFO, or the push of a received character into the RxFIFO. The timer resets when the (G)RxFIFO is read or if another character is pushed into the RxFIFO. The receiver watch-dog timer is included to allow detection of the very last character(s) of a received message that may be waiting in the RxFIFO, but are too few in number to successfully initiate an interrupt. The watch-dog timer is enabled for counting if the channel’s bit in the Watch Dog Timer Control Register (WDTCR) is set. Note: a read of the GRxFIFO will reset the watch-dog timer of only the channel specified in the current interrupt context. Other watch-dogs are unaffected.

The watch-dog timer may generate an input to the interrupt arbiter if IMR[6] is set. The status of the Watch-dog timer can be seen as Bit 6 of the Interrupt Status Register, ISR[6]. When a W atch-dog timer that is programmed to generate an interrupt times out it enters the arbitration process. It will then only allow receivers to enter the enter the arbitration. All other sources are bidding sources are disabled. The receivers arbitrate only amongst themselves.. The receiver only interrupt mode of the interrupt arbiter continues until the last watch-dog timer event has been serviced. While in the receiver only interrupt mode, the control of the interrupt threshold level is also disabled. The receivers arbitrate only between themselves. The threshold value is ignored. The receiver with the most FIFO positions filled will win the bid. Hence the user need not reduce the bidding threshold level in the ICR to see the interrupt from a nearly empty RxFIFO that may have caused the watch-dog time-out.

Note: When any watch-dog times our only the receivers arbitrate. There is no increase in the probability of receiver being serviced causing the overrun of another receiver since they will still have priority based upon received character count.

The interrupt will be cleared automatically upon the push of the next character received or when the RxFIFO or GRxFIFO is read. The ICR is unaffected by the watch-dog time-out interrupt and normal interrupt threshold level sensing resumes after the last watch-dog timer event has been processed. If other interrupt sources are active, the IRQN pin may remain low.

Wake-up Mode

The SC28L194 provides two modes of this common asynchronous “party line” protocol: the new automatic mode with 3 sub modes and the default Host operated mode. The automatic mode has several sub modes (see below). In the full automatic the internal state machine devoted to this function will handle all operations

associated with address recognition, data handling, receiver enables and disables. In both modes the meaning of the parity bit is changed. It is often referred to as the A/D bit or the address/data bit. It is used to indicate whether the byte presently in the receiver shift register is an “address” byte or a “data” byte. “1” usually means address; “0” data.

Its purpose is to allow several receivers connected to the same data source to be individually addressed. Of course addressing could be by group also. Normally the “Master” would send an address byte to all receivers “listening” The receiver would then recognize its address and enable itself receiving the following data stream. Upon receipt of an address not its own it would then disable itself. As descried below appropriate status bits are available to describe the operation.

Enabling the Wake-up mode

This mode is selected by programming bits MR1[4:3] to ’11’. The sub modes are controlled by bits 6, 1, 0 in the MR0 register. Bit 6 controls the loading of the address byte to the RxFIFO and MR0[1:0] determines the sub mode as shown in the following table.

MR0[1:0] = 00 Normal Wake-up Mode (default). Host controls

operation via interrupts and commands written to the command register (CR).

MR0[1:0] = 01 Auto wake. Enable receiver on address

recognition for this station. Upon recognition of its assigned address, in the Auto Wake mode, the local receiver will be enabled and normal receiver communications with the host will be established.

MR0[1:0] = 10 Auto Doze. Disable receiver on address

recognition, not for this station. Upon recognition of an address character that is not its own, in the Auto Doze mode, the receiver will be disabled and the address just received either discarded or pushed to the RxFIFO depending on the programming of MR0[6].

MR0[1:0] = 11 Auto wake and doze. Both modes above. The

programming of MR0[1:0] to 11 will enable both the auto wake and auto doze features.

The enabling of the wake-up mode executes a partial enabling of the receiver state machine. Even though the receiver has been reset the Wake-up mode will over ride the disable and reset condition.

Normal Wake-up (The default configuration)

In the default configuration for this mode of operation, a ’master’ station transmits an address character followed by data characters for the addressed ’slave’ station. The slave stations, whose receivers are normally disabled (not reset), examine the received data stream and interrupts the CPU (by setting RxRDY) only upon receipt of an address character. The CPU (host) compares the received address to its station address and enables the receiver if it wishes to receive the subsequent data characters. Upon receipt of another address character, the CPU may disable the receiver to initiate the process again.

A transmitted character consists of a start bit, the programmed number of data bits, an address/data (A/D) bit, and the programmed number of stop bits. The polarity of the transmitted A/D bit is selected by the CPU by programming bit MR1[2]. MR1[2] = 0 transmits a zero in the A/D bit position which identifies the corresponding data bits as data. MR1[2] = 1 transmits a one in the A/D bit position which identifies the corresponding data bits as an address. The CPU should program the mode register prior to loading the corresponding data bytes into the TxFIFO.

Philips Semiconductors Preliminary specification

SC28L194Quad UART for 3.3V and 5V supply voltage

1998 Sep 21

While in this mode, the receiver continuously looks at the received data stream, whether it is enabled or disabled. If disabled, it sets the RxRDY status bit and loads the character into the RxFIFO if the received A/D bit is a one, but discards the received character if the received A/D bit is a zero. If the receiver is enabled, all received characters are transferred to the CPU via the RxFIFO. In either case, the data bits are loaded into the data FIFO while the A/D bit is loaded into the status FIFO position normally used for parity error (SR[5]). Framing error, overrun error, and break detect operate normally whether or not the receiver is enabled.

Automatic Operation, Wake-up and Doze

The automatic configuration for this mode uses onboard comparators to examine incoming address characters. Each UART channel may be assigned a unique address character. See the address register map and the description of the Address Recognition Character Register (ARCR). The device may be programmed to automatically awaken a sleeping receiver and/or disable an active receiver based upon address characters received. The operation of the basic receiver is the same as described above for the default mode of wake-up operation except that the CPU need not be interrupted to make a change in the receiver status.

Three bits in the Mode Register 0, (MR0), control the address recognition operation. MR0[6] controls the RxFIFO operation of the received character; MR0[1:0] controls the Wake-up mode options. If MR0[6] is set the address character will be pushed onto the RxFIFO, otherwise the character will be discarded. (The charter is stripped from the data stream) The MR0[1:0] bits set the options as follows: A b’00 in this field, the default or power-on condition, puts the device in the default (CPU controlled) Wake-up mode of operation as described above. The auto-wake mode, enabled if MR0[0] is set, will cause the dedicated comparators to examine each address character presented by the receiver. If the received character matches the reference character in ARCR, the receiver will be enabled and all subsequent characters will be FIFOed until another address event occurs or the host CPU disables the receiver explicitly. The auto doze mode, enabled if MR0[1] is set, will automatically disable the receiver if an address is received that does not match the reference character in the ARCR.

The UART channel can present the address recognition event to the interrupt arbiter for IRQN generation. The IRQN generation may be masked by setting bit 5 of the Interrupt Mask Register, IMR. The bid level of an address recognition event is controlled by the Bidding Control Register, BCRA, of the channel.

Note: To ensure proper operation, the host CPU must clear any pending Address Recognition interrupt before enabling a disabled receiver operating in the Special or Wake-up mode. This may be accomplished via the CR commands (or a read of the XISR) to clear the Address Interrupt or by resetting the receiver.

Xon/Xoff Operation Receiver Mode

Since the receiving FIFO resources in the Quad UART are limited, some means of controlling a remote transmitter is desirable in order to lessen the probability of receiver overrun. The Quad UART provides two methods of controlling the data flow. A hardware assisted means of accomplishing control, the so-called out-of-band flow control, and an in-band flow control method.

The out-of-band flow control is implemented through the CTSN-RTSN signaling via the I/O ports. The operation of these hardware handshake signals is described in the receiver and transmitter discussions.

In-band flow control is a protocol for controlling a remote transmitter by embedding special characters within the message stream, itself. Two characters, Xon and Xoff, which do not represent normal printable characters take on flow control definitions when the Xon/Xoff capability is enabled. Flow control characters received may be used to gate the channel transmitter on and off. This activity is referred to as Auto-transmitter mode. To protect the channel receiver from overrun, fixed fill levels (hardware set at 12 characters) of the RxFIFO may be employed to automatically insert Xon/Xoff characters in the transmitter’s data stream. This mode of operation is referred to as auto-receiver mode. Commands issued by the host CPU via the CR can simulate all these conditions.

Auto-Transmitter Mode

When a channel receiver pushes an Xoff character into the RxFIFO, the channel transmitter will finish transmission of the current character and then stop transmitting. A transmitter so idled can be restarted by the receipt of an Xon character by the receiver, or by a hardware or software reset. The last option results in the loss of the un-transmitted contents of the TxFIFO. When operating in this mode the Command Register commands for the transmitter are not effective.

While idle data may be written to the TxFIFO and it continues to present its fill level to the interrupt arbiter and maintains the integrity of its status registers.

Use of ’00’ as an Xon/Xoff character is complicated by the Receiver break operation which pushes a ’00’ character on the RxFIFO. The Xon/Xoff character detectors do not discriminate this case from an Xon/Xoff character received through the RxD pin.

Note: To be recognized as an Xon or Xoff character, the receiver must have room in the RxFIFO to accommodate the character. An Xon/Xoff character that is received resulting in a receiver overrun does not effect the transmitter nor is it pushed into the RxFIFO, regardless of the state of the Xon/Xoff transparency bit, MR0(7).

Note: Xon /Xoff Characters

The Xon/Xoff characters with errors will be accepted as valid. The user has the option sending or not sending these characters to the FIFO. Error bits associated with Xon/Xoff will be stored normally to the receiver FIFO.

The channel’s transmitter may be programmed to automatically transmit an Xoff character without host CPU intervention when the RxFIFO fill level exceeds a fixed limit (12). In this mode, it will conversely transmit an Xon character when the RxFIFO level drops below a second fixed limit (8). A character from the TxFIFO that has been loaded into the TxD shift register will continue to transmit. Character(s) in the TxFIFO that have not been popped are unaffected by the Xon or Xoff transmission. They will be transmitted after the Xon/Xoff activity concludes.

If the fill level condition that initiates Xon activity negates before the flow control character can begin transmission, the transmission of the flow control character will not occur, i.e. either of the following sequences may be transmitted depending on the timing of the FIFO level changes with respect to the normal character times:

Character Xoff Xon Character Character Character

Hardware keeps track of Xoff characters sent that are not rescinded by an Xon. This logic is reset by writing MR0(3) to ’0’. If the user drops out of Auto-receiver mode while the XISR shows Xon as the last character sent, the Xon/Xoff logic will not automatically send the negating Xon.

Philips Semiconductors Preliminary specification

SC28L194Quad UART for 3.3V and 5V supply voltage

1998 Sep 21

Host mode

When neither the auto-receiver nor auto-transmitter modes are set, the Xon/Xoff logic is operating in the host mode. In host mode, all activity of the Xon/Xoff logic is initiated by commands to the CRx command forces the transmitter to disable exactly as though an Xoff character had been received by the RxFIFO. The transmitter will remain disabled until the chip is reset or the CR(7:3) = 10110 (Xof f resume) command is given. In particular, reception of an Xon or disabling or re-enabling the transmitter will NOT cause resumption of transmission. Redundant CRTX-- commands, i.e. CRTXon CRTXon, are harmless, although they waste time. A CRTXon may be used to cancel a CRTXoff (and vice versa) but both may be transmitted depending on the timing with the transmit state machine. The kill CRTX command can be used to cleanly terminate any CRTX commands pending with the minimum impact on the transmitter.

Note: In no case will an Xon/Xoff character transmission be aborted. Once the character is loaded into the TX Shift Register, transmission continues until completion or a chip reset is encountered.

The kill CRTX command has no effect in either of the Auto modes.

Mode Control

Xon/Xoff mode control is accomplished via the MR0. Bits 3 and 2 reset to zero resulting in all Xon/Xoff processing being disabled. If MR0[2] is set, the transmitter may be gated by Xon/Xoff characters received. If MR0[3] is set, the transmitter will transmit Xon and Xoff when triggered by attainment of fixed fill levels in the channel RxFIFO. The MR0[7] bit also has an Xon/Xoff function control. If this bit is set, a received Xon or Xoff character is not pushed into the RxFIFO. If cleared, the power-on and reset default, the received Xon or Xoff character is pushed onto the RxFIFO for examination by the host CPU. The MR0(7) function operates regardless of the value in MR0(3:2)

Xon/Xoff Interrupts

The Xon/Xoff logic generates interrupts only in response to recognizing either of the characters in the XonCR or XoffCR (Xon or Xoff Character Registers). The transmitter activity initiated by the Xon/Xoff logic or any CR command does not generate an interrupt.

The character comparators operate regardless of the value in MR0(3:2). Hence the comparators may be used as general purpose character detectors by setting MR0(3:2)=’00’ and enabling the Xon/Xoff interrupt in the IMR.

The Quad UART can present the Xon/Xoff recognition event to the interrupt arbiter for IRQN generation. The IRQN generation may be masked by setting bit 4 of the Interrupt Mask Register, IMR. The bid level of an Xon/Xoff recognition event is controlled by the Bidding Control Register X, BCRX, of the channel. The interrupt status can be examined in ISR[4]. If cleared, no Xon/Xoff recognition event is interrupting. If set, an Xon or Xoff recognition event has been detected. The X Interrupt Status Register, XISR, can be read for details of the interrupt and to examine other, non-interrupting, status of the Xon/Xoff logic. Refer to the XISR in the Register Descriptions.

The character recognition function and the associated interrupt generation is disabled on hardware or software reset.

The operation of the Quad UART is programmed by writing control words into the appropriate registers. Operational feedback is provided via status registers which can be read by the host CPU. The Quad UART addressing is loosely divided, by the address bit A(7), into two parts:

1. That part which is concerned with the configuration of the chip interface and communication modes.

This part controls the elements of host interface setup, interrupt arbitration, I/O Port Configuration that part of the UART channel definitions that do not change in normal data handling. This section is listed in the “Register Map, Control”.

2. That part concerned with the transmission and reception of the bit streams.

This part concerns the data status, FIFO fill levels, data error conditions, channel status, data flow control (hand shaking). This section is listed in the “Register Map, Data”.

Philips Semiconductors Preliminary specification

SC28L194Quad UART for 3.3V and 5V supply voltage

1998 Sep 21

Table 2. GCCR - Global Configuration Control Register

THIS IS A VERY IMPORTANT REGISTER! IT SHOULD BE THE FIRST REGISTER ADDRESSED DURING INITIALIZATION. This register

has two addresses: x‘0F and x‘8F. The Global Configuration Control Register (GCCR) sets the type of bus cycle, interrupt vector modification and the power-up or -down mode.

Bit 7

Bit 6

Bit 5:3

Bit 2:1

Bit 0

Reserved

Sync bus cycles

Reserved

IVC, Interrupt Vector Control

Power Down Mode

ÁÁÁÁ

Reserved Must be set to 0

БББББ

0 - async cycles 1 - Sync, non-pipe-lined cycle

ÁÁÁ

Reserved Set to 0

ББББББББББ

00 - no interrupt vector 01 - IVR 10 - IVR + channel code 11 - IVR + interrupt type + channel code

ББББББ

0 - Device enabled 1 - Power down

GCCR(7): This bit is reserved for future versions of this device. If not set to zero most internal addressing will be disabled!

GCCR(6): Bus cycle selection Controls the operation of the host interface logic. If reset, the power on/reset default, the host interface can accommodate arbitrarily long bus I/O cycles. If the bit is set, the Quad UART expects four Sclk cycle bus I/O operations similar to those produced by an i80386 processor in non-pipelined mode. The major differences in these modes are observed in the DACKN pin function. In Sync mode, no negation of CEN is required between cycles.

GCCR(2:1): Interrupt vector configuration The IVC field controls if and how the assertion of IACKN (the interrupt acknowledge pin) will form the interrupt vector for the Quad UART. If b’00, no vector will be presented during an IACKN cycle. The bus will be driven high (xFF). If the field contains a b’01, the contents of the IVR, Interrupt Vector Register, will be presented as the interrupt vector without modification. If IVC = b’10, the channel code will replace the 3 LSBs of the IVR; if IVC = b’11 then a modified interrupt type and channel code replace the 5 LSBs of the IVR.

Note: The modified type field IVR(4:3) is:

10 Receiver w/o error 11 Receiver with error 01 Transmitter 00 All remaining sources

GCCR(0): Power down control Controls the power down function. During power down the internal oscillator is disabled, interrupt arbitration and all data

transmission/reception activities cease, and all processing for input change detection, BRG counter/timers and Address/Xon./Xoff recognition is disabled.

Note: For maximum power savings it is recommended that all switching inputs be stopped and all input voltage levels be within 0.5 volt of the Vcc and Vss power supply levels.

To switch from the asynchronous to the synchronous bus cycle mode, a single write operation to the GCCR, terminated by a negation of the CEN pin, is required. This cycle may be 4 cycles long if the setup time of the CEN edge to Sclk can be guaranteed. The host CPU must ensure that a minimum of two Sclk cycles elapse before the initiation of the next (synchronous) bus cycle(s).

A hardware or software reset is recommended for the unlikely requirement of returning to the asynchronous bus cycling mode.

MR - Mode Registers

The user must exercise caution when changing the mode of running receivers, transmitters or BRG counter/timers. The selected mode will be activated immediately upon selection, even if this occurs during the reception or transmission of a character. It is also possible to disrupt internal controllers by changing modes at critical times, thus rendering later transmission or reception faulty or impossible. An exception to this policy is switching from auto-echo or remote loop back modes to normal mode. If the deselection occurs just after the receiver has sampled the stop bit (in most cases indicated by the assertion of the channel’s RxRDY bit) and the transmitter is enabled, the transmitter will remain in auto-echo mode until the end of the transmission of the stop bit.

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