Philips SC16C2550 Technical data

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1. Description

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and infrared (IrDA) encoder/decoder

Rev. 03 — 19 June 2003 Product data

The SC16C2550 is a 2 channel Universal Asynchronous Receiver and Transmitter (UART) used for serial data communications. Its principal function is to convert parallel data into serial data and vice versa. The UART can handle serial data rates up to 5 Mbits/s.

The SC16C2550 is pin compatible with the ST16C2550. It will power-up to be functionally equivalent to the 16C2450. The SC16C2550 provides enhanced UART functions with 16-byte FIFOs, modemcontrol interface, DMA mode data transfer. The DMA mode data transfer is controlled by the FIFO trigger levels and the TXRDY and RXRDY signals. On-board status registers provide the user with error indications and operational status. System interrupts and modem control features may be tailored by software to meet speciﬁc user requirements. An internal loop-back capability allows on-board diagnostics. Independent programmable baud rate generators are provided to select transmit and receive baud rates.

2. Features

The SC16C2550 operates at 5 V, 3.3 V and 2.5 V and the Industrial temperature range, and is available in plastic PLCC44, LQFP48 and DIP40 packages.

■ 2 channel UART ■ 5 V, 3.3 V and 2.5 V operation ■ Industrial temperature range ■ Pin and functionally compatible to 16C2450 and software compatible with

INS8250, SC16C550

■ Up to 5 Mbits/s data rate at 5 V and 3.3 V, and 3 Mbits/s at 2.5 V ■ 16 byte transmit FIFO to reduce the bandwidth requirement of the external CPU ■ 16 byte receive FIFO with error ﬂags to reduce the bandwidth requirement of the

external CPU

■ Independent transmit and receive UART control ■ Four selectable Receive FIFO interrupt trigger levels ■ Automatic software/hardware ﬂow control ■ Programmable Xon/Xoff characters ■ Software selectable Baud Rate Generator ■ Sleep mode ■ Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun

Break)

■ Transmit, Receive, Line Status, and Data Set interrupts independently controlled

Philips Semiconductors

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

■ Fully programmable character formatting:

◆ 5-, 6-, 7-, or 8-bit characters

◆ Even-, Odd-, or No-Parity formats

◆ 1-, 11⁄2-, or 2-stop bit

◆ Baud generation (DC to 1.5 Mbit/s) ■ False start-bit detection ■ Complete status reporting capabilities ■ 3-State output TTL drive capabilities for bi-directional data bus and control bus ■ Line Break generation and detection ■ Internal diagnostic capabilities:

◆ Loop-back controls for communications link fault isolation ■ Prioritized interrupt system controls ■ Modem control functions (CTS, RTS, DSR, DTR, RI, DCD).

3. Ordering information

Table 1: Ordering information

Type number Package

Name Description Version

SC16C2550IN40 DIP40 plastic dual in-line package; 40 leads (600 mil) SOT129-1 SC16C2550IA44 PLCC44 plastic leaded chip carrier; 44 leads SOT187-2 SC16C2550IB48 LQFP48 plastic low proﬁle quad ﬂat package; 48 leads; body 7 × 7 × 1.4 mm SOT313-2

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4. Block diagram

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

D0–D7

IOR

IOW

RESET

A0–A2

CSA CSB

INTA, INTB

, TXRDYB

TXRDYA

RXRDYA, RXRDYB

DATA BUS

AND

CONTROL LOGIC

SELECT

LOGIC

INTERRUPT

CONTROL

LOGIC

AND

CONTROL SIGNALS

INTERCONNECT BUS LINES

TRANSMIT

FIFO

RECEIVE

FIFO

CLOCK AND BAUD RATE

GENERATOR

TRANSMIT

SHIFT

RECEIVE

SHIFT

MODEM

CONTROL

LOGIC

TXA, TXB

RXA, RXB

DTRA, DTRB RTSA, RTSB OP2A, OP2B

, CTSB

CTSA RIA, RIB CDA, CDB DSRA, DSRB

002aaa119

XTAL2XTAL1

Fig 1. SC16C2550 block diagram.

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5. Pinning information

5.1 Pinning

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

D0 D1 D2 D3 D4 D5 D6

D7 RXB RXA

TXA TXB

OP2B

CSA CSB

XTAL1 XTAL2

IOW CDB

GND

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20

SC16C2550IN40

002aaa105

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

RIA CDA DSRA CTSA RESET DTRB DTRA RTSA OP2A INTA INTB A0 A1 A2 CTSB RTSB RIB DSRB IOR

Fig 2. DIP40 pin conﬁguration.

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SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

RXB

RXA

TXA TXB

OP2B

CSA CSB

12 13 14 15 16 17

XTAL2

IOW

XTAL1

TXRDYB

Fig 3. PLCC44 pin conﬁguration.

D1 3

D0 2

TXRDYA

SC16C2550IA44

CDB

GND

IOR

RXRDYB

RIA 43

DSRB

CDA 42

26 RIB

DSRA 41

RTSB

CTSA 40

002aaa103

CTSB

39 38 37 36 35 34 33 32 31 30 29

RESET DTRB DTRA RTSA OP2A RXRDYA INTA INTB A0 A1 A2

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SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

D5 D6

D7 RXB RXA

TXRDYB

TXA TXB

OP2B

CSA CSB N.C.

1 2 3 4 5 6 7 8

9 10 11 12

XTAL1

XTAL2

SC16C2550IB48

IOW

CDB

GND

TXRDYA

IOR

RXRDYB

RIA 41

DSRB

CDA 40

21 RIB

DSRA 39

RTSB

CTSA 38

CTSB

N.C. 37

N.C.

36 35 34 33 32 31 30 29 28 27 26 25

002aaa104

RESET DTRB DTRA RTSA OP2A RXRDYA INTA INTB A0 A1 A2 N.C.

Fig 4. LQFP48 pin conﬁguration.

5.2 Pin description

Table 2: Pin description

Symbol Pin Type Description

DIP40 PLCC44 LQFP48

A0 28 31 28 I Address 0 select bit. Internal register address selection. A1 27 30 27 I Address 1 select bit. Internal register address selection. A2 26 29 26 I Address 2 select bit. Internal register address selection. CSA, CSB 14, 15 16, 17 10, 11 I Chip Select A, B (Active-LOW).This function is associated with individual

channels, A through B. These pins enable data transfers between the user CPU and the SC16C2550 for the channel(s) addressed. Individual UART sections (A, B) are addressed by providing a logic 0 on the respective CSB pin.

D0-D7 1-8 2-9 44-48,

1-3

I/O Data bus (bi-directional). These pins are the 8-bit, 3-State data bus for

transferring information to or from the controlling CPU. D0 is the least signiﬁcant bit and the ﬁrst data bit in a transmit or receive serial data stream.

GND 20 22 17 I Signal and power ground.

CSA,

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SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

Table 2: Pin description

Symbol Pin Type Description

DIP40 PLCC44 LQFP48

INTA, INTB

IOR 21 24 19 I Read strobe (Active-LOW strobe). A logic 0 transition on this pin will load

IOW182015IWrite strobe (Active-LOW strobe). A logic 0 transition on this pin will

OP2A, OP2B

RESET 35 39 36 I Reset (Active-HIGH). A logic 1 on this pin will reset the internal registers

RXRDYA, RXRDYB

TXRDYA, TXRDYB

XTAL1 16 18 13 I Crystal or external clock input. Functions as a crystal input or as an

30, 29 33, 32 30, 29 O Interrupt A, B (3-State). This function is associated with individual channel

31, 13 35, 15 32, 9 O Output 2 (user-deﬁned). This function is associated with individual

- 34, 23 31, 18 O Receive Ready A, B (Active-LOW). This function is associated with

- 1, 12 43, 6 O Transmit Ready A, B (Active-LOW). This function is associated with

40 44 42 I Power supply input.

…continued

interrupts, INTA, INTB. INTA, INTB are enabled when MCR bit 3 is set to a logic 1, interrupts are enabled in the interrupt enable register (IER), and is active when an interrupt condition exists. Interrupt conditions include: receiver errors, available receiver buffer data, transmit buffer empty, or when a modem status ﬂag is detected.

the contents of an internal register deﬁned by address bits A0-A2 onto the SC16C2550 data bus (D0-D7) for access by external CPU.

transfer the contents of the data bus (D0-D7) from the external CPU to an internal register that is deﬁned by address bits A0-A2.

channels, A through B. The state at these pin(s) are deﬁned by the user and through MCR register bit 3. INTA, INTB are set to the active mode and OP2 to logic 0 when MCR[3] is set to a logic 1. INTA, INTB are set to the 3-State mode and bit 3, Modem Control Register (MCR[3]). Since these bits control both the INTA, INTB operation and at one time, INT or

and all the outputs. The UART transmitter output and the receiver input will be disabled during reset time. (See Section 7.11 “SC16C2550 external

reset condition” for initialization details.)

PLCC44 and LQFP48 packages only. This function provides the RX FIFO/RHR status for individual receive channels (A-B). primarily intended for monitoring DMA mode 1 transfersforthe receivedata FIFOs. A logic 0 indicates there is a receive data to read/upload, i.e., receive ready status with one or more RX characters available in the FIFO/RHR. This pin is a logic 1 when the FIFO/RHR is empty or when the programmed trigger level has not been reached. This signal can also be used for single mode transfers (DMA mode 0).

PLCC44 and LQFP48 packages only. These outputs provide the TX FIFO/THR status for individual transmit channels (A-B). primarily intended for monitoring DMA mode 1 transfers for the transmit data FIFOs. An individual channel’s is indicated by logic 0, i.e., at lease one location is empty and available in the FIFO or THR. This pin goes to a logic 1 (DMA mode 1) when there are no more empty locations in the FIFO or THR. This signal can also be used for single mode transfers (DMA mode0).

external clock input. A crystal can be connected between this pin and XTAL2 to form an internal oscillator circuit. This conﬁguration requires an external 1 MΩ resistor between the XTAL1 and XTAL2 pins. Alternatively, an external clock can be connected to this pin to provide custom data rates. (See Section 6.8 “Programmable baud rate generator”.) See Figure 5.

OP2 to a logic 1 when MCR[3] is set to a logic 0. See

OP2 outputs, only one function should be used

OP2.

RXRDYn is

TXRDYn is

TXRDYA, TXRDYB buffer ready status

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SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

Table 2: Pin description

Symbol Pin Type Description

DIP40 PLCC44 LQFP48

XTAL2 17 19 14 O Output of the crystal oscillator or buffered clock. (See also XTAL1.)

CDA, CDB

CTSA, CTSB

DSRA, DSRB

DTRA, DTRB

RIA, RIB 39, 23 43, 26 41, 21 I Ring Indicator (Active-LOW). These inputs are associated with individual

RTSA, RTSB

RXA, RXB 10, 9 11, 10 5, 4 I Receive data A, B. These inputs are associated with individual serial

TXA, TXB 11, 12 13, 14 7, 8 O Transmit data A, B. These outputs are associated with individual serial

38, 19 42, 21 40, 16 I Carrier Detect (Active-LOW). These inputs are associated with individual

36, 25 40, 28 38, 23 I Clear to Send (Active-LOW). These inputs are associated with individual

37, 22 41, 25 39, 20 I Data Set Ready (Active-LOW). These inputs are associated with

33, 34 37, 38 34, 35 O Data Terminal REady (Active-LOW). These outputs are associated with

32, 24 36, 27 33, 22 O Request to Send (Active-LOW). These outputs are associated with

…continued

Crystal oscillator output or buffered clock output. Should be left open if an external clock is connected to XTAL1. For extended frequency operation, this pin should be tied to V

UART channels A through B. A logic 0 on this pin indicates that a carrier has been detected by the modem for that channel.

UART channels, A through B. A logic 0 on the CTS pin indicates the modem or data set is ready to accept transmit data from the SC16C2550. Status can be tested by reading MSR[4]. This pin has no effect on the UART’s transmit or receive operation.

individual UART channels, A through B. A logic 0 on this pin indicates the modem or data set is powered-on and is ready for data exchange with the UART. This pin has no effect on the UART’s transmit or receive operation.

individual UART channels, A through B. A logic 0 on this pin indicates that the SC16C2550 is powered-on and ready. This pin can be controlled via the modem control register. Writing a logic 1 to MCR[0] will set the output to logic 0, enablingthe modem. This pin will be a logic 1 after writing a logic 0 to MCR[0], or after a reset. This pin has no effect on the UART’s transmit or receive operation.

UARTchannels, A through B. A logic 0 on this pin indicates the modem has received a ringing signal from the telephone line. A logic 1 transition on this input pin will generate an interrupt.

individual UART channels, A through B. A logic 0 on the RTS pin indicates the transmitter has data ready and waiting to send. Writing a logic 1 in the modem control register MCR[1] will set this pin to a logic 0, indicating data is available. After a reset this pin will be set to a logic 1. This pin has no effect on the UART’s transmit or receive operation.

channel data to the SC16C2550 receive input circuits, A-B. The RX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loop-back mode, the RX input pin is disabled and TX data is connected to the UART RX input, internally.

transmit channel data from the SC16C2550. The TX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loop-back mode, the TX output pin is disabled and TX data is internally connected to the UART RX input.

via a 2 kΩ resistor.

DTR

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6. Functional description

The SC16C2550 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. Synchronization for the serial data stream is accomplished by adding start and stop bits to the transmit data to form a data character (character orientated protocol). Data integrity is insured by attaching a parity bit to the data character.The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry to provide all these functions is fairly complex, especially when manufactured on a single integrated silicon chip. The SC16C2550 represents such an integration with greatly enhanced features. The SC16C2550 is fabricated with an advanced CMOS process.

The SC16C2550 is an upward solution that provides a dual UART capability with 16 bytes of transmit and receive FIFO memory, instead of none in the 16C2450. The SC16C2550 is designed to work with high speed modems and shared network environments that require fast data processing time. Increased performance is realized in the SC16C2550 by the transmit and receive FIFOs. This allows the external processor to handle more networking tasks within a given time. For example, the ST16C2450 without a receive FIFO, will require unloading of the RHR in 93 microseconds (this example uses a character length of 11 bits, including start/stop bits at 115.2 kbits/s). This means the external CPU will have to service the receive FIFO less than every 100 microseconds. However, with the 16 byte FIFO in the SC16C2550, the data buffer will not require unloading/loading for 1.53 ms. This increases the service interval, giving the external CPU additional time for other applications and reducing the overall UART interrupt servicing time. In addition, the four selectable receive FIFO trigger interrupt levelsis uniquely provided for maximum data throughput performance especially when operating in a multi-channel environment. The FIFO memory greatly reduces the bandwidth requirement of the external controlling CPU, increases performance, and reduces power consumption.

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

The SC16C2550 is capable of operation up to 5 Mbits/s with a 80 MHz clock. With a crystal or external clock input of 7.3728 MHz, the user can select data rates up to

460.8 kbits/s. The rich feature set of the SC16C2550 is available through internal registers.

Selectable receive FIFO trigger levels,selectable TX and RX baud rates, and modem interface controls are all standard features. Followinga power-on reset or an external reset, the SC16C2550 is software compatible with the previous generation, ST16C2450.

6.1 UART A-B functions

The UART provides the user with the capability to bi-directionally transfer information between an external CPU, the SC16C2550 package,and an external serial device. A logic 0 on chip select pins CSA and/or CSB allows the user to conﬁgure, send data, and/or receive data via UART channels A-B. Individual channel select functions are shown in Table 3.

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Table 3: Serial port selection

Chip Select Function

CSA-CSB = 1 none CSA = 0 UART channel A CSB = 0 UART channel B

6.2 Internal registers

The SC16C2550 provides two sets of internal registers (A and B) consisting of 12 registers each for monitoring and controlling the functions of each channel of the UART. These registers are shown in Table 4. The UART registers function as data holding registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register (FCR), line status and control registers (LCR/LSR), modem status and control registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), and a user accessible scratchpad register (SPR).

Table 4: Internal registers decoding

A2 A1 A0 READ mode WRITE mode

General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)

0 0 0 Receive Holding Register Transmit Holding Register 0 0 1 Interrupt Enable Register 0 1 0 Interrupt Status Register FIFO Control Register 0 1 1 Line Control Register 1 0 0 Modem Control Register 1 0 1 Line Status Register n/a 1 1 0 Modem Status Register n/a 1 1 1 Scratchpad Register Scratchpad Register

Baud rate register set (DLL/DLM)

0 0 0 LSB of Divisor Latch LSB of Divisor Latch 0 0 1 MSB of Divisor Latch MSB of Divisor Latch

Enhanced register set (EFR, Xon/off 1-2)

0 1 0 Enhanced Feature Register Enhanced Feature Register 1 0 0 Xon1 word Xon1 word 1 0 1 Xon2 word Xon2 word 1 1 0 Xoff1 word Xoff1 word 1 1 1 Xoff2 word Xoff2 word

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

[1]

[2]

[3]

[1] These registers are accessible only when LCR[7] is a logic 0. [2] These registers are accessible only when LCR[7] is a logic 1. [3] Enhanced Feature Register, Xon1, 2 and Xoff1, 2 are accessible only when the LCR is set to

‘BF(HEX)’.

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6.3 FIFO operation

The 16 byte transmit and receive data FIFOs are enabled by the FIFO Control Register (FCR) bit 0. The user can set the receive trigger level via FCR bits 6-7, but not the transmit trigger level. The receiver FIFO section includes a time-out function to ensure data is delivered to the external CPU. An interrupt is generated whenever the Receive Holding Register (RHR) has not been read following the loading of a character or the receive trigger level has not been reached.

Table 5: Flow control mechanism

Selected trigger level (characters)

1141 4484 8 8 12 8 14 14 14 10

6.4 Hardware ﬂow control

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

INT pin activation Negate RTS or

send Xoff

Assert RTS or send Xon

When automatic hardware ﬂow control is enabled, the SC16C2550 monitors the CTS pin for a remote buffer overﬂow indication and controls the RTS pin for local buffer overﬂows. Automatic hardware ﬂow control is selected by setting EFR[6] (RTS) and EFR[7] (CTS) to a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating a ﬂow control request, ISR[5] will be set to a logic 1 (if enabled via IER[6,7]), and the SC16C2550 will suspend TX transmissions as soon as the stop bit of the character in process is shifted out. Transmission is resumed after the CTS input returns to a logic 0, indicating more data may be sent.

With the Auto RTS function enabled, an interrupt is generated when the receive FIFO reaches the programmed trigger level. The RTS pin will not be forced to a logic 1 (RTS off), until the receive FIFO reaches the next trigger level. However, the RTS pin will return to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level below the programmed trigger. However, under the above described conditions, the SC16C2550 will continue to accept data until the receive FIFO is full.

6.5 Software ﬂow control

When software ﬂow control is enabled, the SC16C2550 compares one or two sequential receive data characters with the programmed Xon/Xoff or Xoff1,2 character value(s). If received character(s) match the programmed values, the SC16C2550 will halt transmission (TX) as soon as the current character(s) has completed transmission. When a match occurs, the receive ready (if enabled via Xoff IER[5]) ﬂags will be set and the interrupt output pin (if receive interrupt is enabled) will be activated. Following a suspension due to a match of the Xoff characters’ values, the SC16C2550 will monitor the receive data stream for a match to the Xon1,2 character value(s). If a match is found, the SC16C2550 will resume operation and clear the ﬂags (ISR[4]).

Reset initially sets the contents of the Xon/Xoff 8-bit ﬂow control registers to a logic 0. Following reset, the user can write any Xon/Xoff value desired for software ﬂow control. Different conditions can be set to detect Xon/Xoff characters and suspend/resume transmissions. When double 8-bit Xon/Xoff characters are selected,

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the SC16C2550 compares two consecutive receive characters with two software ﬂow control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described ﬂow control mechanisms, ﬂow control characters are not placed (stacked) in the user accessible RX data buffer or FIFO.

In the eventthat the receive buffer is overﬁllingand ﬂow control needs to be executed, the SC16C2550 automatically sends an Xoff message (when enabled) via the serial TX output to the remote modem. The SC16C2550 sends the Xoff1,2 characters as soon as received data passes the programmed trigger level. To clear this condition, the SC16C2550 will transmit the programmed Xon1,2 characters as soon as receive data drops below the programmed trigger level.

6.6 Special feature software ﬂow control

A special feature is provided to detect an 8-bit character when EFR[5] is set. When 8-bit character is detected, it will be placed on the user-accessible data stack along with normal incoming RX data. This condition is selected in conjunction with EFR[0-3]. Note that software ﬂow control should be turned off when using this special mode by setting EFR[0-3] to a logic 0.

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

The SC16C2550 compares each incoming receive character with Xoff2 data. If a match exists, the received data will be transferred to the FIFO, and ISR[4] will be set to indicate detection of a special character. Although the Internal Register Table (Table 7) shows each X-Register with eight bits of character information, the actual number of bits is dependent on the programmed word length. Line Control Register bits LCR[0-1] deﬁne the number of character bits, i.e., either 5 bits, 6 bits, 7 bits or 8 bits. The word length selected by LCR[0-1] also determine the number of bits that will be used for the special character comparison. Bit 0 in the X-registers corresponds with the LSB bit for the receive character.

6.7 Hardware/software and time-out interrupts

The interrupts are enabled by IER[0-3]. Care must be taken when handling these interrupts. Following a reset, if Interrupt Enable Register (IER) bit 1 = 1, the SC16C2550 will issue a Transmit Holding Register interrupt. This interrupt must be serviced prior to continuing operations. The LSR register provides the current singular highest priority interrupt only. It could be noted that CTS and RTS interrupts have lowest interrupt priority. A condition can exist where a higher priority interrupt may mask the lower priority CTS/RTS interrupt(s). Only after servicing the higher pending interrupt will the lower priority CTS/RTS interrupt(s) be reﬂected in the status register. Servicing the interrupt without investigating further interrupt conditions can result in data errors.

When two interrupt conditions have the same priority, it is important to service these interrupts correctly. Receive Data Ready and Receive Time Out have the same interrupt priority (when enabled by IER[3]). The receiver issues an interrupt after the number of characters have reached the programmed trigger level. In this case, the SC16C2550 FIFO may hold more characters than the programmed trigger level. Following the removal of a data byte, the user should re-check LSR[0] for additional characters. A Receive Time Out will not occur if the receive FIFO is empty. The time-out counter is reset at the center of each stop bit received or each time the

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receive holding register (RHR) is read. The actual time-out value is 4 character time, including data information length, start bit, parity bit, and the size of stop bit, i.e., 1×,

1.5×, or 2× bit times.

6.8 Programmable baud rate generator

The SC16C2550 supports high speed modem technologies that have increased input data rates by employing data compression schemes. For example, a 33.6 kbit/s modem that employs data compression may require a 115.2 kbit/s input data rate. A 128.0 kbit/s ISDN modem that supports data compression may need an input data rate of 460.8 kbit/s. The SC16C2550 can support a standard data rate of

921.6 kbit/s. A single baud rate generator is provided for the transmitter and receiver, allowing

independent TX/RX channel control. The programmable Baud Rate Generator is capable of operating with a frequency of up to 80 MHz. Toobtain maximum data rate, it is necessary to use full rail swing on the clock input. The SC16C2550 can be conﬁgured for internal or external clock operation. For internal clock oscillator operation, an industry standard microprocessor crystal is connected externally between the XTAL1 and XTAL2 pins. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal baud rate generator for standard or custom rates (see Table 6).

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

The generator divides the input 16× clock by any divisor from 1 to 216− 1. The SC16C2550 divides the basic external clock by 16. The basic 16× clock provides table rates to support standard and custom applications using the same system design. The rate table is conﬁgured via the DLL and DLM internal register functions. Customized Baud Rates can be achieved by selecting the proper divisor values for the MSB and LSB sections of baud rate generator.

Programming the Baud Rate Generator Registers DLM (MSB) and DLL (LSB) provides a user capability for selecting the desired ﬁnal baud rate. The example in

Table 6 shows the selectable baud rate table available when using a 1.8432 MHz

external clock input.

XTAL1

1.8432 MHz

C1 47 pF

XTAL2

C2 100 pF

XTAL1

1.8432 MHz

C1 22 pF

XTAL2

1.5 kΩ

C2 47 pF

002aaa169

Fig 5. Crystal oscillator connection.

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Table 6: Baud rate generator programming table using a 1.8432 MHz clock

Output baud rate

50 2304 900 09 00 75 1536 600 06 00 110 1047 417 04 17 150 768 300 03 00 300 384 180 01 80 600 192 C0 00 C0 1200 96 60 00 60 2400 48 30 00 30 3600 32 20 00 20 4800 24 18 00 18 7200 16 10 00 10 9600 12 0C 00 0C

19.2 k 6 06 00 06

38.4 k 3 03 00 03

57.6 k 2 02 00 02

115.2 k 1 01 00 01

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

Output 16 × clock divisor (decimal)

Output 16 × clockdivisor (HEX)

DLM program value (HEX)

DLL program value (HEX)

6.9 DMA operation

The SC16C2550 FIFO trigger level provides additional ﬂexibility to the user for block mode operation. LSR[5,6] provide an indication when the transmitter is empty or has an empty location(s). The user can optionally operate the transmit and receive FIFOs in the DMA mode (FCR[3]). When the transmit and receive FIFOs are enabled and the DMA mode is de-activated (DMA Mode 0), the SC16C2550 activates the interrupt output pin for each data transmit or receive operation. When DMA mode is activated (DMA Mode 1), the user takes the advantage of block mode operation by loading or unloading the FIFO in a block sequence determined by the receive trigger level and the transmit FIFO. In this mode, the SC16C2550 sets the TXRDY (or RXRDY) output pin when characters in the transmit FIFO is below 16, or the characters in the receive FIFOs are above the receive trigger level.

6.10 Loop-back mode

The internal loop-back capability allows on-board diagnostics. In the loop-back mode, the normal modem interface pins are disconnected and reconﬁgured for loop-back internally (see Figure 6). MCR[0-3] register bits are used for controlling loop-back diagnostic testing. In the loop-back mode, the transmitter output (TX) and the receiver input (RX) are disconnected from their associated interface pins, and instead are connected together internally. The CTS, DSR, CD, and RI are disconnected from their normal modem control inputs pins, and instead are connected internally to RTS, DTR, MCR[3] (OP2) and MCR[2] (OP1). Loop-back test data is entered into the transmit holding register via the user data bus interface, D0-D7. The transmit UART serializes the data and passes the serial data to the receive UART via the internal loop-back connection. The receive UART converts the serial data back into parallel

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