Philips SC16C2550 Technical data

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1. Description

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and infrared (IrDA) encoder/decoder

Rev. 03 — 19 June 2003 Product data

The SC16C2550 is a 2 channel Universal Asynchronous Receiver and Transmitter (UART) used for serial data communications. Its principal function is to convert parallel data into serial data and vice versa. The UART can handle serial data rates up to 5 Mbits/s.

The SC16C2550 is pin compatible with the ST16C2550. It will power-up to be functionally equivalent to the 16C2450. The SC16C2550 provides enhanced UART functions with 16-byte FIFOs, modemcontrol interface, DMA mode data transfer. The DMA mode data transfer is controlled by the FIFO trigger levels and the TXRDY and RXRDY signals. On-board status registers provide the user with error indications and operational status. System interrupts and modem control features may be tailored by software to meet speciﬁc user requirements. An internal loop-back capability allows on-board diagnostics. Independent programmable baud rate generators are provided to select transmit and receive baud rates.

2. Features

The SC16C2550 operates at 5 V, 3.3 V and 2.5 V and the Industrial temperature range, and is available in plastic PLCC44, LQFP48 and DIP40 packages.

■ 2 channel UART

■ 5 V, 3.3 V and 2.5 V operation

■ Industrial temperature range

■ Pin and functionally compatible to 16C2450 and software compatible with

INS8250, SC16C550

■ Up to 5 Mbits/s data rate at 5 V and 3.3 V, and 3 Mbits/s at 2.5 V

■ 16 byte transmit FIFO to reduce the bandwidth requirement of the external CPU

■ 16 byte receive FIFO with error ﬂags to reduce the bandwidth requirement of the

external CPU

■ Independent transmit and receive UART control

■ Four selectable Receive FIFO interrupt trigger levels

■ Automatic software/hardware ﬂow control

■ Programmable Xon/Xoff characters

■ Software selectable Baud Rate Generator

■ Sleep mode

■ Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun

Break)

■ Transmit, Receive, Line Status, and Data Set interrupts independently controlled

Philips Semiconductors

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

■ Fully programmable character formatting:

◆ 5-, 6-, 7-, or 8-bit characters

◆ Even-, Odd-, or No-Parity formats

◆ 1-, 11⁄2-, or 2-stop bit

◆ Baud generation (DC to 1.5 Mbit/s)

■ False start-bit detection

■ Complete status reporting capabilities

■ 3-State output TTL drive capabilities for bi-directional data bus and control bus

■ Line Break generation and detection

■ Internal diagnostic capabilities:

◆ Loop-back controls for communications link fault isolation

■ Prioritized interrupt system controls

■ Modem control functions (CTS, RTS, DSR, DTR, RI, DCD).

3. Ordering information

Table 1: Ordering information

Type number Package

Name Description Version

SC16C2550IN40 DIP40 plastic dual in-line package; 40 leads (600 mil) SOT129-1 SC16C2550IA44 PLCC44 plastic leaded chip carrier; 44 leads SOT187-2 SC16C2550IB48 LQFP48 plastic low proﬁle quad ﬂat package; 48 leads; body 7 × 7 × 1.4 mm SOT313-2

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4. Block diagram

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

D0–D7

IOR

IOW

RESET

A0–A2

CSA CSB

INTA, INTB

, TXRDYB

TXRDYA

RXRDYA, RXRDYB

DATA BUS

AND

CONTROL LOGIC

SELECT

LOGIC

INTERRUPT

CONTROL

LOGIC

AND

CONTROL SIGNALS

INTERCONNECT BUS LINES

TRANSMIT

FIFO

RECEIVE

FIFO

CLOCK AND BAUD RATE

GENERATOR

TRANSMIT

SHIFT

RECEIVE

SHIFT

MODEM

CONTROL

LOGIC

TXA, TXB

RXA, RXB

DTRA, DTRB RTSA, RTSB OP2A, OP2B

, CTSB

CTSA RIA, RIB CDA, CDB DSRA, DSRB

002aaa119

XTAL2XTAL1

Fig 1. SC16C2550 block diagram.

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5. Pinning information

5.1 Pinning

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

D0 D1 D2 D3 D4 D5 D6

D7 RXB RXA

TXA TXB

OP2B

CSA CSB

XTAL1 XTAL2

IOW CDB

GND

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20

SC16C2550IN40

002aaa105

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

RIA CDA DSRA CTSA RESET DTRB DTRA RTSA OP2A INTA INTB A0 A1 A2 CTSB RTSB RIB DSRB IOR

Fig 2. DIP40 pin conﬁguration.

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SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

RXB

RXA

TXA TXB

OP2B

CSA CSB

12 13 14 15 16 17

XTAL2

IOW

XTAL1

TXRDYB

Fig 3. PLCC44 pin conﬁguration.

D1 3

D0 2

TXRDYA

SC16C2550IA44

CDB

GND

IOR

RXRDYB

RIA 43

DSRB

CDA 42

26 RIB

DSRA 41

RTSB

CTSA 40

002aaa103

CTSB

39 38 37 36 35 34 33 32 31 30 29

RESET DTRB DTRA RTSA OP2A RXRDYA INTA INTB A0 A1 A2

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SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

D5 D6

D7 RXB RXA

TXRDYB

TXA TXB

OP2B

CSA CSB N.C.

1 2 3 4 5 6 7 8

9 10 11 12

XTAL1

XTAL2

SC16C2550IB48

IOW

CDB

GND

TXRDYA

IOR

RXRDYB

RIA 41

DSRB

CDA 40

21 RIB

DSRA 39

RTSB

CTSA 38

CTSB

N.C. 37

N.C.

36 35 34 33 32 31 30 29 28 27 26 25

002aaa104

RESET DTRB DTRA RTSA OP2A RXRDYA INTA INTB A0 A1 A2 N.C.

Fig 4. LQFP48 pin conﬁguration.

5.2 Pin description

Table 2: Pin description

Symbol Pin Type Description

DIP40 PLCC44 LQFP48

A0 28 31 28 I Address 0 select bit. Internal register address selection. A1 27 30 27 I Address 1 select bit. Internal register address selection. A2 26 29 26 I Address 2 select bit. Internal register address selection. CSA, CSB 14, 15 16, 17 10, 11 I Chip Select A, B (Active-LOW).This function is associated with individual

channels, A through B. These pins enable data transfers between the user CPU and the SC16C2550 for the channel(s) addressed. Individual UART sections (A, B) are addressed by providing a logic 0 on the respective CSB pin.

D0-D7 1-8 2-9 44-48,

1-3

I/O Data bus (bi-directional). These pins are the 8-bit, 3-State data bus for

transferring information to or from the controlling CPU. D0 is the least signiﬁcant bit and the ﬁrst data bit in a transmit or receive serial data stream.

GND 20 22 17 I Signal and power ground.

CSA,

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SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

Table 2: Pin description

Symbol Pin Type Description

DIP40 PLCC44 LQFP48

INTA, INTB

IOR 21 24 19 I Read strobe (Active-LOW strobe). A logic 0 transition on this pin will load

IOW182015IWrite strobe (Active-LOW strobe). A logic 0 transition on this pin will

OP2A, OP2B

RESET 35 39 36 I Reset (Active-HIGH). A logic 1 on this pin will reset the internal registers

RXRDYA, RXRDYB

TXRDYA, TXRDYB

XTAL1 16 18 13 I Crystal or external clock input. Functions as a crystal input or as an

30, 29 33, 32 30, 29 O Interrupt A, B (3-State). This function is associated with individual channel

31, 13 35, 15 32, 9 O Output 2 (user-deﬁned). This function is associated with individual

- 34, 23 31, 18 O Receive Ready A, B (Active-LOW). This function is associated with

- 1, 12 43, 6 O Transmit Ready A, B (Active-LOW). This function is associated with

40 44 42 I Power supply input.

…continued

interrupts, INTA, INTB. INTA, INTB are enabled when MCR bit 3 is set to a logic 1, interrupts are enabled in the interrupt enable register (IER), and is active when an interrupt condition exists. Interrupt conditions include: receiver errors, available receiver buffer data, transmit buffer empty, or when a modem status ﬂag is detected.

the contents of an internal register deﬁned by address bits A0-A2 onto the SC16C2550 data bus (D0-D7) for access by external CPU.

transfer the contents of the data bus (D0-D7) from the external CPU to an internal register that is deﬁned by address bits A0-A2.

channels, A through B. The state at these pin(s) are deﬁned by the user and through MCR register bit 3. INTA, INTB are set to the active mode and OP2 to logic 0 when MCR[3] is set to a logic 1. INTA, INTB are set to the 3-State mode and bit 3, Modem Control Register (MCR[3]). Since these bits control both the INTA, INTB operation and at one time, INT or

and all the outputs. The UART transmitter output and the receiver input will be disabled during reset time. (See Section 7.11 “SC16C2550 external

reset condition” for initialization details.)

PLCC44 and LQFP48 packages only. This function provides the RX FIFO/RHR status for individual receive channels (A-B). primarily intended for monitoring DMA mode 1 transfersforthe receivedata FIFOs. A logic 0 indicates there is a receive data to read/upload, i.e., receive ready status with one or more RX characters available in the FIFO/RHR. This pin is a logic 1 when the FIFO/RHR is empty or when the programmed trigger level has not been reached. This signal can also be used for single mode transfers (DMA mode 0).

PLCC44 and LQFP48 packages only. These outputs provide the TX FIFO/THR status for individual transmit channels (A-B). primarily intended for monitoring DMA mode 1 transfers for the transmit data FIFOs. An individual channel’s is indicated by logic 0, i.e., at lease one location is empty and available in the FIFO or THR. This pin goes to a logic 1 (DMA mode 1) when there are no more empty locations in the FIFO or THR. This signal can also be used for single mode transfers (DMA mode0).

external clock input. A crystal can be connected between this pin and XTAL2 to form an internal oscillator circuit. This conﬁguration requires an external 1 MΩ resistor between the XTAL1 and XTAL2 pins. Alternatively, an external clock can be connected to this pin to provide custom data rates. (See Section 6.8 “Programmable baud rate generator”.) See Figure 5.

OP2 to a logic 1 when MCR[3] is set to a logic 0. See

OP2 outputs, only one function should be used

OP2.

RXRDYn is

TXRDYn is

TXRDYA, TXRDYB buffer ready status

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SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

Table 2: Pin description

Symbol Pin Type Description

DIP40 PLCC44 LQFP48

XTAL2 17 19 14 O Output of the crystal oscillator or buffered clock. (See also XTAL1.)

CDA, CDB

CTSA, CTSB

DSRA, DSRB

DTRA, DTRB

RIA, RIB 39, 23 43, 26 41, 21 I Ring Indicator (Active-LOW). These inputs are associated with individual

RTSA, RTSB

RXA, RXB 10, 9 11, 10 5, 4 I Receive data A, B. These inputs are associated with individual serial

TXA, TXB 11, 12 13, 14 7, 8 O Transmit data A, B. These outputs are associated with individual serial

38, 19 42, 21 40, 16 I Carrier Detect (Active-LOW). These inputs are associated with individual

36, 25 40, 28 38, 23 I Clear to Send (Active-LOW). These inputs are associated with individual

37, 22 41, 25 39, 20 I Data Set Ready (Active-LOW). These inputs are associated with

33, 34 37, 38 34, 35 O Data Terminal REady (Active-LOW). These outputs are associated with

32, 24 36, 27 33, 22 O Request to Send (Active-LOW). These outputs are associated with

…continued

Crystal oscillator output or buffered clock output. Should be left open if an external clock is connected to XTAL1. For extended frequency operation, this pin should be tied to V

UART channels A through B. A logic 0 on this pin indicates that a carrier has been detected by the modem for that channel.

UART channels, A through B. A logic 0 on the CTS pin indicates the modem or data set is ready to accept transmit data from the SC16C2550. Status can be tested by reading MSR[4]. This pin has no effect on the UART’s transmit or receive operation.

individual UART channels, A through B. A logic 0 on this pin indicates the modem or data set is powered-on and is ready for data exchange with the UART. This pin has no effect on the UART’s transmit or receive operation.

individual UART channels, A through B. A logic 0 on this pin indicates that the SC16C2550 is powered-on and ready. This pin can be controlled via the modem control register. Writing a logic 1 to MCR[0] will set the output to logic 0, enablingthe modem. This pin will be a logic 1 after writing a logic 0 to MCR[0], or after a reset. This pin has no effect on the UART’s transmit or receive operation.

UARTchannels, A through B. A logic 0 on this pin indicates the modem has received a ringing signal from the telephone line. A logic 1 transition on this input pin will generate an interrupt.

individual UART channels, A through B. A logic 0 on the RTS pin indicates the transmitter has data ready and waiting to send. Writing a logic 1 in the modem control register MCR[1] will set this pin to a logic 0, indicating data is available. After a reset this pin will be set to a logic 1. This pin has no effect on the UART’s transmit or receive operation.

channel data to the SC16C2550 receive input circuits, A-B. The RX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loop-back mode, the RX input pin is disabled and TX data is connected to the UART RX input, internally.

transmit channel data from the SC16C2550. The TX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loop-back mode, the TX output pin is disabled and TX data is internally connected to the UART RX input.

via a 2 kΩ resistor.

DTR

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6. Functional description

The SC16C2550 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. Synchronization for the serial data stream is accomplished by adding start and stop bits to the transmit data to form a data character (character orientated protocol). Data integrity is insured by attaching a parity bit to the data character.The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry to provide all these functions is fairly complex, especially when manufactured on a single integrated silicon chip. The SC16C2550 represents such an integration with greatly enhanced features. The SC16C2550 is fabricated with an advanced CMOS process.

The SC16C2550 is an upward solution that provides a dual UART capability with 16 bytes of transmit and receive FIFO memory, instead of none in the 16C2450. The SC16C2550 is designed to work with high speed modems and shared network environments that require fast data processing time. Increased performance is realized in the SC16C2550 by the transmit and receive FIFOs. This allows the external processor to handle more networking tasks within a given time. For example, the ST16C2450 without a receive FIFO, will require unloading of the RHR in 93 microseconds (this example uses a character length of 11 bits, including start/stop bits at 115.2 kbits/s). This means the external CPU will have to service the receive FIFO less than every 100 microseconds. However, with the 16 byte FIFO in the SC16C2550, the data buffer will not require unloading/loading for 1.53 ms. This increases the service interval, giving the external CPU additional time for other applications and reducing the overall UART interrupt servicing time. In addition, the four selectable receive FIFO trigger interrupt levelsis uniquely provided for maximum data throughput performance especially when operating in a multi-channel environment. The FIFO memory greatly reduces the bandwidth requirement of the external controlling CPU, increases performance, and reduces power consumption.

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

The SC16C2550 is capable of operation up to 5 Mbits/s with a 80 MHz clock. With a crystal or external clock input of 7.3728 MHz, the user can select data rates up to

460.8 kbits/s. The rich feature set of the SC16C2550 is available through internal registers.

Selectable receive FIFO trigger levels,selectable TX and RX baud rates, and modem interface controls are all standard features. Followinga power-on reset or an external reset, the SC16C2550 is software compatible with the previous generation, ST16C2450.

6.1 UART A-B functions

The UART provides the user with the capability to bi-directionally transfer information between an external CPU, the SC16C2550 package,and an external serial device. A logic 0 on chip select pins CSA and/or CSB allows the user to conﬁgure, send data, and/or receive data via UART channels A-B. Individual channel select functions are shown in Table 3.

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Table 3: Serial port selection

Chip Select Function

CSA-CSB = 1 none CSA = 0 UART channel A CSB = 0 UART channel B

6.2 Internal registers

The SC16C2550 provides two sets of internal registers (A and B) consisting of 12 registers each for monitoring and controlling the functions of each channel of the UART. These registers are shown in Table 4. The UART registers function as data holding registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register (FCR), line status and control registers (LCR/LSR), modem status and control registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), and a user accessible scratchpad register (SPR).

Table 4: Internal registers decoding

A2 A1 A0 READ mode WRITE mode

General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)

0 0 0 Receive Holding Register Transmit Holding Register 0 0 1 Interrupt Enable Register 0 1 0 Interrupt Status Register FIFO Control Register 0 1 1 Line Control Register 1 0 0 Modem Control Register 1 0 1 Line Status Register n/a 1 1 0 Modem Status Register n/a 1 1 1 Scratchpad Register Scratchpad Register

Baud rate register set (DLL/DLM)

0 0 0 LSB of Divisor Latch LSB of Divisor Latch 0 0 1 MSB of Divisor Latch MSB of Divisor Latch

Enhanced register set (EFR, Xon/off 1-2)

0 1 0 Enhanced Feature Register Enhanced Feature Register 1 0 0 Xon1 word Xon1 word 1 0 1 Xon2 word Xon2 word 1 1 0 Xoff1 word Xoff1 word 1 1 1 Xoff2 word Xoff2 word

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

[1]

[2]

[3]

[1] These registers are accessible only when LCR[7] is a logic 0. [2] These registers are accessible only when LCR[7] is a logic 1. [3] Enhanced Feature Register, Xon1, 2 and Xoff1, 2 are accessible only when the LCR is set to

‘BF(HEX)’.

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6.3 FIFO operation

The 16 byte transmit and receive data FIFOs are enabled by the FIFO Control Register (FCR) bit 0. The user can set the receive trigger level via FCR bits 6-7, but not the transmit trigger level. The receiver FIFO section includes a time-out function to ensure data is delivered to the external CPU. An interrupt is generated whenever the Receive Holding Register (RHR) has not been read following the loading of a character or the receive trigger level has not been reached.

Table 5: Flow control mechanism

Selected trigger level (characters)

1141 4484 8 8 12 8 14 14 14 10

6.4 Hardware ﬂow control

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

INT pin activation Negate RTS or

send Xoff

Assert RTS or send Xon

When automatic hardware ﬂow control is enabled, the SC16C2550 monitors the CTS pin for a remote buffer overﬂow indication and controls the RTS pin for local buffer overﬂows. Automatic hardware ﬂow control is selected by setting EFR[6] (RTS) and EFR[7] (CTS) to a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating a ﬂow control request, ISR[5] will be set to a logic 1 (if enabled via IER[6,7]), and the SC16C2550 will suspend TX transmissions as soon as the stop bit of the character in process is shifted out. Transmission is resumed after the CTS input returns to a logic 0, indicating more data may be sent.

With the Auto RTS function enabled, an interrupt is generated when the receive FIFO reaches the programmed trigger level. The RTS pin will not be forced to a logic 1 (RTS off), until the receive FIFO reaches the next trigger level. However, the RTS pin will return to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level below the programmed trigger. However, under the above described conditions, the SC16C2550 will continue to accept data until the receive FIFO is full.

6.5 Software ﬂow control

When software ﬂow control is enabled, the SC16C2550 compares one or two sequential receive data characters with the programmed Xon/Xoff or Xoff1,2 character value(s). If received character(s) match the programmed values, the SC16C2550 will halt transmission (TX) as soon as the current character(s) has completed transmission. When a match occurs, the receive ready (if enabled via Xoff IER[5]) ﬂags will be set and the interrupt output pin (if receive interrupt is enabled) will be activated. Following a suspension due to a match of the Xoff characters’ values, the SC16C2550 will monitor the receive data stream for a match to the Xon1,2 character value(s). If a match is found, the SC16C2550 will resume operation and clear the ﬂags (ISR[4]).

Reset initially sets the contents of the Xon/Xoff 8-bit ﬂow control registers to a logic 0. Following reset, the user can write any Xon/Xoff value desired for software ﬂow control. Different conditions can be set to detect Xon/Xoff characters and suspend/resume transmissions. When double 8-bit Xon/Xoff characters are selected,

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the SC16C2550 compares two consecutive receive characters with two software ﬂow control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described ﬂow control mechanisms, ﬂow control characters are not placed (stacked) in the user accessible RX data buffer or FIFO.

In the eventthat the receive buffer is overﬁllingand ﬂow control needs to be executed, the SC16C2550 automatically sends an Xoff message (when enabled) via the serial TX output to the remote modem. The SC16C2550 sends the Xoff1,2 characters as soon as received data passes the programmed trigger level. To clear this condition, the SC16C2550 will transmit the programmed Xon1,2 characters as soon as receive data drops below the programmed trigger level.

6.6 Special feature software ﬂow control

A special feature is provided to detect an 8-bit character when EFR[5] is set. When 8-bit character is detected, it will be placed on the user-accessible data stack along with normal incoming RX data. This condition is selected in conjunction with EFR[0-3]. Note that software ﬂow control should be turned off when using this special mode by setting EFR[0-3] to a logic 0.

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

The SC16C2550 compares each incoming receive character with Xoff2 data. If a match exists, the received data will be transferred to the FIFO, and ISR[4] will be set to indicate detection of a special character. Although the Internal Register Table (Table 7) shows each X-Register with eight bits of character information, the actual number of bits is dependent on the programmed word length. Line Control Register bits LCR[0-1] deﬁne the number of character bits, i.e., either 5 bits, 6 bits, 7 bits or 8 bits. The word length selected by LCR[0-1] also determine the number of bits that will be used for the special character comparison. Bit 0 in the X-registers corresponds with the LSB bit for the receive character.

6.7 Hardware/software and time-out interrupts

The interrupts are enabled by IER[0-3]. Care must be taken when handling these interrupts. Following a reset, if Interrupt Enable Register (IER) bit 1 = 1, the SC16C2550 will issue a Transmit Holding Register interrupt. This interrupt must be serviced prior to continuing operations. The LSR register provides the current singular highest priority interrupt only. It could be noted that CTS and RTS interrupts have lowest interrupt priority. A condition can exist where a higher priority interrupt may mask the lower priority CTS/RTS interrupt(s). Only after servicing the higher pending interrupt will the lower priority CTS/RTS interrupt(s) be reﬂected in the status register. Servicing the interrupt without investigating further interrupt conditions can result in data errors.

When two interrupt conditions have the same priority, it is important to service these interrupts correctly. Receive Data Ready and Receive Time Out have the same interrupt priority (when enabled by IER[3]). The receiver issues an interrupt after the number of characters have reached the programmed trigger level. In this case, the SC16C2550 FIFO may hold more characters than the programmed trigger level. Following the removal of a data byte, the user should re-check LSR[0] for additional characters. A Receive Time Out will not occur if the receive FIFO is empty. The time-out counter is reset at the center of each stop bit received or each time the

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receive holding register (RHR) is read. The actual time-out value is 4 character time, including data information length, start bit, parity bit, and the size of stop bit, i.e., 1×,

1.5×, or 2× bit times.

6.8 Programmable baud rate generator

The SC16C2550 supports high speed modem technologies that have increased input data rates by employing data compression schemes. For example, a 33.6 kbit/s modem that employs data compression may require a 115.2 kbit/s input data rate. A 128.0 kbit/s ISDN modem that supports data compression may need an input data rate of 460.8 kbit/s. The SC16C2550 can support a standard data rate of

921.6 kbit/s. A single baud rate generator is provided for the transmitter and receiver, allowing

independent TX/RX channel control. The programmable Baud Rate Generator is capable of operating with a frequency of up to 80 MHz. Toobtain maximum data rate, it is necessary to use full rail swing on the clock input. The SC16C2550 can be conﬁgured for internal or external clock operation. For internal clock oscillator operation, an industry standard microprocessor crystal is connected externally between the XTAL1 and XTAL2 pins. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal baud rate generator for standard or custom rates (see Table 6).

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

The generator divides the input 16× clock by any divisor from 1 to 216− 1. The SC16C2550 divides the basic external clock by 16. The basic 16× clock provides table rates to support standard and custom applications using the same system design. The rate table is conﬁgured via the DLL and DLM internal register functions. Customized Baud Rates can be achieved by selecting the proper divisor values for the MSB and LSB sections of baud rate generator.

Programming the Baud Rate Generator Registers DLM (MSB) and DLL (LSB) provides a user capability for selecting the desired ﬁnal baud rate. The example in

Table 6 shows the selectable baud rate table available when using a 1.8432 MHz

external clock input.

XTAL1

1.8432 MHz

C1 47 pF

XTAL2

C2 100 pF

XTAL1

1.8432 MHz

C1 22 pF

XTAL2

1.5 kΩ

C2 47 pF

002aaa169

Fig 5. Crystal oscillator connection.

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Table 6: Baud rate generator programming table using a 1.8432 MHz clock

Output baud rate

50 2304 900 09 00 75 1536 600 06 00 110 1047 417 04 17 150 768 300 03 00 300 384 180 01 80 600 192 C0 00 C0 1200 96 60 00 60 2400 48 30 00 30 3600 32 20 00 20 4800 24 18 00 18 7200 16 10 00 10 9600 12 0C 00 0C

19.2 k 6 06 00 06

38.4 k 3 03 00 03

57.6 k 2 02 00 02

115.2 k 1 01 00 01

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

Output 16 × clock divisor (decimal)

Output 16 × clockdivisor (HEX)

DLM program value (HEX)

DLL program value (HEX)

6.9 DMA operation

The SC16C2550 FIFO trigger level provides additional ﬂexibility to the user for block mode operation. LSR[5,6] provide an indication when the transmitter is empty or has an empty location(s). The user can optionally operate the transmit and receive FIFOs in the DMA mode (FCR[3]). When the transmit and receive FIFOs are enabled and the DMA mode is de-activated (DMA Mode 0), the SC16C2550 activates the interrupt output pin for each data transmit or receive operation. When DMA mode is activated (DMA Mode 1), the user takes the advantage of block mode operation by loading or unloading the FIFO in a block sequence determined by the receive trigger level and the transmit FIFO. In this mode, the SC16C2550 sets the TXRDY (or RXRDY) output pin when characters in the transmit FIFO is below 16, or the characters in the receive FIFOs are above the receive trigger level.

6.10 Loop-back mode

The internal loop-back capability allows on-board diagnostics. In the loop-back mode, the normal modem interface pins are disconnected and reconﬁgured for loop-back internally (see Figure 6). MCR[0-3] register bits are used for controlling loop-back diagnostic testing. In the loop-back mode, the transmitter output (TX) and the receiver input (RX) are disconnected from their associated interface pins, and instead are connected together internally. The CTS, DSR, CD, and RI are disconnected from their normal modem control inputs pins, and instead are connected internally to RTS, DTR, MCR[3] (OP2) and MCR[2] (OP1). Loop-back test data is entered into the transmit holding register via the user data bus interface, D0-D7. The transmit UART serializes the data and passes the serial data to the receive UART via the internal loop-back connection. The receive UART converts the serial data back into parallel

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data that is then made available at the user data interface D0-D7. The user optionally compares the received data to the initial transmitted data for verifying error-free operation of the UART TX/RX circuits.

In this mode, the receiver and transmitter interrupts are fully operational. The Modem Control Interrupts are also operational.

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

D0–D7

RESET

CSA

IOR

IOW

A0–A2

, CSB

DATA BUS

AND

CONTROL LOGIC

SELECT

LOGIC

AND

CONTROL SIGNALS

INTERCONNECT BUS LINES

TRANSMIT

FIFO

RECEIVE

FIFO

TRANSMIT

SHIFT

RECEIVE

SHIFT

MODEM

CONTROL

LOGIC

TXA, TXB

MCR[4] = 1

RXA, RXB

RTSA, RTSB

CTSA, CTSB

DTRA, DTRB

DSRA, DSRB

(OP1A, OP1B)

INTA, INTB

, TXRDYB

TXRDYA

RXRDYA, RXRDYB

INTERRUPT

CONTROL

LOGIC

CLOCK AND BAUD RATE

GENERATOR

XTAL2XTAL1

002aaa120

RIA, RIB

(OP2A, OP2B)

CDA, CDB

Fig 6. Internal loop-back mode diagram.

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SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

7. Register descriptions

Table 7 details the assigned bit functions for the SC16C2550 internal registers. The

assigned bit functions are more fully deﬁned in Section 7.1 through Section 7.11.

Table 7: SC16C2550 internal registers

Shaded bits are only accessible when EFR[4] is set.

A2 A1 A0 Register Default

General Register Set

[2]

0 0 0 RHR XX bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 THR XX bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 1 IER 00

0 1 0 FCR 00 RCVR

0 1 0 ISR 01 FIFOs

0 1 1 LCR 00 divisor

1 0 0 MCR 00 0

1 0 1 LSR 60 FIFO

1 1 0 MSR X0 CD RI DSR CTS ∆ 1 1 1 SPR FF bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Special Register Set

[3]

0 0 0 DLL XX bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 1 DLM XX bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8

Enhanced Register Set

[4]

0 1 0 EFR 00 Auto

1 0 0 Xon-1 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 0 1 Xon-2 00 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 1 1 0 Xoff-1 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 1 1 Xoff-2 00 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8

[1]

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CTS interrupt

trigger (MSB)

enabled

latch enable

data error

RTS interrupt

RCVR

Xoff interrupt

Sleep mode

reserved0reserved0DMA trigger (LSB)

FIFOs enabled

INT

priority

bit 4

INT priority bit 3

set break set parity even

parity

0 loop back OP2/INT enable

THR and TSR

THR

empty

break interrupt

empty

modem status interrupt

mode select

INT priority bit 2

parity enable

enable framing

error

receive line status interrupt

XMIT FIFO reset

INT priority bit 1

transmit holding register interrupt

RCVR FIFO reset

INT priority bit 0

stop bits word

length bit 1

(OP1) RTS DTR

parity error

overrun error

CD ∆RI ∆DSR ∆CTS

CTS

Auto RTS

Special

char.

select

Enable IER[4-7], ISR[4,5],

Cont-3 Tx, Rx Control

Cont-2 Tx, Rx Control

Cont-1 Tx, Rx

Control FCR[4,5], MCR[5-7]

receive holding register

FIFOs enable

INT status

word length bit 0

receive data ready

Cont-0 Tx, Rx Control

[1] The value shown in represents the register’s initialized HEX value; X = n/a. [2] Accessible only when LCR[7] is logic 0. [3] Baud rate registers accessible only when LCR[7] is logic 1. [4] Enhanced Feature Register, Xon-1,2 and Xoff-1,2 are accessible only when LCR is set to ‘BF

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7.1 Transmit (THR) and Receive (RHR) Holding Registers

The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and Transmit Shift Register (TSR). The status of the THR is provided in the Line Status Register (LSR). Writing to the THR transfers the contents of the data bus (D7-D0) to the TSR and UART via the THR, providing that the THR is empty. The THR empty ﬂag in the LSR register will be set to a logic 1 when the transmitter is empty or when data is transferred to the TSR. Note that a write operation can be performed when the THR empty ﬂag is set (logic 0 = at least one byte in FIFO/THR, logic 1 = FIFO/THR empty).

The serial receive section also contains an 8-bit ReceiveHolding Register (RHR) and a Receive Serial Shift Register (RSR). Receivedata is removed from the SC16C2550 and receive FIFO by reading the RHR register. The receive section provides a mechanism to prevent false starts. On the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at the 16× clock rate. After 7-1⁄ clocks, the start bit time should be shifted to the center of the start bit. At this time the start bit is sampled, and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from assembling a false character. Receiver status codes will be posted in the LSR.

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

7.2 Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter empty, line status and modem status registers. These interrupts would normally be seen on the INTA, INTB output pins.

Table 8: Interrupt Enable Register bits description

Bit Symbol Description

7 IER[7] CTS interrupt.

Logic 0 = Disable the CTS interrupt (normal default condition). Logic 1 = Enable the CTS interrupt. The SC16C2550 issues an

interrupt when the CTS pin transitions from a logic 0 to a logic 1.

6 IER[6] RTS interrupt.

Logic 0 = Disable the RTS interrupt (normal default condition). Logic 1 = Enable the RTS interrupt. The SC16C2550 issues an

interrupt when the RTS pin transitions from a logic 0 to a logic 1.

5 IER[5] Xoff interrupt.

Logic 0 = Disable the software ﬂow control, receiveXoff interrupt (normal default condition).

Logic 1 = Enable the software ﬂow control, receive Xoff interrupt.

4 IER[4] Sleep mode.

Logic 0 = Disable sleep mode (normal default condition). Logic 1 = Enable sleep mode.

3 IER[3] Modem Status Interrupt. This interrupt will be issued whenever

there is a modem status change as reﬂected in MSR[0-3].

Logic 0 = Disable the modem status register interrupt (normal default condition).

Logic 1 = Enable the modem status register interrupt.

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SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

Table 8: Interrupt Enable Register bits description

Bit Symbol Description

2 IER[2] Receive Line Status interrupt. This interrupt will be issued

whenever a receive data error condition exists as reﬂected in LSR[1-4].

Logic 0 = Disable the receiver line status interrupt (normal default condition).

Logic 1 = Enable the receiver line status interrupt.

1 IER[1] Transmit Holding Register interrupt. In the 16C450 mode, this

interrupt will be issued whenever the THR is empty, and is associated with LSR[5]. In the FIFO modes, this interrupt will be issued whenever the FIFO is empty.

Logic 0 = Disable the Transmit Holding Register Empty (TXRDY) interrupt (normal default condition).

Logic 1 = Enable the TXRDY (ISR level 3) interrupt.

0 IER[0] Receive Holding Register. In the 16C450 mode, this interrupt will

be issued when the RHR has data, or is cleared when the RHR is empty. In the FIFO mode, this interrupt will be issued when the FIFO has reached the programmed trigger levelor is cleared when the FIFO drops below the trigger level.

Logic 0 = Disable the receiver ready (ISR level 2, RXRDY) interrupt (normal default condition).

Logic 1 = Enable the RXRDY (ISR level 2) interrupt.

…continued

7.2.1 IER versus Transmit/Receive FIFO interrupt mode operation

When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are enabled, the receive interrupts and register status will reﬂect the following:

• The receive RXRDY interrupt (Level 2 ISR interrupt) is issued to the external CPU

when the receive FIFO has reached the programmed trigger level. It will be cleared when the receive FIFO drops below the programmed trigger level.

• Receive FIFO status will also be reﬂected in the user accessible ISR register when

the receive FIFO trigger level is reached. Both the ISR register receive status bit and the interrupt will be cleared when the FIFO drops below the trigger level.

• The receive data ready bit (LSR[0]) is set as soon as a character is transferred

from the shift register (RSR) to the receive FIFO. It is reset when the FIFO is empty.

• When the Transmit FIFO and interrupts are enabled, an interrupt is generated

when the transmit FIFO is empty due to the unloading of the data by the TSR and UART for transmission via the transmission media. The interrupt is cleared either by reading the ISR register, or by loading the THR with new data characters.

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7.2.2 IER versus Receive/Transmit FIFO polled mode operation

When FCR[0] = logic 1, resetting IER[0-3] enables the SC16C2550 in the FIFO polled mode of operation. In this mode, interrupts are not generated and the user must poll the LSR register for TX and/or RX data status. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s).

• LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.

• LSR[1-4] will provide the type of receive errors, or a receive break, if encountered.

• LSR[5] will indicate when the transmit FIFO is empty.

• LSR[6] will indicate when both the transmit FIFO and transmit shift register are

• LSR[7] will show if any FIFO data errors occurred.

7.3 FIFO Control Register (FCR)

This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger levels, and select the DMA mode.

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

empty.

7.3.1 DMA mode

Mode 0 (FCR bit 3 = 0): Set and enable the interrupt for each single transmit or

receive operation, and is similar to the 16C450 mode. Transmit Ready (TXRDY) on PLCC44 and LQFP48 packages will go to a logic 0 wheneverthe FIFO (THR, if FIFO is not enabled) is empty. Receive Ready (RXRDY) on PLCC44 and LQFP48 packages will go to a logic 0 wheneverthe ReceiveHolding Register (RHR) is loaded with a character.

Mode 1 (FCR bit 3 = 1): Set and enable the interrupt in a blockmode operation. The

transmit interrupt is set when the transmit FIFO is empty. TXRDY on PLCC and LQFP48 packages remains a logic 0 as long as one empty FIFO location is available. The receive interrupt is set when the receive FIFO ﬁlls to the programmed trigger level.However, the FIFO continues to ﬁll regardless of the programmed level until the FIFO is full. RXRDY on PLCC44 and LQFP48 packages transitions LOW when the FIFO reaches the trigger level, and transitions HIGH when the FIFO empties.

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7.3.2 FIFO mode

Table 9: FIFO Control Register bits description

Bit Symbol Description

7-6 FCR[7]

5-4 FCR[5-4] Not used; initialized to logic 0. 3 FCR[3] DMA mode select.

2 FCR[2] XMIT FIFO reset.

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

RCVR trigger. These bits are used to set the trigger level for the (MSB), FCR[6] (LSB)

receive FIFO interrupt.

Logic 0 (or cleared) = normal default condition. Logic 1 = RX trigger level.

An interrupt is generated when the number of characters in the

FIFO equals the programmed trigger level. However, the FIFO will

continue to be loaded until it is full. Refer to Table 10.

Logic 0 = Set DMA mode ‘0’ Logic 1 = Set DMA mode ‘1’

Transmit operation in mode ‘0’: When the SC16C2550 is in the

16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO

mode (FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and

when there are no characters in the transmit FIFO or transmit

holding register, the

will be a logic 0. Once active, the

after the ﬁrst character is loaded into the transmit holding register.

Receive operation in mode ‘0’: When the SC16C2550 is in

mode ‘0’ (FCR[0] = logic 0), or in the FIFO mode (FCR[3] = logic 0)

and there is at lease one character in the receive FIFO, the

RXRDY pin will be a logic 0. Once active, the RXRDY pin on

PLCC44 and LQFP48 packages will go to a logic 1 when there are

no more characters in the receiver.

Transmit operation in mode ‘1’: When the SC16C2550 is in

FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1), the

PLCC44 and LQFP48 packageswill be a logic 1 when the transmit

FIFO is completely full. It will be a logic 0 if one or more FIFO

locations are empty.

Receive operation in mode ‘1’: When the SC16C2550 is in FIFO

mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has

been reached, or a Receive Time-Out has occurred, the

pin on PLCC44 and LQFP48 packages will go to a logic 0. Once

activated,it will go to a logic 1 after there are no more charactersin

the FIFO.

Logic 0 = Transmit FIFO not reset (normal default condition). Logic 1 = Clears the contents of the transmit FIFO and resets

the FIFO counter logic (the transmit shift register is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO.

TXRDY pin in PLCC44 or LQFP48 packages

TXRDY pin will go to a logic 1

TXRDY pin on

RXRDY

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SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

Table 9: FIFO Control Register bits description

Bit Symbol Description

1 FCR[1] RCVR FIFO reset.

Logic 0 = Receive FIFO not reset (normal default condition). Logic 1 = Clears the contents of the receive FIFO and resets the

FIFO counter logic (the receive shift register is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO.

0 FCR[0] FIFOs enabled.

Logic 0 = Disable the transmit and receive FIFO (normal default condition).

Logic 1 = Enable the transmit and receive FIFO. This bit must

be a ‘1’ when other FCR bits are written to, or they will not be programmed.

Table 10: RCVR trigger levels

FCR[7] FCR[6] RX FIFO trigger level

0001 0104 1008 1114

…continued

7.4 Interrupt Status Register (ISR)

The SC16C2550 provides four levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with four interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced. No other interrupts are acknowledged until the pending interrupt is serviced. A lower level interrupt may be seen after servicing the higher level interrupt and re-reading the interrupt status bits. Table 11

“Interrupt source” shows the data values (bits 0-3) for the four prioritized interrupt

levels and the interrupt sources associated with each of these interrupt levels.

Table 11: Interrupt source

Priority level

1 000110LSR(ReceiverLineStatus

2 000100RXRDY (Received Data

2 001100RXRDY (Receive Data

3 000010TXRDY (Transmitter

4 000000MSR (Modem Status

5 010000RXRDY (Received Xoff

6 100000CTS, RTS change of state

ISR[5] ISR[4] ISR[3] ISR[2] ISR[1] ISR[0] Source of the interrupt

Ready)

time-out)

Holding Register Empty)

signal) / Special character

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Table 12: Interrupt Status Register bits description

Bit Symbol Description

7-6 ISR[7-6] FIFOs enabled. These bits are set to a logic 0 when the FIFOs are

5-4 ISR[5-4] INT priority bits 4-3. These bits are enabled when EFR[4] is set to

3-1 ISR[3-1] INT priority bits 2-0. These bits indicate the source for a pending

0 ISR[0] INT status.

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

not being used in the 16C450 mode. They are set to a logic 1

when the FIFOs are enabled in the SC16C2550 mode.

Logic 0 or cleared = default condition.

a logic 1. ISR[4] indicates that matching Xoff character(s) have

been detected. ISR[5] indicates that CTS, RTS have been

generated. Note that once set to a logic 1, the ISR[4] bit will stay a

logic 1 until Xon character(s) are received.

Logic 0 or cleared = default condition.

interrupt at interrupt priority levels 1, 2, and 3 (see Table 11).

Logic 0 or cleared = default condition.

Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt service routine.

Logic 1 = No interrupt pending (normal default condition).

7.5 Line Control Register (LCR)

The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register.

Table 13: Line Control Register bits description

Bit Symbol Description

7 LCR[7] Divisor latch enable. The internal baud rate counter latch and

Enhance Feature mode enable.

Logic 0 = Divisor latch disabled (normal default condition). Logic 1 = Divisor latch enabled.

6 LCR[6] Set break. When enabled, the Break control bit causes a break

condition to be transmitted (the TX output is forced to a logic 0

state). This condition exists until disabled by setting LCR[6] to a

logic 0.

Logic 0 = no TX break condition (normal default condition) Logic 1 = forces the transmitter output (TX) to a logic 0 for

alerting the remote receiver to a line break condition. 5-3 LCR[5-3] Programs the parity conditions (see Table 14). 2 LCR[2] Stop bits. The length of stop bit is speciﬁed by this bit in

conjunction with the programmed word length (see Table 15).

Logic 0 or cleared = default condition. 1-0 LCR[1-0] Word length bits 1, 0. These two bits specify the word length to be

transmitted or received (see Table 16).

Logic 0 or cleared = default condition.

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Table 14: LCR[5-3] parity selection

LCR[5] LCR[4] LCR[3] Parity selection

X X 0 no parity X 0 1 ODD parity 0 1 1 EVEN parity 001forced parity ‘1’ 111forced parity ‘0’

Table 15: LCR[2] stop bit length

LCR[2] Word length Stop bit length (bit times)

0 5, 6, 7, 8 1 15 11 6, 7, 8 2

Table 16: LCR[1-0] word length

LCR[1] LCR[0] Word length

005 016 107 118

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

⁄

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7.6 Modem Control Register (MCR)

This register controls the interface with the modem or a peripheral device.

Table 17: Modem Control Register bits description

Bit Symbol Description

7 MCR[7] Reserved; set to ‘0’. 6 MCR[6] IR enable.

5 MCR[5] Reserved; set to ‘0’. 4 MCR[4] Loop-back. Enable the local loop-back mode (diagnostics). In this

3 MCR[3]

2 MCR[2] (

1 MCR[1]

0 MCR[0]

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

Logic 0 = Enable the standard modem receive and transmit input/output interface (normal default condition).

Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. While in this mode, the TX/RX output/inputs are routed to the infrared encoder/decoder. The data input and output levels will conform to the IrDA infrared interface requirement. As such, while in this mode, the infrared TX output will be a logic 0 during idle data conditions.

mode the transmitter output ( DSR, CD, and RI are disconnected from the SC16C2550 I/O pins. Internally the modem data and control pins are connected into a loop-back data conﬁguration (see Figure 6). In this mode, the receiver and transmitter interrupts remain fully operational. The Modem Control Interrupts are also operational, but the interrupts’ sources are switched to the lower four bits of the Modem Control. Interrupts continue to be controlled by the IER register.

Logic 0 = Disable loop-back mode (normal default condition). Logic 1 = Enable local loop-back mode (diagnostics).

OP2/INT enable

Logic 0 = Forces INT (A-B) outputs to the 3-State mode and sets OP2 to a logic 1 (normal default condition).

Logic 1 = Forces the INT (A-B outputs to the active mode and sets OP2 to a logic 0.

OP1). OP1A/OP1B are not available as an external signal in the SC16C2550. This bit is instead used in the Loop-back mode only. In the loop-back mode, this bit is used to write the state of the modem interface signal.

RTS

Logic 0 = Force Logic1=Force

DTR

Logic 0 = Force Logic 1 = Force

RTS output to a logic 1 (normal default condition). RTS output to a logic 0.

DTR output to a logic 1 (normal default condition). DTR output to a logic 0.

TX) and the receiver input (RX), CTS,

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7.7 Line Status Register (LSR)

This register provides the status of data transfers between the SC16C2550 and the CPU.

Table 18: Line Status Register bits description

Bit Symbol Description

7 LSR[7] FIFO data error.

6 LSR[6] THR and TSR empty. This bit is the Transmit Empty indicator. This

5 LSR[5] THR empty. This bit is the Transmit Holding Register Empty

4 LSR[4] Break interrupt.

3 LSR[3] Framing error.

2 LSR[2] Parity error.

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

Logic 0 = No error (normal default condition). Logic 1 = At least one parity error, framing error or break

indication is in the current FIFO data. This bit is cleared when there are no remaining error ﬂags associated with the remaining data in the FIFO.

bit is set to a logic 1 whenever the transmit holding register and the transmit shift register are both empty. It is reset to logic 0 whenever either the THR or TSR contains a data character. In the FIFO mode, this bit is set to ‘1’ whenever the transmit FIFO and transmit shift register are both empty.

indicator.This bit indicates that the UART is ready to accept a new character for transmission. In addition, this bit causes the UARTto issue an interrupt to CPU when the THR interrupt enable is set. The THR bit is set to a logic 1 when a character is transferred from the transmit holding register into the transmitter shift register. The bit is reset to a logic 0 concurrently with the loading of the transmitter holding register by the CPU. In the FIFO mode, this bit is set when the transmit FIFO is empty; it is cleared when at least 1 byte is written to the transmit FIFO.

Logic 0 = No break condition (normal default condition). Logic 1 = The receiver received a break signal (RX was a logic 0

for one character frame time). In the FIFO mode, only one break character is loaded into the FIFO.

Logic 0 = No framing error (normal default condition). Logic 1 = Framing error. The receive character did not have a

valid stop bit(s). In the FIFO mode, this error is associated with the character at the top of the FIFO.

Logic 0 = No parity error (normal default condition. Logic 1 = Parity error. The receive character does not have

correct parity information and is suspect. In the FIFO mode, this error is associated with the character at the top of the FIFO.

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SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

Table 18: Line Status Register bits description

Bit Symbol Description

1 LSR[1] Overrun error.

Logic 0 = No overrun error (normal default condition). Logic1=Overrun error. A data overrun error occurred in the

receive shift register.This happens when additional data arrives while the FIFO is full. In this case, the previous data in the shift register is overwritten. Note that under this condition, the data byte in the receive shift register is not transferred into the FIFO, therefore the data in the FIFO is not corrupted by the error.

0 LSR[0] Receive data ready.

Logic 0 = No data in receive holding register or FIFO (normal default condition).

Logic 1 = Data has been received and is saved in the receive holding register or FIFO.

…continued

7.8 Modem Status Register (MSR)

This register provides the current state of the control interface signals from the modem, or other peripheral device to which the SC16C2550 is connected. Four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a control input from the modem changes state. These bits are set to a logic 0 whenever the CPU reads this register.

Table 19: Modem Status Register bits description

Bit Symbol Description

7 MSR[7] CD. During normal operation, this bit is the complement of the

input. Reading this bit in the loop-back mode produces the state of MCR[3] (

6 MSR[6] RI. During normal operation, this bit is the complement of the

input. Reading this bit in the loop-back mode produces the state of MCR[2] (

5 MSR[5] DSR. During normal operation, this bit is the complement of the

DSR input. During the loop-back mode, this bit is equivalent to MCR[0] (

4 MSR[4] CTS. During normal operation, this bit is the complement of the

CTS input. During the loop-back mode, this bit is equivalent to MCR[1] (

3 MSR[3] ∆

2 MSR[2] ∆

OP2).

OP1).

DTR).

RTS).

[1]

Logic 0 = No CD change (normal default condition). Logic 1 = The

since the last time it was read. A modem Status Interrupt will be generated.

[1]

Logic 0 = No RI change (normal default condition). Logic 1 = The

logic 0 to a logic 1. A modem Status Interrupt will be generated.

CD input to the SC16C2550 has changed state

RI input to the SC16C2550 has changed from a

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SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

Table 19: Modem Status Register bits description

Bit Symbol Description

1 MSR[1] ∆DSR

0 MSR[0] ∆

[1] Whenever any MSR bit 0-3 is set to logic 1, a Modem Status Interrupt will be generated.

[1]

Logic 0 = No DSR change (normal default condition). Logic1=The

since the last time it was read. A modem Status Interrupt will be generated.

[1]

CTS

Logic 0 = No CTS change (normal default condition). Logic 1 = The

since the last time it was read. A modem Status Interrupt will be generated.

DSR input to the SC16C2550 has changed state

CTS input to the SC16C2550 has changed state

7.9 Scratchpad Register (SPR)

The SC16C2550 provides a temporary data register to store 8 bits of user information.

7.10 Enhanced Feature Register (EFR)

Enhanced features are enabled or disabled using this register.

…continued

Bits 0 through 4 provide single or dual character software ﬂow control selection. When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double 8-bit words are concatenated into two sequential numbers.

Table 20: Enhanced Feature Register bits description

Bit Symbol Description

7 EFR[7] Automatic CTS ﬂow control.

Logic0=Automatic CTS ﬂow control is disabled (normal default condition).

Logic 1 = Enable Automatic CTS ﬂow control. Transmission will stop

CTS goes to a logical 1. Transmission will resume when the CTS

when pin returns to a logical 0.

6 EFR[6] Automatic RTS ﬂow control. Automatic RTS may be used for hardware ﬂow

control by enabling EFR[6]. When Auto-RTS is selected, an interrupt will be generated when the receive FIFO is ﬁlled to the programmed trigger leveland a logic 0 when data is unloaded below the next lower trigger level (programmed trigger level 1). The state of this register bit changes with the status of the hardware ﬂow control. hardware ﬂow control is disabled.

RTS will go to a logic 1 at the next trigger level. RTS will return to

RTS functions normally when

0 = Automatic RTS ﬂow control is disabled (normal default condition). 1 = Enable Automatic RTS ﬂow control.

9397 750 11621

Product data Rev. 03 — 19 June 2003 27 of 46

Philips Semiconductors

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

Table 20: Enhanced Feature Register bits description

Bit Symbol Description

5 EFR[5] Special Character Detect.

Logic 0 = Special character detect disabled (normal default condition). Logic 1 = Special character detect enabled. The SC16C2550 compares

each incoming receive character with Xoff2 data. If a match exists, the received data will be transferred to FIFO and ISR[4] will be set to indicate detection of special character. Bit-0 in the X-registers corresponds with the LSB bit for the receivecharacter.Whenthis feature is enabled, the normal software ﬂow control must be disabled (EFR[3-0] must be set to a logic 0).

4 EFR[4] Enhanced function control bit. The content of IER[7-4], ISR[5-4], FCR[5-4],

and MCR[7-5] can be modiﬁed and latched. After modifying any bits in the enhanced registers, EFR[4] can be set to a logic 0 to latch the new values. This feature prevents existing software from altering or overwriting the SC16C2550 enhanced functions.

Logic 0 = disable/latch enhanced features. IER[7-4], ISR[5-4], FCR[5-4], and MCR[7-5] are saved to retain the user settings, then IER[7-4] ISR[5-4], FCR[5-4], and MCR[7-5] are set to a logic 0 to be compatible with SC16C554 mode. (Normal default condition.)

Logic 1 = Enables the enhanced functions. When this bit is set to a logic 1, all enhanced features of the SC16C2550 are enabled and user settings stored during a reset will be restored.

3-0 EFR[3-0] Cont-3-0 Tx, Rx control. Logic 0 or cleared is the default condition.

Combinations of software ﬂow control can be selected by programming these bits. See Table 21.

…continued

Table 21: Software ﬂow control functions

Cont-3 Cont-2 Cont-1 Cont-0 TX, RX software ﬂow controls

0 0 X X No transmit ﬂow control 1 0 X X Transmit Xon1/Xoff1 0 1 X X Transmit Xon2/Xoff2 1 1 X X Transmit Xon1 and Xon2/Xoff1 and Xoff2 X X 0 0 No receive ﬂow control X X 1 0 Receiver compares Xon1/Xoff1 X X 0 1 Receiver compares Xon2/Xoff2 1 0 1 1 Transmit Xon1/Xoff1

0 1 1 1 Transmit Xon2/Xoff2

1 1 1 1 Transmit Xon1 and Xon2/Xoff1 and Xoff2

[1] When using a software ﬂow control the Xon/Xoff characters cannot be used for data transfer.

[1]

Receiver compares Xon1 and Xon2, Xoff1 and Xoff2

Receiver compares Xon1 and Xon2/Xoff1 and Xoff2

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Product data Rev. 03 — 19 June 2003 28 of 46

Philips Semiconductors

7.11 SC16C2550 external reset condition

Table 22: Reset state for registers

IER IER[7-0] = 0 FCR FCR[7-0] = 0 ISR ISR[7-1] = 0; ISR[0] = 1 LCR LCR[7-0] = 0 MCR MCR[7-0] = 0 LSR LSR[7] = 0; LSR[6-5] = 1; LSR[4-0] = 0 MSR MSR[7-4] = input signals; MSR[3-0] = 0 SPR SFR[7-0] = 1 DLL DLL[7-0] = X DLM DLM[7-0] = X

Table 23: Reset state for outputs

Output Reset state

TXA, TXB Logic 1 OP2A, OP2B Logic 1 RTSA, RTSB Logic 1 DTRA, DTRB Logic 1 INTA, INTB 3-State condition

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

8. Limiting values

Table 24: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

amb

stg

tot(pack)

supply voltage - 7 V voltage at any pin GND − 0.3 VCC+ 0.3 V operating temperature −40 +85 °C storage temperature −65 +150 °C total power dissipation

per package

- 500 mW

9397 750 11621

Product data Rev. 03 — 19 June 2003 29 of 46

Philips Semiconductors

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

9. Static characteristics

Table 25: DC electrical characteristics

=−40°C to +85°C; VCC= 2.5 V, 3.3 V or 5.0 V±10%, unless otherwise speciﬁed.

amb

Symbol Parameter Conditions 2.5 V 3.3 V 5.0 V Unit

Min Max Min Max Min Max

IL(CK)

IH(CK)

LIL

LOW-level clock input voltage −0.3 0.45 −0.3 0.6 −0.5 0.6 V HIGH-level clock input voltage 1.8 V LOW-level input voltage

−0.3 0.65 −0.3 0.8 −0.5 0.8 V

2.4 V

3.0 V

(except X1 clock) HIGH-level input voltage

1.6 - 2.0 - 2.2 - V

(except X1 clock) LOW-level output voltage

on all outputs

[1]

IOL=5mA (databus)

=4mA

-----0.4V

---0.4--V

(other outputs) I

=2mA

-0.4----V

(databus) I

= 1.6 mA

-0.4----V

(other outputs)

HIGH-level output voltage IOH= −5mA

----2.4-V

(databus) I

= −1mA

--2.0---V

(other outputs) I

= −800 µA

1.85 -----V

(data bus) I

= −400 µA

1.85 -----V

(other outputs)

LOW-level input leakage

- ±10 - ±10 - ±10 µA

current clock leakage - ±30 - ±30 - ±30 µA supply current f = 5 MHz - 3.5 - 4.5 - 4.5 mA input capacitance - 5 - 5 - 5 pF

[1] Except x2, VOL= 1 V typical.

9397 750 11621

Product data Rev. 03 — 19 June 2003 30 of 46

Philips Semiconductors

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

10. Dynamic characteristics

Table 26: AC electrical characteristics

=−40°C to +85°C; VCC= 2.5 V, 3.3 V or 5.0 V±10%, unless otherwise speciﬁed.

amb

Symbol Parameter Conditions 2.5 V 3.3 V 5.0 V Unit

Min Max Min Max Min Max

, t

12d

12h

13d

13w

13h

15d

16s

16h

17d

18d

19d

20d

21d

22d

23d

24d

25d

26d

27d

28d

RESET

N baud rate divisor 1 2

clock pulse duration 10 - 6 - 6 - ns

oscillator/clock frequency

[1]

- 48 - 80 80 MHz address set-up time 0 - 0 - 0 - ns address hold time 0 - 0 - 0 - ns IOR delay from chip select 10 - 10 - 10 - ns IOR strobe width 25 pF load 77 - 26 - 23 - ns chip select hold time from IOR 0 - 0 - 0 - ns read cycle delay 25 pF load 20 - 20 - 20 - ns delay from IOR to data 25 pF load - 77 - 26 - 23 ns data disable time 25 pF load - 15 - 15 - 15 ns IOW delay from chip select 10 - 10 - 10 - ns IOW strobe width 20 -

[2]

20 -

[2]

15 -

[2]

chip select hold time from IOW 0-0-0-ns write cycle delay

[3]

25 - 25 - 20 - ns data set-up time 20 - 20 - 15 - ns data hold time 15 - 5 - 5 - ns delay from IOW to output 25 pF load - 100 - 33 - 29 ns delay to set interrupt from Modem

25 pF load - 100 - 24 - 23 ns

input delay to reset interrupt from IOR 25 pF load - 100 - 24 - 23 ns delay from stop to set interrupt - 1 - 1 - 1 R delay from IOR to reset interrupt 25 pF load - 100 - 29 - 28 ns delay from start to set interrupt - 100 - 45 - 40 ns delay from IOW to transmit start 8 24 8 24 8 24 R delay from IOW to reset interrupt - 100 - 45 - 40 ns delay from stop to set RXRDY -1-1-1R delay from IOR to reset RXRDY - 100 - 45 - 40 ns delay from IOW to set TXRDY - 100 - 45 - 40 ns delay from start to reset TXRDY -8-8-8R Reset pulse width 200 - 40 - 40 - ns

− 11 216− 11 216− 1R

clk

[1] Applies to external clock, crystal oscillator max 24 MHz. [2]

IOWstrobe

= 333 ns (for Baudrate = 1 µs (for Baudrate = 4 µs (for Baudrate

[3] When in both DMA mode 0 and FIFO enable mode, the write cycle delay should be larger than one x1, clock cycle.

9397 750 11621

Product data Rev. 03 — 19 June 2003 31 of 46

max

--------------------------------------

2 Baudrate

()

max max max

max

= 1.5 Mbits/s) = 460.8 kbits/s) = 115.2 kbits/s)

Philips Semiconductors

10.1 Timing diagrams

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

A0–A2

CSx

IOW

D0–D7

Fig 7. General write timing.

A0–A2

VALID

ADDRESS

13h

ACTIVE

13d

ACTIVE

VALID

ADDRESS

13w

16h

16s

DATA

15d

002aaa109

12d

ACTIVE

DATA

12h

002aaa110

CSx

IOR

D0–D7

Fig 8. General read timing.

9397 750 11621

Product data Rev. 03 — 19 June 2003 32 of 46

Philips Semiconductors

ACTIVEIOW

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

17d

RTS

DTR

DCD CTS DSR

INT

CHANGE OF STATE CHANGE OF STATE

Fig 9. Modem input/output timing.

CHANGE OF STATE CHANGE OF STATE

18d

ACTIVE ACTIVE ACTIVE

ACTIVE ACTIVE ACTIVEIOR

18d

19d

18d

CHANGE OF STATE

002aaa111

EXTERNAL

CLOCK

002aaa112

Fig 10. External clock timing.

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Product data Rev. 03 — 19 June 2003 33 of 46

Philips Semiconductors

START

BIT

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

NEXT DATA

START

STOP

DATA BITS (5-8)

PARITY

BIT

INT

IOR

Fig 11. Receive timing.

D0 D1 D2 D3 D4 D5 D6 D7

5 DATA BITS

6 DATA BITS

7 DATA BITS

16 BAUD RATE CLOCK

20d

ACTIVE

21d

ACTIVE

002aaa113

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Product data Rev. 03 — 19 June 2003 34 of 46

Philips Semiconductors

START

BIT

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

NEXT DATA

START

STOP

DATA BITS (5–8)

PARITY

BIT

RXRDY

IOR

D0 D1 D2 D3 D4 D5 D6 D7

Fig 12. Receive ready timing in non-FIFO mode.

START

BIT

DATA BITS (5–8)

PARITY

BIT

STOP

BIT

25d

ACTIVE

DATA

READY

ACTIVE

26d

002aaa114

RXRDY

IOR

D0 D1 D2 D3 D4 D5 D6 D7

FIRST BYTE THAT REACHES THE TRIGGER LEVEL

25d

ACTIVE

DATA

READY

26d

ACTIVE

002aaa115

Fig 13. Receive ready timing in FIFO mode.

9397 750 11621

Product data Rev. 03 — 19 June 2003 35 of 46

Philips Semiconductors

START

BIT

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

NEXT DATA

START

BIT

STOP

BIT

PARITY

DATA BITS (5–8)

INT

IOW

ACTIVE

Fig 14. Transmit timing.

D0 D1 D2 D3 D4 D5 D6 D7

5 DATA BITS

6 DATA BITS

7 DATA BITS

ACTIVE TX READY

22d

23d

16 BAUD RATE CLOCK

24d

ACTIVE

002aaa116

9397 750 11621

Product data Rev. 03 — 19 June 2003 36 of 46

Philips Semiconductors

START

BIT

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

DATA

START

STOP

DATA BITS (5-8)

PARITY

BIT

IOW

D0–D7 BYTE #1

TXRDY

ACTIVE

27d

D0 D1 D2 D3 D4 D5 D6 D7

TRANSMITTER

NOT READY

Fig 15. Transmit ready timing in non-FIFO mode.

ACTIVE

TRANSMITTER READY

002aaa117

9397 750 11621

Product data Rev. 03 — 19 June 2003 37 of 46

Philips Semiconductors

START

BIT

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

STOP

PARITY

DATA BITS (5-8)

BIT

IOW

D0–D7 BYTE #16

TXRDY

ACTIVE

27d

D0 D1 D2 D3 D4 D5 D6 D7

5 DATA BITS

6 DATA BITS

7 DATA BITS

28d

FIFO FULL

Fig 16. Transmit ready timing in FIFO mode (DMA mode ‘1’).

002aaa118

9397 750 11621

Product data Rev. 03 — 19 June 2003 38 of 46

Philips Semiconductors

11. Package outline

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

DIP40: plastic dual in-line package; 40 leads (600 mil)

seating plane

pin 1 index

SOT129-1

w M

(e )

0 5 10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

UNIT

inches

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

max.

OUTLINE

VERSION

SOT129-1

1 2

min.

max.

IEC JEDEC JEITA

051G08 MO-015 SC-511-40

1.70

1.14

0.067

0.045

0.53

0.38

0.021

0.015

cD E e M

0.36

0.23

0.014

0.009

REFERENCES

52.5

51.5

2.067

2.028

Fig 17. DIP40 package outline (SOT129-1).

14.1

13.7

0.56

0.54

(1)(1)

3.60

3.05

0.14

0.12

15.80

15.24

0.62

0.60

EUROPEAN

PROJECTION

17.42

15.90

0.69

0.63

0.2542.54 15.24

0.010.1 0.6

ISSUE DATE

99-12-27 03-02-13

max.

2.254.7 0.51 4

0.089 0.19 0.02 0.16

(1)

9397 750 11621

Product data Rev. 03 — 19 June 2003 39 of 46

Philips Semiconductors

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

PLCC44: plastic leaded chip carrier; 44 leads

pin 1 index

717

2939

SOT187-2

w M

detail X

(A )

v M

0 5 10 mm

scale

DIMENSIONS (mm dimensions are derived from the original inch dimensions)

(1)

UNIT A

0.180

inches

0.165

4.57

4.19

min.

0.51

0.02

0.25

0.01

4 max.

3.05

0.12

0.53

0.33

0.021

0.013

0.81

0.66

0.032

0.026

(1)E(1)

16.66

16.51

0.656

0.650

eywv β

eDe

16.66

16.51

0.656

0.650

1.27

0.05

16.00

14.99

0.63

0.59

16.00

14.99

0.63

0.59

HDH

17.65

17.40

0.695

0.685

17.65

17.40

0.695

0.685

1.22

1.07

0.048

0.042

1.44

1.02

0.057

0.040

0.18 0.10.18

0.007 0.0040.007

max.

2.16

0.085

max.

2.16

0.085

(1)

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

OUTLINE VERSION

SOT187-2

IEC JEDEC JEITA

112E10 MS-018 EDR-7319

REFERENCES

EUROPEAN

PROJECTION

ISSUE DATE

99-12-27 01-11-14

Fig 18. PLCC44 package outline (SOT187-2).

9397 750 11621

Product data Rev. 03 — 19 June 2003 40 of 46

Philips Semiconductors

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm

pin 1 index

w M

SOT313-2

(A )

DIMENSIONS (mm are the original dimensions)

UNIT

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

A1A2A3bpcE

max.

0.20

0.05

1.45

1.35

1.6

OUTLINE VERSION

SOT313-2 MS-026136E05

IEC JEDEC JEITA

0.25

w M

0.27

0.17

0 2.5 5 mm

(1)

(1) (1)(1)

7.1

0.18

0.12

7.1

6.9

REFERENCES

v M

scale

eHELL

9.15

0.5

8.85

detail X

Zywv θ

0.95

0.55

0.95

0.55

ISSUE DATE

00-01-19 03-02-25

o o

0.75

0.45

0.12 0.10.21

EUROPEAN

PROJECTION

9.15

8.85

Fig 19. LQFP48 package outline (SOT313-2).

9397 750 11621

Product data Rev. 03 — 19 June 2003 41 of 46

Philips Semiconductors

12. Soldering

12.1 Introduction

This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our

Packages

There is no soldering method that is ideal for all IC packages. Wavesoldering is often preferred when through-hole and surface mount components are mixed on one printed-circuit board. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for ﬁne pitch SMDs. In these situations reﬂow soldering is recommended. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing.

12.2 Through-hole mount packages

12.2.1 Soldering by dipping or by solder wave

Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

Data Handbook IC26; Integrated Circuit

(document order number 9398 652 90011).

The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the

plastic body must not exceed the speciﬁed maximum storage temperature (T If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit.

12.2.2 Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds.

12.3 Surface mount packages

12.3.1 Reﬂow soldering

Reﬂow soldering requires solder paste (a suspension of ﬁne solder particles, ﬂux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.

Several methods exist for reﬂowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method.

stg(max)

Typical reﬂow peak temperatures range from 215 to 270 °C depending on solder paste material. The top-surface temperature of the packages should preferably be kept:

• below 220 °C (SnPb process) or below 245 °C (Pb-free process)

– for all the BGA and SSOP-T packages

9397 750 11621

Product data Rev. 03 — 19 June 2003 42 of 46

Philips Semiconductors

• below 235 °C (SnPb process) or below260 °C (Pb-free process) for packages with

Moisture sensitivity precautions, as indicated on packing, must be respected at all times.

12.3.2 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems.

To overcome these problems the double-wave soldering method was speciﬁcally developed.

If wave soldering is used the following conditions must be observed for optimal results:

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

– for packages with a thickness ≥ 2.5 mm – for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called

thick/large packages.

a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages.

• Use a double-wave soldering method comprising a turbulent wave with high

upward pressure followed by a smooth laminar wave.

• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

• For packages with leads on four sides, the footprint must be placed at a 45° angle

to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners.

During placement and before soldering, the package must be ﬁxed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated ﬂux will eliminate the need for removal of corrosive residues in most applications.

12.3.3 Manual soldering

Fix the component by ﬁrst soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the ﬂat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.

9397 750 11621

Product data Rev. 03 — 19 June 2003 43 of 46

Philips Semiconductors

12.4 Package related soldering information

Table 27: Suitability of IC packages for wave, reﬂow and dipping soldering methods

Mounting Package

Through-hole mount

Surface mount BGA, LBGA, LFBGA,

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

[1]

DBS, DIP, HDIP, SDIP, SIL suitable

SQFP, SSOP-T

[4]

TFBGA, VFBGA DHVQFN, HBCC, HBGA,

HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS

[6]

PLCC

, SO, SOJ suitable suitable − LQFP, QFP, TQFP not recommended SSOP, TSSOP, VSO,

VSSOP

Soldering method Wave Reﬂow

[3]

− suitable

[2]

not suitable suitable −

not suitable

[5]

not recommended

[6][7] [8]

suitable −

suitable − suitable −

Dipping

[1] For more detailed information on the BGA packages refer to the

(AN01026); order a copy from your Philips Semiconductors sales ofﬁce.

[2] All surface mount (SMD) packages are moisture sensitive.Depending upon the moisture content, the

maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the

Circuit Packages; Section: Packing Methods

[3] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the

printed-circuit board.

[4] These transparent plastic packages are extremely sensitive to reﬂow soldering conditions and must

on no account be processed through more than one soldering cycle or subjected to infrared reﬂow soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reﬂow oven. The package body peak temperature must be kept as low as possible.

[5] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom

side, the solder cannot penetrate betweentheprinted-circuit board and the heatsink. On versionswith the heatsink on the top side, the solder might be deposited on the heatsink surface.

[6] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[7] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it

is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.65mm.

[8] Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than

0.65 mm; it is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

(LF)BGA Application Note

Data Handbook IC26; Integrated

13. Revision history

Table 28: Revision history

Rev Date CPCN Description

03 20030619 - Product data (9397 750 11621). ECN 853-2368 30033 of 16 June 2003.

Modiﬁcations:

• Figure 5 “Crystal oscillator connection.” on page 13: changed capacitors’ values and

added connection with resistor.

02 20030314 - Product data (9397 750 11204). ECN 853-2368 29624 of 07 March 2003. 01 20020904 - Product data (9397 750 08831). ECN 853-2368 28865 of 04 September 2002.

9397 750 11621

Product data Rev. 03 — 19 June 2003 44 of 46

Philips Semiconductors

14. Data sheet status

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

Level Data sheet status

I Objective data Development This data sheet contains data from the objective speciﬁcation for product development. Philips

II Preliminary data Qualiﬁcation This datasheet contains data from the preliminary speciﬁcation. Supplementary data will bepublished

III Product data Production This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

[1]

Product status

15. Deﬁnitions

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook.

Limiting values deﬁnition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the speciﬁed use without further testing or modiﬁcation.

[2][3]

Deﬁnition

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

at a later date.Philips Semiconductors reserves the right to change the speciﬁcation without notice, in order to improve the design and supply the best possible product.

right to make changes at anytime in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

16. Disclaimers

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes norepresentations or warrantiesthat these productsare free frompatent, copyright, or mask work right infringement, unless otherwise speciﬁed.

Contact information

For additional information, please visit http://www.semiconductors.philips.com. For sales ofﬁce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com. Fax: +31 40 27 24825

9397 750 11621

Product data Rev. 03 — 19 June 2003 45 of 46

Philips Semiconductors

Contents

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

6 Functional description . . . . . . . . . . . . . . . . . . . 9

6.1 UART A-B functions . . . . . . . . . . . . . . . . . . . . . 9

6.2 Internal registers. . . . . . . . . . . . . . . . . . . . . . . 10

6.3 FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . 11

6.4 Hardware ﬂow control. . . . . . . . . . . . . . . . . . . 11

6.5 Software ﬂow control . . . . . . . . . . . . . . . . . . . 11

6.6 Special feature software ﬂow control . . . . . . . 12

6.7 Hardware/software and time-out interrupts. . . 12

6.8 Programmable baud rate generator . . . . . . . . 13

6.9 DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 14

6.10 Loop-back mode. . . . . . . . . . . . . . . . . . . . . . . 14

7 Register descriptions . . . . . . . . . . . . . . . . . . . 16

7.1 Transmit (THR) and Receive (RHR)

Holding Registers . . . . . . . . . . . . . . . . . . . . . 17

7.2 Interrupt Enable Register (IER) . . . . . . . . . . . 17

7.2.1 IER versus Transmit/Receive FIFO interrupt

mode operation . . . . . . . . . . . . . . . . . . . . . . . 18

7.2.2 IER versus Receive/Transmit FIFO polled

mode operation . . . . . . . . . . . . . . . . . . . . . . . 19

7.3 FIFO Control Register (FCR) . . . . . . . . . . . . . 19

7.3.1 DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.3.2 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.4 Interrupt Status Register (ISR) . . . . . . . . . . . . 21

7.5 Line Control Register (LCR) . . . . . . . . . . . . . . 22

7.6 Modem Control Register (MCR). . . . . . . . . . . 24

7.7 Line Status Register (LSR). . . . . . . . . . . . . . . 25

7.8 Modem Status Register (MSR). . . . . . . . . . . . 26

7.9 Scratchpad Register (SPR) . . . . . . . . . . . . . . 27

7.10 Enhanced Feature Register (EFR) . . . . . . . . . 27

7.11 SC16C2550 external reset condition . . . . . . . 29

8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 29

9 Static characteristics . . . . . . . . . . . . . . . . . . . 30

10 Dynamic characteristics. . . . . . . . . . . . . . . . . 31

10.1 Timing diagrams. . . . . . . . . . . . . . . . . . . . . . . 32

11 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 39

12 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 42

12.2 Through-hole mount packages . . . . . . . . . . . 42

12.2.1 Soldering by dipping or by solder wave . . . . . 42

12.2.2 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 42

12.3 Surface mount packages . . . . . . . . . . . . . . . . 42

12.3.1 Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 42

12.3.2 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 43

12.3.3 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 43

12.4 Package related soldering information. . . . . . 44

13 Revision history . . . . . . . . . . . . . . . . . . . . . . . 44

14 Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 45

15 Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

Date of release: 19 June 2003 Document order number: 9397 750 11621

Philips SC16C2550 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual