Dual UART with 16 bytes of transmit and receive FIFOs
and infrared (IrDA) encoder/decoder
Rev. 03 — 19 June 2003Product data
The SC16C2550 is a 2 channel Universal Asynchronous Receiver and Transmitter
(UART) used for serial data communications. Its principal function is to convert
parallel data into serial data and vice versa. The UART can handle serial data rates
up to 5 Mbits/s.
The SC16C2550 is pin compatible with the ST16C2550. It will power-up to be
functionally equivalent to the 16C2450. The SC16C2550 provides enhanced UART
functions with 16-byte FIFOs, modemcontrol interface, DMA mode data transfer. The
DMA mode data transfer is controlled by the FIFO trigger levels and the TXRDY and
RXRDY signals. On-board status registers provide the user with error indications and
operational status. System interrupts and modem control features may be tailored by
software to meet specific user requirements. An internal loop-back capability allows
on-board diagnostics. Independent programmable baud rate generators are provided
to select transmit and receive baud rates.
2.Features
The SC16C2550 operates at 5 V, 3.3 V and 2.5 V and the Industrial temperature
range, and is available in plastic PLCC44, LQFP48 and DIP40 packages.
■ 2 channel UART
■ 5 V, 3.3 V and 2.5 V operation
■ Industrial temperature range
■ Pin and functionally compatible to 16C2450 and software compatible with
INS8250, SC16C550
■ Up to 5 Mbits/s data rate at 5 V and 3.3 V, and 3 Mbits/s at 2.5 V
■ 16 byte transmit FIFO to reduce the bandwidth requirement of the external CPU
■ 16 byte receive FIFO with error flags to reduce the bandwidth requirement of the
external CPU
■ Independent transmit and receive UART control
■ Four selectable Receive FIFO interrupt trigger levels
■ Automatic software/hardware flow control
■ Programmable Xon/Xoff characters
■ Software selectable Baud Rate Generator
■ Sleep mode
■ Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun
Break)
■ Transmit, Receive, Line Status, and Data Set interrupts independently controlled
Philips Semiconductors
SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
■ Fully programmable character formatting:
◆ 5-, 6-, 7-, or 8-bit characters
◆ Even-, Odd-, or No-Parity formats
◆ 1-, 11⁄2-, or 2-stop bit
◆ Baud generation (DC to 1.5 Mbit/s)
■ False start-bit detection
■ Complete status reporting capabilities
■ 3-State output TTL drive capabilities for bi-directional data bus and control bus
■ Line Break generation and detection
■ Internal diagnostic capabilities:
◆ Loop-back controls for communications link fault isolation
■ Prioritized interrupt system controls
■ Modem control functions (CTS, RTS, DSR, DTR, RI, DCD).
A0283128IAddress 0 select bit. Internal register address selection.
A1273027IAddress 1 select bit. Internal register address selection.
A2262926IAddress 2 select bit. Internal register address selection.
CSA, CSB 14, 15 16, 1710, 11IChip Select A, B (Active-LOW).This function is associated with individual
channels, A through B. These pins enable data transfers between the user
CPU and the SC16C2550 for the channel(s) addressed. Individual UART
sections (A, B) are addressed by providing a logic 0 on the respective
CSB pin.
D0-D71-82-944-48,
1-3
I/OData bus (bi-directional). These pins are the 8-bit, 3-State data bus for
transferring information to or from the controlling CPU. D0 is the least
significant bit and the first data bit in a transmit or receive serial data
stream.
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
Table 2:Pin description
SymbolPinType Description
DIP40 PLCC44 LQFP48
INTA,
INTB
IOR212419IRead strobe (Active-LOW strobe). A logic 0 transition on this pin will load
IOW182015IWrite strobe (Active-LOW strobe). A logic 0 transition on this pin will
OP2A,
OP2B
RESET353936IReset (Active-HIGH). A logic 1 on this pin will reset the internal registers
RXRDYA,
RXRDYB
TXRDYA,
TXRDYB
V
CC
XTAL1161813ICrystal or external clock input. Functions as a crystal input or as an
30, 29 33, 3230, 29OInterrupt A, B (3-State). This function is associated with individual channel
31, 13 35, 1532, 9OOutput 2 (user-defined). This function is associated with individual
-34, 2331, 18OReceive Ready A, B (Active-LOW). This function is associated with
-1, 1243, 6OTransmit Ready A, B (Active-LOW). This function is associated with
404442IPower supply input.
…continued
interrupts, INTA, INTB. INTA, INTB are enabled when MCR bit 3 is set to a
logic 1, interrupts are enabled in the interrupt enable register (IER), and is
active when an interrupt condition exists. Interrupt conditions include:
receiver errors, available receiver buffer data, transmit buffer empty, or
when a modem status flag is detected.
the contents of an internal register defined by address bits A0-A2 onto the
SC16C2550 data bus (D0-D7) for access by external CPU.
transfer the contents of the data bus (D0-D7) from the external CPU to an
internal register that is defined by address bits A0-A2.
channels, A through B. The state at these pin(s) are defined by the user
and through MCR register bit 3. INTA, INTB are set to the active mode and
OP2 to logic 0 when MCR[3] is set to a logic 1. INTA, INTB are set to the
3-State mode and
bit 3, Modem Control Register (MCR[3]). Since these bits control both the
INTA, INTB operation and
at one time, INT or
and all the outputs. The UART transmitter output and the receiver input will
be disabled during reset time. (See Section 7.11 “SC16C2550 external
reset condition” for initialization details.)
PLCC44 and LQFP48 packages only. This function provides the
RX FIFO/RHR status for individual receive channels (A-B).
primarily intended for monitoring DMA mode 1 transfersforthe receivedata
FIFOs. A logic 0 indicates there is a receive data to read/upload, i.e.,
receive ready status with one or more RX characters available in the
FIFO/RHR. This pin is a logic 1 when the FIFO/RHR is empty or when the
programmed trigger level has not been reached. This signal can also be
used for single mode transfers (DMA mode 0).
PLCC44 and LQFP48 packages only. These outputs provide the
TX FIFO/THR status for individual transmit channels (A-B).
primarily intended for monitoring DMA mode 1 transfers for the transmit
data FIFOs. An individual channel’s
is indicated by logic 0, i.e., at lease one location is empty and available in
the FIFO or THR. This pin goes to a logic 1 (DMA mode 1) when there are
no more empty locations in the FIFO or THR. This signal can also be used
for single mode transfers (DMA mode0).
external clock input. A crystal can be connected between this pin and
XTAL2 to form an internal oscillator circuit. This configuration requires an
external 1 MΩ resistor between the XTAL1 and XTAL2 pins. Alternatively,
an external clock can be connected to this pin to provide custom data rates.
(See Section 6.8 “Programmable baud rate generator”.) See Figure 5.
OP2 to a logic 1 when MCR[3] is set to a logic 0. See
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
Table 2:Pin description
SymbolPinType Description
DIP40 PLCC44 LQFP48
XTAL2171914OOutput of the crystal oscillator or buffered clock. (See also XTAL1.)
CDA,
CDB
CTSA,
CTSB
DSRA,
DSRB
DTRA,
DTRB
RIA, RIB39, 23 43, 2641, 21IRing Indicator (Active-LOW). These inputs are associated with individual
RTSA,
RTSB
RXA, RXB 10, 911, 105, 4IReceive data A, B. These inputs are associated with individual serial
TXA, TXB 11, 12 13, 147, 8OTransmit data A, B. These outputs are associated with individual serial
38, 19 42, 2140, 16ICarrier Detect (Active-LOW). These inputs are associated with individual
36, 25 40, 2838, 23IClear to Send (Active-LOW). These inputs are associated with individual
37, 22 41, 2539, 20IData Set Ready (Active-LOW). These inputs are associated with
33, 34 37, 3834, 35OData Terminal REady (Active-LOW). These outputs are associated with
32, 24 36, 2733, 22ORequest to Send (Active-LOW). These outputs are associated with
…continued
Crystal oscillator output or buffered clock output. Should be left open if an
external clock is connected to XTAL1. For extended frequency operation,
this pin should be tied to V
UART channels A through B. A logic 0 on this pin indicates that a carrier
has been detected by the modem for that channel.
UART channels, A through B. A logic 0 on the CTS pin indicates the
modem or data set is ready to accept transmit data from the SC16C2550.
Status can be tested by reading MSR[4]. This pin has no effect on the
UART’s transmit or receive operation.
individual UART channels, A through B. A logic 0 on this pin indicates the
modem or data set is powered-on and is ready for data exchange with the
UART. This pin has no effect on the UART’s transmit or receive operation.
individual UART channels, A through B. A logic 0 on this pin indicates that
the SC16C2550 is powered-on and ready. This pin can be controlled via
the modem control register. Writing a logic 1 to MCR[0] will set the
output to logic 0, enablingthe modem. This pin will be a logic 1 after writing
a logic 0 to MCR[0], or after a reset. This pin has no effect on the UART’s
transmit or receive operation.
UARTchannels, A through B. A logic 0 on this pin indicates the modem has
received a ringing signal from the telephone line. A logic 1 transition on this
input pin will generate an interrupt.
individual UART channels, A through B. A logic 0 on the RTS pin indicates
the transmitter has data ready and waiting to send. Writing a logic 1 in the
modem control register MCR[1] will set this pin to a logic 0, indicating data
is available. After a reset this pin will be set to a logic 1. This pin has no
effect on the UART’s transmit or receive operation.
channel data to the SC16C2550 receive input circuits, A-B. The RX signal
will be a logic 1 during reset, idle (no data), or when the transmitter is
disabled. During the local loop-back mode, the RX input pin is disabled and
TX data is connected to the UART RX input, internally.
transmit channel data from the SC16C2550. The TX signal will be a logic 1
during reset, idle (no data), or when the transmitter is disabled. During the
local loop-back mode, the TX output pin is disabled and TX data is
internally connected to the UART RX input.
The SC16C2550 provides serial asynchronous receive data synchronization,
parallel-to-serial and serial-to-parallel data conversions for both the transmitter and
receiver sections. These functions are necessary for converting the serial data
stream into parallel data that is required with digital data systems. Synchronization for
the serial data stream is accomplished by adding start and stop bits to the transmit
data to form a data character (character orientated protocol). Data integrity is insured
by attaching a parity bit to the data character.The parity bit is checked by the receiver
for any transmission bit errors. The electronic circuitry to provide all these functions is
fairly complex, especially when manufactured on a single integrated silicon chip. The
SC16C2550 represents such an integration with greatly enhanced features. The
SC16C2550 is fabricated with an advanced CMOS process.
The SC16C2550 is an upward solution that provides a dual UART capability with
16 bytes of transmit and receive FIFO memory, instead of none in the 16C2450. The
SC16C2550 is designed to work with high speed modems and shared network
environments that require fast data processing time. Increased performance is
realized in the SC16C2550 by the transmit and receive FIFOs. This allows the
external processor to handle more networking tasks within a given time. For example,
the ST16C2450 without a receive FIFO, will require unloading of the RHR in
93 microseconds (this example uses a character length of 11 bits, including start/stop
bits at 115.2 kbits/s). This means the external CPU will have to service the receive
FIFO less than every 100 microseconds. However, with the 16 byte FIFO in the
SC16C2550, the data buffer will not require unloading/loading for 1.53 ms. This
increases the service interval, giving the external CPU additional time for other
applications and reducing the overall UART interrupt servicing time. In addition, the
four selectable receive FIFO trigger interrupt levelsis uniquely provided for maximum
data throughput performance especially when operating in a multi-channel
environment. The FIFO memory greatly reduces the bandwidth requirement of the
external controlling CPU, increases performance, and reduces power consumption.
SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
The SC16C2550 is capable of operation up to 5 Mbits/s with a 80 MHz clock. With a
crystal or external clock input of 7.3728 MHz, the user can select data rates up to
460.8 kbits/s.
The rich feature set of the SC16C2550 is available through internal registers.
Selectable receive FIFO trigger levels,selectable TX and RX baud rates, and modem
interface controls are all standard features. Followinga power-on reset or an external
reset, the SC16C2550 is software compatible with the previous generation,
ST16C2450.
6.1 UART A-B functions
The UART provides the user with the capability to bi-directionally transfer information
between an external CPU, the SC16C2550 package,and an external serial device. A
logic 0 on chip select pins CSA and/or CSB allows the user to configure, send data,
and/or receive data via UART channels A-B. Individual channel select functions are
shown in Table 3.
CSA-CSB = 1none
CSA = 0UART channel A
CSB = 0UART channel B
6.2 Internal registers
The SC16C2550 provides two sets of internal registers (A and B) consisting of
12 registers each for monitoring and controlling the functions of each channel of the
UART. These registers are shown in Table 4. The UART registers function as data
holding registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO
control register (FCR), line status and control registers (LCR/LSR), modem status
and control registers (MCR/MSR), programmable data rate (clock) control registers
(DLL/DLM), and a user accessible scratchpad register (SPR).
Table 4:Internal registers decoding
A2A1A0READ modeWRITE mode
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)
000Receive Holding RegisterTransmit Holding Register
001Interrupt Enable Register
010Interrupt Status RegisterFIFO Control Register
011Line Control Register
100Modem Control Register
101Line Status Registern/a
110Modem Status Registern/a
111Scratchpad RegisterScratchpad Register
Baud rate register set (DLL/DLM)
000LSB of Divisor LatchLSB of Divisor Latch
001MSB of Divisor LatchMSB of Divisor Latch
Enhanced register set (EFR, Xon/off 1-2)
010Enhanced Feature RegisterEnhanced Feature Register
100Xon1 wordXon1 word
101Xon2 wordXon2 word
110Xoff1 wordXoff1 word
111Xoff2 wordXoff2 word
SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
[1]
[2]
[3]
[1] These registers are accessible only when LCR[7] is a logic 0.
[2] These registers are accessible only when LCR[7] is a logic 1.
[3] Enhanced Feature Register, Xon1, 2 and Xoff1, 2 are accessible only when the LCR is set to
The 16 byte transmit and receive data FIFOs are enabled by the FIFO Control
Register (FCR) bit 0. The user can set the receive trigger level via FCR bits 6-7, but
not the transmit trigger level. The receiver FIFO section includes a time-out function
to ensure data is delivered to the external CPU. An interrupt is generated whenever
the Receive Holding Register (RHR) has not been read following the loading of a
character or the receive trigger level has not been reached.
Table 5:Flow control mechanism
Selected trigger level
(characters)
1141
4484
88128
14141410
6.4 Hardware flow control
SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
INT pin activationNegate RTS or
send Xoff
Assert RTS or
send Xon
When automatic hardware flow control is enabled, the SC16C2550 monitors the CTS
pin for a remote buffer overflow indication and controls the RTS pin for local buffer
overflows. Automatic hardware flow control is selected by setting EFR[6] (RTS) and
EFR[7] (CTS) to a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating a
flow control request, ISR[5] will be set to a logic 1 (if enabled via IER[6,7]), and the
SC16C2550 will suspend TX transmissions as soon as the stop bit of the character in
process is shifted out. Transmission is resumed after the CTS input returns to a
logic 0, indicating more data may be sent.
With the Auto RTS function enabled, an interrupt is generated when the receive FIFO
reaches the programmed trigger level. The RTS pin will not be forced to a logic 1
(RTS off), until the receive FIFO reaches the next trigger level. However, the RTS pin
will return to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level
below the programmed trigger. However, under the above described conditions, the
SC16C2550 will continue to accept data until the receive FIFO is full.
6.5 Software flow control
When software flow control is enabled, the SC16C2550 compares one or two
sequential receive data characters with the programmed Xon/Xoff or Xoff1,2
character value(s). If received character(s) match the programmed values, the
SC16C2550 will halt transmission (TX) as soon as the current character(s) has
completed transmission. When a match occurs, the receive ready (if enabled via Xoff
IER[5]) flags will be set and the interrupt output pin (if receive interrupt is enabled) will
be activated. Following a suspension due to a match of the Xoff characters’ values,
the SC16C2550 will monitor the receive data stream for a match to the Xon1,2
character value(s). If a match is found, the SC16C2550 will resume operation and
clear the flags (ISR[4]).
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0.
Following reset, the user can write any Xon/Xoff value desired for software flow
control. Different conditions can be set to detect Xon/Xoff characters and
suspend/resume transmissions. When double 8-bit Xon/Xoff characters are selected,
the SC16C2550 compares two consecutive receive characters with two software flow
control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions
accordingly. Under the above described flow control mechanisms, flow control
characters are not placed (stacked) in the user accessible RX data buffer or FIFO.
In the eventthat the receive buffer is overfillingand flow control needs to be executed,
the SC16C2550 automatically sends an Xoff message (when enabled) via the serial
TX output to the remote modem. The SC16C2550 sends the Xoff1,2 characters as
soon as received data passes the programmed trigger level. To clear this condition,
the SC16C2550 will transmit the programmed Xon1,2 characters as soon as receive
data drops below the programmed trigger level.
6.6 Special feature software flow control
A special feature is provided to detect an 8-bit character when EFR[5] is set. When
8-bit character is detected, it will be placed on the user-accessible data stack along
with normal incoming RX data. This condition is selected in conjunction with
EFR[0-3]. Note that software flow control should be turned off when using this special
mode by setting EFR[0-3] to a logic 0.
SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
The SC16C2550 compares each incoming receive character with Xoff2 data. If a
match exists, the received data will be transferred to the FIFO, and ISR[4] will be set
to indicate detection of a special character. Although the Internal Register Table
(Table 7) shows each X-Register with eight bits of character information, the actual
number of bits is dependent on the programmed word length. Line Control Register
bits LCR[0-1] define the number of character bits, i.e., either 5 bits, 6 bits, 7 bits or
8 bits. The word length selected by LCR[0-1] also determine the number of bits that
will be used for the special character comparison. Bit 0 in the X-registers corresponds
with the LSB bit for the receive character.
6.7 Hardware/software and time-out interrupts
The interrupts are enabled by IER[0-3]. Care must be taken when handling these
interrupts. Following a reset, if Interrupt Enable Register (IER) bit 1 = 1, the
SC16C2550 will issue a Transmit Holding Register interrupt. This interrupt must be
serviced prior to continuing operations. The LSR register provides the current
singular highest priority interrupt only. It could be noted that CTS and RTS interrupts
have lowest interrupt priority. A condition can exist where a higher priority interrupt
may mask the lower priority CTS/RTS interrupt(s). Only after servicing the higher
pending interrupt will the lower priority CTS/RTS interrupt(s) be reflected in the status
register. Servicing the interrupt without investigating further interrupt conditions can
result in data errors.
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time Out have the same
interrupt priority (when enabled by IER[3]). The receiver issues an interrupt after the
number of characters have reached the programmed trigger level. In this case, the
SC16C2550 FIFO may hold more characters than the programmed trigger level.
Following the removal of a data byte, the user should re-check LSR[0] for additional
characters. A Receive Time Out will not occur if the receive FIFO is empty. The
time-out counter is reset at the center of each stop bit received or each time the
receive holding register (RHR) is read. The actual time-out value is 4 character time,
including data information length, start bit, parity bit, and the size of stop bit, i.e., 1×,
1.5×, or 2× bit times.
6.8 Programmable baud rate generator
The SC16C2550 supports high speed modem technologies that have increased input
data rates by employing data compression schemes. For example, a 33.6 kbit/s
modem that employs data compression may require a 115.2 kbit/s input data rate.
A 128.0 kbit/s ISDN modem that supports data compression may need an input
data rate of 460.8 kbit/s. The SC16C2550 can support a standard data rate of
921.6 kbit/s.
A single baud rate generator is provided for the transmitter and receiver, allowing
independent TX/RX channel control. The programmable Baud Rate Generator is
capable of operating with a frequency of up to 80 MHz. Toobtain maximum data rate,
it is necessary to use full rail swing on the clock input. The SC16C2550 can be
configured for internal or external clock operation. For internal clock oscillator
operation, an industry standard microprocessor crystal is connected externally
between the XTAL1 and XTAL2 pins. Alternatively, an external clock can be
connected to the XTAL1 pin to clock the internal baud rate generator for standard or
custom rates (see Table 6).
SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
The generator divides the input 16× clock by any divisor from 1 to 216− 1. The
SC16C2550 divides the basic external clock by 16. The basic 16× clock provides
table rates to support standard and custom applications using the same system
design. The rate table is configured via the DLL and DLM internal register functions.
Customized Baud Rates can be achieved by selecting the proper divisor values for
the MSB and LSB sections of baud rate generator.
Programming the Baud Rate Generator Registers DLM (MSB) and DLL (LSB)
provides a user capability for selecting the desired final baud rate. The example in
Table 6 shows the selectable baud rate table available when using a 1.8432 MHz
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
Output
16 × clock divisor
(decimal)
Output
16 × clockdivisor
(HEX)
DLM
program value
(HEX)
DLL
program value
(HEX)
6.9 DMA operation
The SC16C2550 FIFO trigger level provides additional flexibility to the user for block
mode operation. LSR[5,6] provide an indication when the transmitter is empty or has
an empty location(s). The user can optionally operate the transmit and receive FIFOs
in the DMA mode (FCR[3]). When the transmit and receive FIFOs are enabled and
the DMA mode is de-activated (DMA Mode 0), the SC16C2550 activates the interrupt
output pin for each data transmit or receive operation. When DMA mode is activated
(DMA Mode 1), the user takes the advantage of block mode operation by loading or
unloading the FIFO in a block sequence determined by the receive trigger level and
the transmit FIFO. In this mode, the SC16C2550 sets the TXRDY (or RXRDY) output
pin when characters in the transmit FIFO is below 16, or the characters in the receive
FIFOs are above the receive trigger level.
6.10 Loop-back mode
The internal loop-back capability allows on-board diagnostics. In the loop-back mode,
the normal modem interface pins are disconnected and reconfigured for loop-back
internally (see Figure 6). MCR[0-3] register bits are used for controlling loop-back
diagnostic testing. In the loop-back mode, the transmitter output (TX) and the receiver
input (RX) are disconnected from their associated interface pins, and instead are
connected together internally. The CTS, DSR, CD, and RI are disconnected from
their normal modem control inputs pins, and instead are connected internally to RTS,
DTR, MCR[3] (OP2) and MCR[2] (OP1). Loop-back test data is entered into the
transmit holding register via the user data bus interface, D0-D7. The transmit UART
serializes the data and passes the serial data to the receive UART via the internal
loop-back connection. The receive UART converts the serial data back into parallel
data that is then made available at the user data interface D0-D7. The user optionally
compares the received data to the initial transmitted data for verifying error-free
operation of the UART TX/RX circuits.
In this mode, the receiver and transmitter interrupts are fully operational. The Modem
Control Interrupts are also operational.
SC16C2550
SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
[1] The value shown in represents the register’s initialized HEX value; X = n/a.
[2] Accessible only when LCR[7] is logic 0.
[3] Baud rate registers accessible only when LCR[7] is logic 1.
[4] Enhanced Feature Register, Xon-1,2 and Xoff-1,2 are accessible only when LCR is set to ‘BF
7.1 Transmit (THR) and Receive (RHR) Holding Registers
The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D7-D0) to
the TSR and UART via the THR, providing that the THR is empty. The THR empty
flag in the LSR register will be set to a logic 1 when the transmitter is empty or when
data is transferred to the TSR. Note that a write operation can be performed when the
THR empty flag is set (logic 0 = at least one byte in FIFO/THR, logic 1 = FIFO/THR
empty).
The serial receive section also contains an 8-bit ReceiveHolding Register (RHR) and
a Receive Serial Shift Register (RSR). Receivedata is removed from the SC16C2550
and receive FIFO by reading the RHR register. The receive section provides a
mechanism to prevent false starts. On the falling edge of a start or false start bit, an
internal receiver counter starts counting clocks at the 16× clock rate. After 7-1⁄
clocks, the start bit time should be shifted to the center of the start bit. At this time the
start bit is sampled, and if it is still a logic 0 it is validated. Evaluating the start bit in
this manner prevents the receiver from assembling a false character. Receiver status
codes will be posted in the LSR.
SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
2
7.2 Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) masks the interrupts from receiver ready,
transmitter empty, line status and modem status registers. These interrupts would
normally be seen on the INTA, INTB output pins.
2IER[2]Receive Line Status interrupt. This interrupt will be issued
whenever a receive data error condition exists as reflected in
LSR[1-4].
Logic 0 = Disable the receiver line status interrupt (normal
default condition).
Logic 1 = Enable the receiver line status interrupt.
1IER[1]Transmit Holding Register interrupt. In the 16C450 mode, this
interrupt will be issued whenever the THR is empty, and is
associated with LSR[5]. In the FIFO modes, this interrupt will be
issued whenever the FIFO is empty.
Logic 1 = Enable the TXRDY (ISR level 3) interrupt.
0IER[0]Receive Holding Register. In the 16C450 mode, this interrupt will
be issued when the RHR has data, or is cleared when the RHR is
empty. In the FIFO mode, this interrupt will be issued when the
FIFO has reached the programmed trigger levelor is cleared when
the FIFO drops below the trigger level.
Logic 1 = Enable the RXRDY (ISR level 2) interrupt.
…continued
7.2.1 IER versus Transmit/Receive FIFO interrupt mode operation
When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1)
are enabled, the receive interrupts and register status will reflect the following:
• The receive RXRDY interrupt (Level 2 ISR interrupt) is issued to the external CPU
when the receive FIFO has reached the programmed trigger level. It will be cleared
when the receive FIFO drops below the programmed trigger level.
• Receive FIFO status will also be reflected in the user accessible ISR register when
the receive FIFO trigger level is reached. Both the ISR register receive status bit
and the interrupt will be cleared when the FIFO drops below the trigger level.
• The receive data ready bit (LSR[0]) is set as soon as a character is transferred
from the shift register (RSR) to the receive FIFO. It is reset when the FIFO is
empty.
• When the Transmit FIFO and interrupts are enabled, an interrupt is generated
when the transmit FIFO is empty due to the unloading of the data by the TSR and
UART for transmission via the transmission media. The interrupt is cleared either
by reading the ISR register, or by loading the THR with new data characters.
7.2.2 IER versus Receive/Transmit FIFO polled mode operation
When FCR[0] = logic 1, resetting IER[0-3] enables the SC16C2550 in the FIFO
polled mode of operation. In this mode, interrupts are not generated and the user
must poll the LSR register for TX and/or RX data status. Since the receiver and
transmitter have separate bits in the LSR either or both can be used in the polled
mode by selecting respective transmit or receive control bit(s).
• LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.
• LSR[1-4] will provide the type of receive errors, or a receive break, if encountered.
• LSR[5] will indicate when the transmit FIFO is empty.
• LSR[6] will indicate when both the transmit FIFO and transmit shift register are
• LSR[7] will show if any FIFO data errors occurred.
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO
trigger levels, and select the DMA mode.
SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
empty.
7.3.1 DMA mode
Mode 0 (FCR bit 3 = 0): Set and enable the interrupt for each single transmit or
receive operation, and is similar to the 16C450 mode. Transmit Ready (TXRDY) on
PLCC44 and LQFP48 packages will go to a logic 0 wheneverthe FIFO (THR, if FIFO
is not enabled) is empty. Receive Ready (RXRDY) on PLCC44 and LQFP48
packages will go to a logic 0 wheneverthe ReceiveHolding Register (RHR) is loaded
with a character.
Mode 1 (FCR bit 3 = 1): Set and enable the interrupt in a blockmode operation. The
transmit interrupt is set when the transmit FIFO is empty. TXRDY on PLCC and
LQFP48 packages remains a logic 0 as long as one empty FIFO location is available.
The receive interrupt is set when the receive FIFO fills to the programmed trigger
level.However, the FIFO continues to fill regardless of the programmed level until the
FIFO is full. RXRDY on PLCC44 and LQFP48 packages transitions LOW when the
FIFO reaches the trigger level, and transitions HIGH when the FIFO empties.
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
Table 9:FIFO Control Register bits description
BitSymbolDescription
1FCR[1]RCVR FIFO reset.
Logic 0 = Receive FIFO not reset (normal default condition).
Logic 1 = Clears the contents of the receive FIFO and resets the
FIFO counter logic (the receive shift register is not cleared or
altered). This bit will return to a logic 0 after clearing the FIFO.
0FCR[0]FIFOs enabled.
Logic 0 = Disable the transmit and receive FIFO (normal default
condition).
Logic 1 = Enable the transmit and receive FIFO. This bit must
be a ‘1’ when other FCR bits are written to, or they will not
be programmed.
Table 10: RCVR trigger levels
FCR[7]FCR[6]RX FIFO trigger level
0001
0104
1008
1114
…continued
7.4 Interrupt Status Register (ISR)
The SC16C2550 provides four levels of prioritized interrupts to minimize external
software interaction. The Interrupt Status Register (ISR) provides the user with four
interrupt status bits. Performing a read cycle on the ISR will provide the user with the
highest pending interrupt level to be serviced. No other interrupts are acknowledged
until the pending interrupt is serviced. A lower level interrupt may be seen after
servicing the higher level interrupt and re-reading the interrupt status bits. Table 11
“Interrupt source” shows the data values (bits 0-3) for the four prioritized interrupt
levels and the interrupt sources associated with each of these interrupt levels.
Table 11: Interrupt source
Priority
level
1 000110LSR(ReceiverLineStatus
2 000100RXRDY (Received Data
2 001100RXRDY (Receive Data
3 000010TXRDY (Transmitter
4 000000MSR (Modem Status
5 010000RXRDY (Received Xoff
6 100000CTS, RTS change of state
ISR[5] ISR[4]ISR[3] ISR[2]ISR[1] ISR[0]Source of the interrupt
Table 12: Interrupt Status Register bits description
BitSymbolDescription
7-6ISR[7-6]FIFOs enabled. These bits are set to a logic 0 when the FIFOs are
5-4ISR[5-4]INT priority bits 4-3. These bits are enabled when EFR[4] is set to
3-1ISR[3-1]INT priority bits 2-0. These bits indicate the source for a pending
0ISR[0]INT status.
SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
not being used in the 16C450 mode. They are set to a logic 1
when the FIFOs are enabled in the SC16C2550 mode.
Logic 0 or cleared = default condition.
a logic 1. ISR[4] indicates that matching Xoff character(s) have
been detected. ISR[5] indicates that CTS, RTS have been
generated. Note that once set to a logic 1, the ISR[4] bit will stay a
logic 1 until Xon character(s) are received.
Logic 0 or cleared = default condition.
interrupt at interrupt priority levels 1, 2, and 3 (see Table 11).
Logic 0 or cleared = default condition.
Logic 0 = An interrupt is pending and the ISR contents may be
used as a pointer to the appropriate interrupt service routine.
Logic 1 = No interrupt pending (normal default condition).
7.5 Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by
writing the appropriate bits in this register.
Table 13: Line Control Register bits description
BitSymbolDescription
7LCR[7]Divisor latch enable. The internal baud rate counter latch and
6LCR[6]Set break. When enabled, the Break control bit causes a break
condition to be transmitted (the TX output is forced to a logic 0
state). This condition exists until disabled by setting LCR[6] to a
logic 0.
Logic 0 = no TX break condition (normal default condition)
Logic 1 = forces the transmitter output (TX) to a logic 0 for
alerting the remote receiver to a line break condition.
5-3LCR[5-3]Programs the parity conditions (see Table 14).
2LCR[2]Stop bits. The length of stop bit is specified by this bit in
conjunction with the programmed word length (see Table 15).
Logic 0 or cleared = default condition.
1-0LCR[1-0]Word length bits 1, 0. These two bits specify the word length to be
This register controls the interface with the modem or a peripheral device.
Table 17: Modem Control Register bits description
BitSymbolDescription
7MCR[7]Reserved; set to ‘0’.
6MCR[6]IR enable.
5MCR[5]Reserved; set to ‘0’.
4MCR[4]Loop-back. Enable the local loop-back mode (diagnostics). In this
3MCR[3]
2MCR[2](
1MCR[1]
0MCR[0]
SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
Logic 0 = Enable the standard modem receive and transmit
input/output interface (normal default condition).
Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs.
While in this mode, the TX/RX output/inputs are routed to the
infrared encoder/decoder. The data input and output levels will
conform to the IrDA infrared interface requirement. As such, while
in this mode, the infrared TX output will be a logic 0 during idle data
conditions.
mode the transmitter output (
DSR, CD, and RI are disconnected from the SC16C2550 I/O pins.
Internally the modem data and control pins are connected into a
loop-back data configuration (see Figure 6). In this mode, the receiver
and transmitter interrupts remain fully operational. The Modem
Control Interrupts are also operational, but the interrupts’ sources are
switched to the lower four bits of the Modem Control. Interrupts
continue to be controlled by the IER register.
Logic 0 = Forces INT (A-B) outputs to the 3-State mode and sets
OP2 to a logic 1 (normal default condition).
Logic 1 = Forces the INT (A-B outputs to the active mode and sets
OP2 to a logic 0.
OP1). OP1A/OP1B are not available as an external signal in the
SC16C2550. This bit is instead used in the Loop-back mode only. In
the loop-back mode, this bit is used to write the state of the modem
interface signal.
RTS
Logic 0 = Force
Logic1=Force
DTR
Logic 0 = Force
Logic 1 = Force
RTS output to a logic 1 (normal default condition).
RTS output to a logic 0.
DTR output to a logic 1 (normal default condition).
DTR output to a logic 0.
This register provides the status of data transfers between the SC16C2550 and
the CPU.
Table 18: Line Status Register bits description
BitSymbolDescription
7LSR[7]FIFO data error.
6LSR[6]THR and TSR empty. This bit is the Transmit Empty indicator. This
5LSR[5]THR empty. This bit is the Transmit Holding Register Empty
4LSR[4]Break interrupt.
3LSR[3]Framing error.
2LSR[2]Parity error.
SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
Logic 0 = No error (normal default condition).
Logic 1 = At least one parity error, framing error or break
indication is in the current FIFO data. This bit is cleared when
there are no remaining error flags associated with the remaining
data in the FIFO.
bit is set to a logic 1 whenever the transmit holding register and the
transmit shift register are both empty. It is reset to logic 0 whenever
either the THR or TSR contains a data character. In the FIFO
mode, this bit is set to ‘1’ whenever the transmit FIFO and transmit
shift register are both empty.
indicator.This bit indicates that the UART is ready to accept a new
character for transmission. In addition, this bit causes the UARTto
issue an interrupt to CPU when the THR interrupt enable is set.
The THR bit is set to a logic 1 when a character is transferred from
the transmit holding register into the transmitter shift register. The
bit is reset to a logic 0 concurrently with the loading of the
transmitter holding register by the CPU. In the FIFO mode, this bit
is set when the transmit FIFO is empty; it is cleared when at least
1 byte is written to the transmit FIFO.
Logic 0 = No break condition (normal default condition).
Logic 1 = The receiver received a break signal (RX was a logic 0
for one character frame time). In the FIFO mode, only one break
character is loaded into the FIFO.
Logic 0 = No framing error (normal default condition).
Logic 1 = Framing error. The receive character did not have a
valid stop bit(s). In the FIFO mode, this error is associated with
the character at the top of the FIFO.
Logic 0 = No parity error (normal default condition.
Logic 1 = Parity error. The receive character does not have
correct parity information and is suspect. In the FIFO mode, this
error is associated with the character at the top of the FIFO.
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
Table 18: Line Status Register bits description
BitSymbolDescription
1LSR[1]Overrun error.
Logic 0 = No overrun error (normal default condition).
Logic1=Overrun error. A data overrun error occurred in the
receive shift register.This happens when additional data arrives
while the FIFO is full. In this case, the previous data in the shift
register is overwritten. Note that under this condition, the data
byte in the receive shift register is not transferred into the FIFO,
therefore the data in the FIFO is not corrupted by the error.
0LSR[0]Receive data ready.
Logic 0 = No data in receive holding register or FIFO (normal
default condition).
Logic 1 = Data has been received and is saved in the receive
holding register or FIFO.
…continued
7.8 Modem Status Register (MSR)
This register provides the current state of the control interface signals from the
modem, or other peripheral device to which the SC16C2550 is connected. Four bits
of this register are used to indicate the changed information. These bits are set to a
logic 1 whenever a control input from the modem changes state. These bits are set to
a logic 0 whenever the CPU reads this register.
Table 19: Modem Status Register bits description
BitSymbolDescription
7MSR[7]CD. During normal operation, this bit is the complement of the
input. Reading this bit in the loop-back mode produces the state of
MCR[3] (
6MSR[6]RI. During normal operation, this bit is the complement of the
input. Reading this bit in the loop-back mode produces the state of
MCR[2] (
5MSR[5]DSR. During normal operation, this bit is the complement of the
DSR input. During the loop-back mode, this bit is equivalent to
MCR[0] (
4MSR[4]CTS. During normal operation, this bit is the complement of the
CTS input. During the loop-back mode, this bit is equivalent to
MCR[1] (
3MSR[3]∆
2MSR[2]∆
CD
RI
OP2).
OP1).
DTR).
RTS).
[1]
Logic 0 = No CD change (normal default condition).
Logic 1 = The
since the last time it was read. A modem Status Interrupt will be
generated.
[1]
Logic 0 = No RI change (normal default condition).
Logic 1 = The
logic 0 to a logic 1. A modem Status Interrupt will be generated.
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
Table 19: Modem Status Register bits description
BitSymbolDescription
1MSR[1]∆DSR
0MSR[0]∆
[1] Whenever any MSR bit 0-3 is set to logic 1, a Modem Status Interrupt will be generated.
[1]
Logic 0 = No DSR change (normal default condition).
Logic1=The
since the last time it was read. A modem Status Interrupt will be
generated.
[1]
CTS
Logic 0 = No CTS change (normal default condition).
Logic 1 = The
since the last time it was read. A modem Status Interrupt will be
generated.
DSR input to the SC16C2550 has changed state
CTS input to the SC16C2550 has changed state
7.9 Scratchpad Register (SPR)
The SC16C2550 provides a temporary data register to store 8 bits of user
information.
7.10 Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this register.
…continued
Bits 0 through 4 provide single or dual character software flow control selection.
When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double
8-bit words are concatenated into two sequential numbers.
CTS goes to a logical 1. Transmission will resume when the CTS
when
pin returns to a logical 0.
6EFR[6]Automatic RTS flow control. Automatic RTS may be used for hardware flow
control by enabling EFR[6]. When Auto-RTS is selected, an interrupt will
be generated when the receive FIFO is filled to the programmed trigger
leveland
a logic 0 when data is unloaded below the next lower trigger level
(programmed trigger level 1). The state of this register bit changes with the
status of the hardware flow control.
hardware flow control is disabled.
RTS will go to a logic 1 at the next trigger level. RTS will return to
RTS functions normally when
0 = Automatic RTS flow control is disabled (normal default condition).
1 = Enable Automatic RTS flow control.
Logic 0 = Special character detect disabled (normal default condition).
Logic 1 = Special character detect enabled. The SC16C2550 compares
each incoming receive character with Xoff2 data. If a match exists, the
received data will be transferred to FIFO and ISR[4] will be set to
indicate detection of special character. Bit-0 in the X-registers
corresponds with the LSB bit for the receivecharacter.Whenthis feature
is enabled, the normal software flow control must be disabled (EFR[3-0]
must be set to a logic 0).
4EFR[4]Enhanced function control bit. The content of IER[7-4], ISR[5-4], FCR[5-4],
and MCR[7-5] can be modified and latched. After modifying any bits in the
enhanced registers, EFR[4] can be set to a logic 0 to latch the new values.
This feature prevents existing software from altering or overwriting the
SC16C2550 enhanced functions.
Logic 0 = disable/latch enhanced features. IER[7-4], ISR[5-4], FCR[5-4],
and MCR[7-5] are saved to retain the user settings, then IER[7-4]
ISR[5-4], FCR[5-4], and MCR[7-5] are set to a logic 0 to be compatible
with SC16C554 mode. (Normal default condition.)
Logic 1 = Enables the enhanced functions. When this bit is set to a
logic 1, all enhanced features of the SC16C2550 are enabled and user
settings stored during a reset will be restored.
3-0EFR[3-0] Cont-3-0 Tx, Rx control. Logic 0 or cleared is the default condition.
Combinations of software flow control can be selected by programming
these bits. See Table 21.
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
10. Dynamic characteristics
Table 26: AC electrical characteristics
T
=−40°C to +85°C; VCC= 2.5 V, 3.3 V or 5.0 V±10%, unless otherwise specified.
amb
SymbolParameterConditions2.5 V3.3 V5.0 VUnit
MinMaxMinMaxMinMax
, t
t
1w
t
3w
t
6s
t
6h
t
7d
t
7w
t
7h
t
9d
t
12d
t
12h
t
13d
t
13w
t
13h
t
15d
t
16s
t
16h
t
17d
t
18d
t
19d
t
20d
t
21d
t
22d
t
23d
t
24d
t
25d
t
26d
t
27d
t
28d
t
RESET
Nbaud rate divisor12
clock pulse duration10-6-6-ns
2w
oscillator/clock frequency
[1]
-48-8080MHz
address set-up time0-0-0-ns
address hold time0-0-0-ns
IOR delay from chip select10-10-10-ns
IOR strobe width25 pF load77-26-23-ns
chip select hold time from IOR0-0-0-ns
read cycle delay25 pF load20-20-20-ns
delay from IOR to data25 pF load-77-26-23ns
data disable time25 pF load-15-15-15ns
IOW delay from chip select10-10-10-ns
IOW strobe width20-
[2]
20-
[2]
15-
[2]
chip select hold time from IOW0-0-0-ns
write cycle delay
[3]
25-25-20-ns
data set-up time20-20-15-ns
data hold time15-5-5-ns
delay from IOW to output25 pF load-100-33-29ns
delay to set interrupt from Modem
25 pF load-100-24-23ns
input
delay to reset interrupt from IOR25 pF load-100-24-23ns
delay from stop to set interrupt-1-1-1R
delay from IOR to reset interrupt25 pF load-100-29-28ns
delay from start to set interrupt-100-45-40ns
delay from IOW to transmit start824824824R
delay from IOW to reset interrupt-100-45-40ns
delay from stop to set RXRDY-1-1-1R
delay from IOR to reset RXRDY-100-45-40ns
delay from IOW to set TXRDY-100-45-40ns
delay from start to reset TXRDY-8-8-8R
Reset pulse width200-40-40-ns
16
− 11216− 11 216− 1R
ns
clk
clk
clk
clk
clk
[1] Applies to external clock, crystal oscillator max 24 MHz.
[2]
This text gives a very brief insight to a complex technology. A more in-depth account
of soldering ICs can be found in our
Packages
There is no soldering method that is ideal for all IC packages. Wavesoldering is often
preferred when through-hole and surface mount components are mixed on one
printed-circuit board. Wave soldering can still be used for certain surface mount ICs,
but it is not suitable for fine pitch SMDs. In these situations reflow soldering is
recommended. Driven by legislation and environmental forces the worldwide use of
lead-free solder pastes is increasing.
12.2 Through-hole mount packages
12.2.1 Soldering by dipping or by solder wave
Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or
265 °C, depending on solder material applied, SnPb or Pb-free respectively.
SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
Data Handbook IC26; Integrated Circuit
(document order number 9398 652 90011).
The total contact time of successive solder waves must not exceed 5 seconds.
The device may be mounted up to the seating plane, but the temperature of the
plastic body must not exceed the specified maximum storage temperature (T
If the printed-circuit board has been pre-heated, forced cooling may be necessary
immediately after soldering to keep the temperature within the permissible limit.
12.2.2 Manual soldering
Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the
seating plane or not more than 2 mm above it. If the temperature of the soldering iron
bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit
temperature is between 300 and 400 °C, contact may be up to 5 seconds.
12.3 Surface mount packages
12.3.1 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling
or pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending on heating method.
stg(max)
).
Typical reflow peak temperatures range from 215 to 270 °C depending on solder
paste material. The top-surface temperature of the packages should preferably be
kept:
• below 220 °C (SnPb process) or below 245 °C (Pb-free process)
• below 235 °C (SnPb process) or below260 °C (Pb-free process) for packages with
Moisture sensitivity precautions, as indicated on packing, must be respected at all
times.
12.3.2 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging
and non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically
developed.
If wave soldering is used the following conditions must be observed for optimal
results:
SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
– for packages with a thickness ≥ 2.5 mm
– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called
thick/large packages.
a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages.
• Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be
parallel to the transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the
transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
• For packages with leads on four sides, the footprint must be placed at a 45° angle
to the transport direction of the printed-circuit board. The footprint must
incorporate solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or
265 °C, depending on solder material applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal of corrosive residues in
most applications.
12.3.3 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low
voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time
must be limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within
2 to 5 seconds between 270 and 320 °C.
, SO, SOJsuitablesuitable−
LQFP, QFP, TQFPnot recommended
SSOP, TSSOP, VSO,
VSSOP
Soldering method
WaveReflow
[3]
−suitable
[2]
not suitablesuitable−
not suitable
[5]
not recommended
[6][7]
[8]
suitable−
suitable−
suitable−
Dipping
[1] For more detailed information on the BGA packages refer to the
(AN01026); order a copy from your Philips Semiconductors sales office.
[2] All surface mount (SMD) packages are moisture sensitive.Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal
or external package cracks may occur due to vaporization of the moisture in them (the so called
popcorn effect). For details, refer to the Drypack information in the
Circuit Packages; Section: Packing Methods
[3] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the
printed-circuit board.
[4] These transparent plastic packages are extremely sensitive to reflow soldering conditions and must
on no account be processed through more than one soldering cycle or subjected to infrared reflow
soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow
oven. The package body peak temperature must be kept as low as possible.
[5] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom
side, the solder cannot penetrate betweentheprinted-circuit board and the heatsink. On versionswith
the heatsink on the top side, the solder might be deposited on the heatsink surface.
[6] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave
direction. The package footprint must incorporate solder thieves downstream and at the side corners.
[7] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it
is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65mm.
[8] Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
.
(LF)BGA Application Note
Data Handbook IC26; Integrated
13. Revision history
Table 28: Revision history
Rev DateCPCNDescription
03 20030619-Product data (9397 750 11621). ECN 853-2368 30033 of 16 June 2003.
Modifications:
• Figure 5 “Crystal oscillator connection.” on page 13: changed capacitors’ values and
added connection with resistor.
02 20030314-Product data (9397 750 11204). ECN 853-2368 29624 of 07 March 2003.
01 20020904-Product data (9397 750 08831). ECN 853-2368 28865 of 04 September 2002.
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
Level Data sheet status
IObjective dataDevelopmentThis data sheet contains data from the objective specification for product development. Philips
IIPreliminary dataQualificationThis datasheet contains data from the preliminary specification. Supplementary data will bepublished
IIIProduct dataProductionThis data sheet contains data from the product specification. Philips Semiconductors reserves the
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
[1]
Product status
15. Definitions
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
[2][3]
Definition
Semiconductors reserves the right to change the specification in any manner without notice.
at a later date.Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
right to make changes at anytime in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
16. Disclaimers
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes norepresentations or warrantiesthat these productsare
free frompatent, copyright, or mask work right infringement, unless otherwise
specified.
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.Fax: +31 40 27 24825
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 19 June 2003Document order number: 9397 750 11621
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