Philips SAA7785 User Manual
INTEGRATED CIRCUITS
SAA7785
ThunderBird Avenger PCI Audio
Accelerator
Preliminary specification 1999 Nov 12
Philips Semiconductors Preliminary Specification
ThunderBird AvengerTM PCI Audio SAA7785
Accelerator
IEEE 1394 devices via 14 Channel Virtual Write
Master
•Superior hardware acceleration for minimum CPU
consumption
GENERAL DESCRIPTION
The SAA7785 ThunderBird AvengerTM is a high-performance PCI audio accelerator offering the ultimate
home theater, gaming and music solution. Armed with
QSound’s advanced QMSS
transforms ordinary stereo games, movies and music
to 5.1 speaker output. An integrated S/PDIF OUT connects to consumer audio equipment and S/PDIF IN
support provides digital connection from a CD player or
other digital audio equipment. The ThunderBird Aveng-
TM
er
supports redirection of up to 5.1 streams from PCI
to USB or IEEE 1394 devices. Full hardware acceleration of DirectSound
TM
gameport functions provides increased graphic framerates and industry leading low CPU consumption. Utilizing a specialized DSP controller and combining with a
AC97 codec creates a high quality, high performance,
low cost audio subsystem.
TM
, ThunderBird AvengerTM
, 3D audio, music synthesis and
•Broadest API compatibility including
DirectSound3D
TM
, EAXTM, and A3D
TM
•64 hardware wavetable polyphony
•Professional soft-synth with 256 voice polyphony
and XG support
•Second generation ActiMedia programmable DSP
architecture
•Global reverb for external digital and analog input
sources
•Enhanced MIDI reverb and chorus (per track and
global)
2
•Independent I
S input and output ports
•Comprehensive Real Mode DOS and DOS windows support
•Dual gameport accelerator with leagacy and digital
joystick modes
TM
•PC/PCI, DDMA, and LAM
PCI DMA support
•Supports quad and dual AC97 CODECS
FEATURES
•2, 4, or 5.1 speaker and headphone 3D algorithms
TM
•QSound3DInteractive
•QSound Multi-Speaker System
interactive positional 3D
TM
stereo to quad or
•3.3 v operation with 5 v tolerant I/O
(R) 95
•Windows
, Windows
2000 (WDM) drivers
stereo to 5.1 processing
•QSound Environmental Modeling
TM
EAX
1.0/2.0 compatible)
TM
•QXpander
and stereo-to-3D remapping
•Integrated S/PDIF OUT and optional S/PDIF IN
•AC3 5.1 or stereo playback through S/PDI F output
•Processing up to 512 simultaneous inputs including
TM
(I3D Level 2.0,
APPLICATIONS
•Complete audio subsystem when combined with
AC97 CODEC
•PC sound cards and motherboards
•Video games and other PCI bus-based multimedia
applications
256 DirectSound streams and up to 96 concurrent
CD quality 3D streams
•Redirection up to 5.1 streams from PCI to USB or
1999 Nov 12 2
(R)
98, and Windows
(R)
Philips Semiconductors Preliminary Specification
ThunderBird AvengerTM PCI Audio SAA7785
Accelerator
ORDERING INFORMATION
TYPE
NUMBER
NAME DESCRIPTION VERSION
PACKAGE
SAA7785 TQFP128 Thin quad flat pack; 128 leads (lead length 1.00 mm); body
14 x 14 x 1.00 mm
SAA7785 TQFP100 Thin quad flat pack; 100 leads (lead length 1.00 mm); body
14 x 14 x 1.00 mm
QUICK REFERENCE DATA
Condition Symbol Maximum Ratings
Ambient Operating Temperature T
Ambient Storage Temperature T
A
S
Non-Operating Core and Ring Supply Voltage VDD, VDDIC -0.5V to 4.6V *
Operating Core Supply Voltage VDDIC -0.5V to 3.63V *
0°C to +70°C
-65°C to +150°C
25-90040
25-90042
Operating Ring Supply Voltage VDD 3.0V to 3.63V *
5V Tolerant Supply (5.0V nominal supply) NWELL -0.5V to 5.5V *
NWELL to VDD Differential NWELL-VDD 0 ≤ (NWE LL-V DD) < 4.0V
3V Tolerant I/O DC Input Voltage V
3V Tolerant I/O DC Output Voltage V
5V Tolerant I/O DC Input Voltage V
5V Tolerant I/O DC Output Voltage V
DC Input Current (at V
DC Output Current (at V
< 0V or VI > VDD) I
I
< 0V or VO > VDD) I
O
Power Dissipation P
I3
O3
I5
O5
I
O
D
-0.5V to VDD+0.5V (≤ 4.6V max)+
-0.5V to VDD+0.5V (≤ 4.6V max)+
-0.5V to 5.5V (≤ 6.0V max)+
-0.5V to VDD+0.5V (≤ 4.6V max)+
± 20mA
± 20mA
500mW
*Refer to Section 3.1 to ensure proper power supply sequencing as well as voltage ranges.
+Items in parenthesis are non-operating conditions.
1999 Nov 12 3
Philips Semiconductors Preliminary Specification
ThunderBird AvengerTM PCI Audio SAA7785
Accelerator
FIGURE 1 BLOCK DIAGRAM
Serial
CFG
Port
PCI
Bus
Test
Port
INTA#
GPIO
GamePort
AC97
Xtal_out
PCI
Configuration
Headers
PCI
Master/Slave
Interface
Serial
Interrupt
Controller
General
Purpose I/O
Game Port
Interface
PLL
Test Logic
PLL Cell
AC Link Interface
AC LINK
Legacy
DMA
Interface
SoundBlaster
Registers
OPL3
Registers
Sample Fetch
Accelerator
Virtual
Registers
I2S
Interface
S/P DIF
Output
DSP Interrupt
Controller
INTRs
DSP DATA BUS
DSP Core
DSP Code
ROM
DSP Code
RAM
DSP
Memory
Controller
DSP Data
RAM
2
S
I
Port
S/P DIF
DSP CODE BUS
Multimedia
Timer
Address
Generation
Host/DSP
Interface
MIDI Regs
and UART
MIDI Interface
1999 Nov 12 4
FM
Accelerator
Prog
IIR Filter
Phase/Env
Accelerator
Philips Semiconductors Preliminary Specification
ThunderBird AvengerTM PCI Audio SAA7785
Accelerator
PINNING
TABLE 1 Signal and Pin Names for 128 pin SAA7785 ThunderBird Avenger
PIN
#
1 BIT_CLK 33 GNT# 65 AD22 97 AD12
2 SDATA_OUT
3 SDATA_IN0 35 RST# 67 AD21 99 AD10
4 SDATA_IN1 36 VSS 68 AD20 100 NWELL1
5 AC_RST# 37 PCLK 69 AD19 101 PGPIO4
6 VSS 38 PCGNT# 70 VSS 102 AD9
7 JAB1 39 PCREQ# 71 AD18 103 VDD
8 JBB1 40 VDD 72 AD17 104 AD8
9 VDD 41 GNT# 73 AD16 105 VSS
10 JACX 42 VDDIC 74 PGPIO7 106 C/BE0
11 JBCX 43 REQ# 75 NWELL3 107 VDDIC
12 MIDIOUT 44 PGPIO0 76 VSS 108 AD7
13 JBCY 45 AD13 77 C/BE2# 109 VDD
14 NWELL2 46 AD30 78 FRAME# 110 AD6
15 JACY 47 VDD 79 VDD 111 AD5
16 VSSIC 48 PGPIO1 80 IRDY# 112 VSS
17 JBB2 49 AD29 81 PGPIO6 113 AD4
18 TRI#/CFGCLK 50 VSS 82 VDDIC 114 AD3
19 MIDIIN 51 NWELL0 83 TRDY# 115 AD2
20 VDD 52 PGPIO2 84 VSS 116 VSSIC
21 VSS 53 AD28 85 DEVSEL# 117 AD1
22 TRI#/CFGCLK 54 VSSIC 86 STOP# 118 AD0
23 NAND#/CFGDAT 55 AD27 87 PGPIO5 119 VDD
24 SPDO 56 VDD 88 VDD 120 TWS
25 CCLK 57 AD26 89 PERR# 121 TSD
26 DSPCLK 58 VSS 90 SERR# 122 TSCK
27 SPDI 59 AD25 91 PAR 123 CLKRUN
28 VDD 60 AD24 92 C/BE1 124 RESVDS
29 VSS 61 C/BE3# 93 AD15 125 RSD/GPIO2
30 PSUB 62 IDSEL
31 PLLAPWR 63 AD23 95 VSS 127 RWS/GPIO0
32 PLLAGND 64 PGPIO3 96 AD13 128 SYNC
PIN NAME
34 PME# 66 VDD 98 AD11
94 AD14 126 RSCK/GPIO1
TM
1999 Nov 12 5
Philips Semiconductors Preliminary Specification
ThunderBird AvengerTM PCI Audio SAA7785
Accelerator
FIGURE 2 PIN CONFIGURATION
SAA7785 ThunderBird AvengerTM PINS ON 128 PIN TQFP PACKAGE DIAGRAM (TOP VIEW).
RESVD
CLKRUN#
TSCK
TSD
TWS
VDD
AD0
AD1
VSSIC
AD2
AD3
AD4
VSS
AD5
AD6
VDD
AD7
VDDIC
C/BE0#
VSS
AD8
VDD
AD9
PGPIO4
NWELL
AD10
SDATA_OUT
SDATA_IN0
SDATA_IN1
TRI#/CFGCLK
NAND#/CFGDAT
Notes:
1. Package body size is 14 mm.
2. Scale is approx 1” = 5.08 mm (5X actual size).
3. Use package bond form nuber 23-xxxxx.
BIT_CLK
AC_RST#
VSS
JAB1
JBB1
VDD
JACX
JBCX
MIDIOUT
JBCY
NWELL
JACY
VSSIC
JBB2
JAB2
MIDIIN
VDD
VSS
SPDO
CCLK
DSPCLK
SPDI
VDD
VSS
PSUB
PLLAPWR
PLLAGND
RSD/DGPIO2
RSCK/DGPIO1
SYNC
RWS/DGPIO0
12897127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33643435363738394041424344454647484950515253545556575859606162
VSS
RST#
INTA#
PME#
SAA7785
128 PIN TQFP
VSS
REQ#
VDDIC
VDD
AD31
AD30
AD29
PGPIO0
NWELL
PGPIO1
VDD
PCLK
GNT#
PCGNT#
PCREQ#
104
VDD
AD28
AD27
AD26
VSSIC
PGPIO2
103
VSS
102
AD25
101
AD24
100
C/BE3#
AD11
AD12
99
98
AD13
96
VSS
95
AD14
94
AD15
93
C/BE1#
92
PAR
91
SERR#
90
PERR#
89
VDD
88
PGPIO5
87
STOP#
86
DEVSEL#
85
VSS
84
TRDY#
83
VDDIC
82
PGPIO6
81
IRDY#
80
VDD
79
FRAME#
78
C/BE2#
77
VSS
76
NWELL
75
PGPIO7
74
AD16
73
AD17
72
AD18
71
VSS
70
AD19
69
AD20
68
AD21
67
VDD
66
AD22
65
63
AD23
IDSEL
PGPIO3
1999 Nov 12 6
Philips Semiconductors Preliminary Specification
ThunderBird AvengerTM PCI Audio SAA7785
Accelerator
PINNING
TABLE 2 PIN DEFINITIONS FOR THE 100 Pin SAA7785 ThunderBird Avenger
PIN
#
1 BIT_CLK 30 PCLK 59 VSS 87 AD5
2 SDATA_OUT 31 PCGNT# 60 C/BE2# 88 VSS
3 SDATA_IN 32 PCREQ# 61 FRAME# 89 AD4
4 AC_RST# 33 GNT# 62 IRDY# 90 AD3
5 VSS
6 JAB1 35 REQ# 64 TRDY# 92 VSSIC
7 JBB1 36 AD31 65 DEVSEL# 93 AD1
8JACX 37AD30
9JBCX 38VDD 67VDD 95VDD
10 MIDIOUT 39 AD29 68 PERR# 96 CLKRUN#
11 JBCY 40 NWELL_40 69 SERR# 97 RSD/GPIO2
12 JACY 41 AD28 70 PAR 98 RSCK/GPIO1
13 VSSIC 42 VSSIC 71 C/BE1# 99 RWS/GPIO0
14 JBB2 43 AD27 72 AD15 100 SYNC
15 JAB2 44 AD26 73 AD14
16 MIDIIN 45 VSS 74 VSS
17VDD 46AD25 75AD13
18 TRI#/CFGCLK 47 AD24 76 AD12
19 NAND#/CFGDAT 48 C/BE3# 77 AD11
20 SPDO 49 IDSEL 78 AD10
21 CCLK 50 AD23 79 NWELL1
22 DSPCLK 51 AD22 80 AD9
23 PSUB 52 VDD 81 VDD
24 PLLAPWR 53 AD21 82 AD8
25 PLLAGND 54 AD20 83 C/BE0#
26 INTA# 55 AD19 84 VDDIC
27 PME# 56 AD18 85 AD7
28 RST# 57 AD17 86 AD6
29 VSS 58 AD16
PIN NAME
34 VDDIC 63 VDDIC 91 AD2
66 STOP# 94 AD0
TM
1999 Nov 12 7
Philips Semiconductors Preliminary Specification
ThunderBird AvengerTM PCI Audio SAA7785
Accelerator
SAA7785 ThunderBird AvengerTM pinout for 100 pin package
RSCK/DGPIO1
RSD/DGPIO2
CLKRUN#
VDD
AD0
AD1
VSSIC
AD2
AD3
AD4
VSS
AD5
AD6
AD7
VDDIC
C/BE0#
AD8
VDD
AD9
NWELL
AD10
AD11
SYNC
RWS/DGPIO0
AD12
BIT_CLK
SDATA_OUT
SDATA_IN0
AC_RST#
MIDIOUT
TRI#/CFGCLK
NAND#/CFGDAT
DSPCLK
PLLAPWR
PLLAGND
Notes:
1. Package body size is 14 mm.
2. Scale is approx 1” = 5.08 mm (5X actual size).
3. Use package bond form nuber 23-61269.
VSS
JAB1
JBB1
JACX
JBCX
JBCY
JACY
VSSIC
JBB2
JAB2
MIDIIN
VDD
SPDO
CCLK
PSUB
9998979695949392919089888786858483828180797877
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26272829303132333435363738394041424344454647484950
RST#
INTA#
PME#
SAA7785
100 PIN TQFP
VSS
PCLK
GNT#
PCGNT#
PCREQ#
REQ#
VDDIC
VDD
AD31
AD30
AD29
NWELL
VSS
AD28
AD27
AD26
AD25
VSSIC
76
AD13
75
VSS
74
AD14
73
AD15
72
C/BE1#
71
PAR
70
SERR#
69
PERR#
68
VDD
67
STOP#
66
DEVSEL#
65
64
TRDY#
63
VDDIC
62
IRDY#
61
FRAME#
60
C/BE2#
59
VSS
58
AD16
57
AD17
56
AD18
55
AD19
54
AD20
53
AD21
52
VDD
51
AD22
AD24
AD23
IDSEL
C/BE3#
1999 Nov 12 8
Philips Semiconductors Preliminary Specification
ThunderBird AvengerTM PCI Audio SAA7785
Accelerator
FUNCTIONAL OVERVIEW
QSound 3D Audio Algorithms
QSound Labs most advanced algorithms for 3D
virtualization, multichannel processing, audio mixing
and wavetable synthesis result in unsurpassed 3D
audio. QSound’s Q3D
natively for speakers and therefore requires no
crosstalk cancellation. The result is a wide “sweetspot”,
strong positional perception and insensitivity to head
movement and position. Listeners can enjoy a true 3D
experience with only two speakers connected to their
PC.
QSound Multi-Speaker System
proprietary stereo-to-quad or 5.1 remapping algorithm
to transform ordinary stereo into more immersive quad
and 5.1 outputs. Not simply mirroring the front speaker
output to the rear speakers, QMSS
individual channels. The result is DirectSound games
become more realistic with action all around the
listener; music CD, MP3 and MIDI playback become
more immersive; and stereo and Dolby ProLogic film
clips become theatre-like in presentation without
needing a specific decoder.
QSound3DInteractive
to interactively position DirectSound streams in 3D
space around the listener. Four different 3D engines,
based on HRTF and patented QSound technology,
render sound over headphones, 2, 4 or 5.1 speakers.
TM
Q3DI
uses the industry standard DirectSound3DTM
API and is compatible with DirectSound, EAX
A3D1.0
TM
applications.
QSound Environmental Modeling
further realism by adding reverb, occulsion and
obstruction as additional positional ques. With QEM
enabled, each DirectSound3D sound source receives
reverb simulating acoustic reflections based on the
regions reverb present and the sources’ current
position relative to the listener. In addition obstruction
and occlusion filters are used to simulate the acoustical
effects of barriers and openings in a games virtual 3D
environment such as walls, doorways and pillars, and
is compliant with I3D Level 2.0.
S/PDIF OUT/IN
The SAA7785 ThunderBird Avenger
integrated S/PDIF OUT port enabling users to output
TM
is the only solution developed
TM
(QMSSTM) uses a
TM
creates 4 and 5.1
TM
utilizes the ActiMediaTM DSP
TM
, and
TM
(QEMTM) adds
TM
provides an
AC3 data from a DVD directly to an AC3 decoder.
The S/PDIF stereo output capability allows users to
connect to a variety of consumer audio equipment ,
such as a stereo receiv er, minidisk, or digital
speakers. S/PDIF IN support through the I
2
S port
enables digital connection from a CD player or other
audio equipment that utilizes the S/PDIF format.
Superior Concurrency
The SAA7785 ThunderBird Avenger
TM
combines its
64 hardware input buffers with software (256 MIDI
channels and 192 DirectSound
TM
inputs) for a total of
512 simultaneous streams. The ThunderBird
Avenger
TM
can process 64 combined audio and
wavetable voices in hardware plus an additional 192
audio streams using QSound’s efficient MMX host
engine. In addition, Avenger offers game developers
up to 96 simultaneous 3D streams. For greater
concurrency and higher music polyphony a
professional quality 256 voice soft-synth is available.
This can be used for all music synthesis reserving all
256 streams for other audio sources, making the
ThunderBird Avenger
TM
an excellent solution for
gaming applications.
Hardware Acceleration
The SSA7785 ThunderBird Avenger
TM
is a true
hardware audio accelerator. CPU consumption is
minimized by processing sample rate conversion,
panning, mixing, 3D virtualization, filtering, music
synthesis, multichannel conversion, and gameport
functions in the hardware DSP. This frees up the host
CPU to perform other tasks, boosting graphic frame
rates and raising system benchmarks.
320 Voice CD Quality Wavetable Synthesis
ThunderBird Avenger
TM
includes two wavetable
synthesis engines. When hardware mode is enabled,
the ActiMedia
TM
DSP can produce up to 64
wavetable 44Khz, 16 bit voices. This mode
minimizes CPU consumption and is ideal for games
with MIDI music tracks. In addition, a professional
quality soft-synth can produce up t o 256 voices
including special effects. The soft-synth is
configurable and can be optimized for highest quality
with pure music applications or for minimum CPU
consumption in gaming applications. Combining both
hardware and software synthesizers allows for 320
1999 Nov 12 9
Philips Semiconductors Preliminary Specification
ThunderBird AvengerTM PCI Audio SAA7785
Accelerator
total simultaneous voices.
ActiMedia
ActiMedia
TM
DSP Architecture
TM
DSP architecture combines the strengt hs
of programmable and fixed function DSP architectures.
Programmability enables custom features, field
upgrades, and simple application development, while
an array of gate-efficient fixed function DSP processors
(accelerators) operate in parallel to provide an
excellent price/performance ratio. Unlike fixed-point
DSPs that must use a single resolution for all audio
processing, each accelerator is designed with the
optimum resolution for its function. This provides audio
integrity without the cost of high resolution or floating
point programmable DSP implementation.
Digital Model Dual Game Port
The software polling used by analog game ports can
consume up to 10% of the host CPU. ThunderBird PCI
products utilize a digital operation mode that can
eliminate software polling and accelerate the game
port function resulting in significan tly impr ove d syste m
performance. Joystick buttons can be polled or
interrupt driven to further enhance performance. A
default analog mode assures compatibility with DOS
and other non-DirectInput
TM
applications.
Comprehensive Legacy Audio Support
SoundBlaster Pro compatibility in both Real Mode DOS
and DOS windows is achieved through hardware
SoundBlaster and OPL3 (FM) emulation registers.
Legacy DMA over the PCI bus is supported on all
major platforms utilizing PC/PCI, DDMA, or Philips’
proprietary Legacy Accommodation Mode
TM
(LAMTM).
DOS music synthesis includes stereo MIDI playback
and quad/5.1 MIDI playback as well as FM emulation.
1999 Nov 12 10
Philips Semiconductors Preliminary Specification
ThunderBird AvengerTM PCI Audio SAA7785
Accelerator
Architectural Overview
The SAA7785 ThunderBird AvengerTM is a multi-functional device that provides sound processing producing SoundBlaster-compatible emulation, DirectSound acceleration, 3D sound, spatialization, special effects, and 64-voice wavet able synthesis through the use of a Pine Digital Signal Processor (DSP) as the primary engine. Included within the
ThunderBird Q3DIII are interfaces for an AC97 codec, I
Consumer Output port.
FIGURE 3 Block Diagram of a PC/AT System with the SAA7785 ThunderBird AvengerTM
2
S I/O, MIDI port, standard analog joyst icks, and an S/P DI F
CPU
System
Bridge
TM
HOST BUS
AGP
Graphics
Cache
Memory
ISA BUS PCI BUS
Pentium
Controller
PCI to ISA
Multi I/O
AC97 CODEC
2/4 Channels Additional
(Primary)
1999 Nov 12 11
AC97 CODEC
2 channels
ThunderBirdTM Audio
Controller
JoystickMIDI Port
I2S S/P DIF
Philips Semiconductors Preliminary Specification
ThunderBird AvengerTM PCI Audio SAA7785
Accelerator
TM
The SAA7785 ThunderBird Avenger
port. Software support is required for non-DOS applications, such as Windows
tem can also be supported with the additional software.
chip is designed to operate on any PCI system with the proper software sup-
(tm)
drivers. Non Pentium
(tm)
based sys-
Systems that provide DDMA or have the ISA bridge on the primary PCI bus are able to perform SoundBlaster emulation
enabling the operation of legacy DOS based games. The SAA7785 ThunderBird Avenger
TM
chip provides two 8237
style DMA channels to perform legacy DMA cycles on selected syst ems. The s ame t wo 8237 c hannels provide Dist ributed DMA support as well. PC/PCI is also supported to provide legacy DMA support on chipsets that support said protocol. For systems that support neither DDMA nor PC/P CI, there is a sof tw are solution implemented as a TSR.
DirectSound acceleration, both for 2D and 3D audio along with wavetable sample fetching, is accomplished using the
SAA7785 ThunderBird Avenger
ThunderBird Avenger
TM
chip to accelerate DirectSound audio streams as well as fet ch wav etable sample for the 64
TM
chip PCI 2.1 bus master. This bus master provides the means for the SAA7785
voice wavetable synthesis and effects algorithms. Wavetable sample fetching is always retrieved from system memory
saving the cost of an external wavetable ROM. Downloadable sample sets, with software, are also supported using the
bus master hardware.
Additionally, the SAA7785 ThunderBird Avenger
TM
chip follows the AC97 Architecture to provide high quality audio by
the use of one or more separate codecs. Serial DACs, as well as AC97 CODECs can be selected to providing audio
into the analog world for low cost playback. Multi-channel AC97 CODECs can be us ed to provide up to 8 c hannels of
audio output.
A programmable DSP core is also provided to run the audio algorithms for wavetable synthes is, FM s ynthesis, s pecial
effects such as reverb and chorus, along with sample rate conversion and data management. The imbedded DSP core
and its peripherals are managed solely by the DSP and requires no intervention from the host. The host can DS P can
pass messages to and from each domain to provide a host s oftware interf ace into t he DSP domain.
PCI Interface, Configuration, and Interrupt Serializer
The SAA7785 ThunderBird AvengerTM chip PCI interface is composed of master and slave state machines, an
address/data/byte enable datapath, a bus arbiter for the two on chip masters, control logic for the master and slave
internal busses, an interrupt serializer, and the standard PC I configurat ion register header.
The standard PCI configuration header is also supported. Since the SAA7785 ThunderBird Avenger
tion device, there are three PCI configuration spaces allocated f or each funct ion. The three func tions are t he audio
device, the joystick and the 16650 UART. The purpose of the mult iple configuration headers is to ensure PCI c ompliance and enable the operating system to select the correct sof tw are driver for each individual device. The Serial CFG
Port is used to shift in subvendor specific data for each of the PCI configuration headers. The Serial CFG port is an
industry standard I
2CTM
format. The configuration headers are included in the PCI interface to reduc e inter-block rout-
ing. All other PCI configuration space registers are included in the blocks that utilize these registers.
TM
is a multi-func-
Clocks and the PLL Subsystem
Clocks for operation of the SAA7785 ThunderBird AvengerTM are derived from two sources; an external crystal and bit
clock from the AC97 CODEC. The SA A7785 ThunderBird Avenger
external crystal.
TM
The SAA7785 ThunderBird Avenger
substem consists of a fixed layout PLL cell and a digital interface to the 8 bit PS
bus. The PLL is designed to drive the clocks for the DSP subsystem. The implementation calls for the PLL to be utilized
with complete programmable register interface to enable the tuning of the frequencies as necessary.
TM
PLL Subsystem derives its reference from the
Multimedia Timer
The SAA7785 ThunderBird AvengerTM chip supplies a 20-bit, .84 uS resolution timer for game synchronization. The
1999 Nov 12 12
Philips Semiconductors Preliminary Specification
ThunderBird AvengerTM PCI Audio SAA7785
Accelerator
timer data can be accessed as an I/O device. This timer can be used by game developers to keep track of time elapsed
to synchronize the video to the audio stream. The timer can be polled or interrupt driven and is selectable by the user
application.
DMA
DMA is for the Sound Blast er registers, t he DSP Mastering Dev ice (DMD), and the S/P DI F output. To cover as many
systems as possible, the DMA interface supports three modes for legacy s upport: Mobile PC /PCI DMA Arbitrat ion
(PC/PCI), Distributed DMA (DDMA) and Legacy Accommodation Mode (LAM).
Legacy Accommodation Mode allows the SAA7785 ThunderBird Avenger
snoop and snarf selected DMA cycles on the PCI bus that were intended to the ISA B ridge. I f a chip set support s Distributed DMA, the SAA7785 ThunderBird Avenger
ally, PC/PCI can be utilized as well if neither DDMA nor LAM are supported on the selected chip set.
TM
will use this method since it is more efficient than LAM. Addition-
TM
, in an architecturally compatible system, to
AC Link
The SAA7785 ThunderBird AvengerTM chip provides support for the AC97 (V2.1) specification by supplying an AC Link
interface to communicate with industry standard AC97 CODECs. Up to two CODECs can be used for a total of 8 possible outputs (4 stereo channels).
Sound Blaster Registers
The other device that requires DMA is the SoundBlaster registers. DMA is used to transfer SoundBlaster digital audio
files from the host to a codec for playback in addition to prov iding a mailbox for other commands. In order for the DSP
to emulate the Sound Blaster sound effects, a legacy register set must be implemented to capture these commands.
These sixteen, 16-bit registers are used primarily to emulate SoundBlaster Pro register set as well as the SoundBlaster
Pro mixer registers. These registers are used as a mailbox to the DSP dat a bus to deliver data to the SoundB laster
Emulation code. The SAA7785 ThunderBird Avenger
requires. All data transmitted over the SoundBlaster Registers is processed by the DSP to emulate the Sound Blaster
Pro hardware.
TM
chip supports DMA to the Sound Blaster that legacy code
OPL3 Registers and the FM Accelerators
The OPL3 register interface is a subset of the complete SoundBlaster register set . The OPL3 regist ers are separat e to
point out that the FM legacy is supported at the register level. The OPL3 registers simply pass FM synthesis commands
to the SoundBlaster Emulation code and receive status from t he same code.
Virtual Registers
The Virtual Registers interfaces the PCI bus and two substantial wavetable synthesis accelerators: the Sample Fetc h
and Address Generation accelerators. The Virtual Registers is responsible for setting up the PCI interfac e for master
cycles data fetches and retrieving those fetches int o a s ample buffer. The Virt ual Registers get commands from the
Address Generation accelerator and turns them into PCI master requests. Once the data has been retrieved, the Virtual
Register then instructs the Sample Fetch ac celerator to process a block of dat a. Once t he processing is complete, the
Sample Fetch Accelerator notifies the Virtual Registers that all is clear and that new data can be processed.
Address Generation Accelerator
The Address Generation accelerator is a preprocessing unit for the sample f etching mechanism inside the Virtual Registers. The Address Generator will get a set of parameters from the DS P code on a per voice basis for either DirectSound processing or wavetable synthesis. Once these voice parameters are set, the hardware is instructed to translate
1999 Nov 12 13
Philips Semiconductors Preliminary Specification
ThunderBird AvengerTM PCI Audio SAA7785
Accelerator
the addresses and fetch the audio samples from system memory. The Address Generator is also capable of looping
without intervention from the DSP code. The DSP kills voices by instruct ing t he Address Generator to s top fet c hing
data. Once the samples are fetched, they are stored in the Virtual Register’s input sample buffer for processing by t he
Sample Fetch Accelerator.
Sample Fetch Accelerator
The Sample Fetch accelerator is used to process audio samples fetched by the Virtual Registers and deliver them t o
the DSP code for further processing. This processing can include pitch shifting or sample rate conversion. The degree
of pitch shifting is under direction of DSP code indicating the Sample Fetch accelerator is programmable. The input
samples are taken from the Virtual Register’s input sample buffer and stored in DSP memory space.
MIDI Registers and UART
An MPU401 compatible UART is supplied to enable external MIDI devices to use the SAA7785 ThunderBird AvengerTM
chip synthesizers as well as its external device’s own synthesizer. The MIDI register interface is used to pass the MIDI
command stream from the host to the DSP firmware for parsing into synthesizer commands. The MPU401 UA RT
always operates in “dumb” mode. Both the PCI and DSP can access the MIDI UART directly. Data is presented from/to
the MPU401 Registers in a mailbox fashion to the MPU401 UART.
General Purpose Input/Output
There are seven general purpose I/O pins that are controlled by the PCI bus (128 pin version). No GPIOs are available
in the 100 pin package.
PINE DSP Core
The Pine DSP core is a programmable 16-bit integer DS P with separate c ode and dat a buss es (Harvard arc hitecture).
Main features of the DSP core include 2K x 16 data RAM, 64K word code and data space, 16 x 16 bit two’s complement
parallel multiplier with 32-bit product, single cycle multiply/accumulate instructions, 36-bit ALU, two 36-bit accumulators,
six-general purpose 16-bit pointer registers, option for up to eight user-defined 16-bit registers, z ero overhead looping,
repeat and block-repeat instructions with one nes ting level, shifting capability, automatic saturation mode on ov erflow
while reading content of accumulators, divide and normalize step support.
As noted on Figure 2, the DSP subsystem is supported by two dedicated Pine internal busses called the DSP code bus
and the DSP data bus. All DSP peripherals are connected to the DSP data bus while the code bus is used for just that,
DSP code ROM and RAM. Both the DSP code and data busses are 16-bit for the address and data lines on each bus.
DSP code also enables the DSP core to act as a P CI bus mas ter making it a powerful and flexible audio processing
unit.
DSP Interrupt Controller
The DSP Interrupt Controller is a programmable, priority encoded device that encodes two interrupt signals to the Pine
core. The DSP Interrupt Controller resides on the DSP data bus and is programmed by DS P code. Bot h sets of interrupt vectors feature an enable and stat us bit for each int errupt based device.
DSP Memory Controller
The DSP memory controller provides controls and decodes for the regular DSP data and code RAMs as well as the
code ROMs. The Memory Controller also includes a patch mechanism to allow ROM code to be updated or fixed using
a trapping device.
1999 Nov 12 14
Philips Semiconductors Preliminary Specification
ThunderBird AvengerTM PCI Audio SAA7785
Accelerator
SERIAL PORT INTERFACES
OVERVIEW
2
The SAA7785 chip will contain an S/PDIF Consumer Grade transmit port and an I
ports are designed to exchange digital audio data but can be used for any type of data transfer assuming the bandwidth
is adequate. Currently, these ports are connected to the DSP data bus.
The Inter-IC Sound Bus, or I
interface is based on a continuous serial clock that determines the data rate along with the word select line and the data
lines. An I
2
S port can be a master or a slave device. A master device drives the serial clock and word select lines while
a slave device receives the clocking signals. The SAA7785 I
2
S Port, is a simple interface used to transfer digital data from one source to another. The
2
S ports are independently programmable to be either a
master or a slave and for 32.0, 44.1 and 48.0KHz stereo data transfer.
Also included is a Sony/Philips Digital Interface Format, or S/PDIF, serial port. This interface is generally used to trans -
mit raw audio data but is also used to transfer AC-3 encoded data as well using DMA. The S/PDIF format is a synchronous interface with the clock encoded on the data stream. The S/P DIF port s s upport 32.0, 44. 1 and 48.0K Hz stereo
data transfer up to 24 bits. The S/PDIF interface is IEC958 Consumer Grade compliant.
S transmit/receive pair. These serial
1999 Nov 12 15
Philips Semiconductors Preliminary Specification
ThunderBird AvengerTM PCI Audio SAA7785
Accelerator
2
FIGURE 4 I
S SERIAL PORTS BLOCK DIAGRAM
CCLK
Right Data
Left Data
Transmit
Control
Logic
I2S Ports
Clock
Divider
Receive
Control
Logic
Left Data
Right Data
Transmit
Shift
Register
Receive
Shift
Register
XDATA
XSCLK
XWS
RWS
RSCLK
RDATA
DSP DATA BUS
1999 Nov 12 16
Philips Semiconductors Preliminary Specification
ThunderBird AvengerTM PCI Audio SAA7785
Accelerator
FIGURE 5 S/PDIF TRANSMIT PORT BLOCK DIAGRAM
Audio Data
Holding
Registers
DSP DATA BUS
Aux Data
Holding
Registers
Ctl/Channel
Stat Holding
Registers
User Data
Holding
Register
S/PDIF XMT
Port Status
Register
Audio Data
Shift
Registers
Validity Bit
Generation
Aux Data
Shift
Registers
Ctl/Channel
Stat Shift
Registers
User Data
Shift
Register
MUX
Bi-Phase
Mark
Encoder
Line
Driver
SPDO
CCLK
DCLK
S/PDIF XMT
Control
Logic
S/PDIF XMT
Clock
Divider
Preamble
Generation
Parity
Generation
VIRTUAL WRITE MASTER
Audio streams may be directed back to host memory f rom t he DSP domain. The VWM has a data buffer capable of
storing enough audio data to burst into the host memory. The VWM is a simplified version of DMA and has more stringent requirements on which and how many pages need to be allocated.
Using the VWM, the system programmer can redirect audio streams processed by the SAA7785 ThunderBird Aveng-
TM
er
device and use them in any other audio device that resides in the system. The VWM is more efficient than the
DMA and should be the device of choice when redirecting audio streams back to the host. The device supports audio
sample rates from 8 to 48 KHz.
1999 Nov 12 17
Philips Semiconductors Preliminary Specification
ThunderBird AvengerTM PCI Audio SAA7785
Accelerator
Game Port
The SAA7785 ThunderBird AvengerTM Game Port interface is designed to emulate the PC-AT based legacy joystick
operation as well as support of a digital joystick mode. The legacy or analog, type of operation is designed to support all
legacy software that uses the original joystick address and the method for resolving the joystick axes positions. The
Digital Mode is designed to reduce the joystick overhead by resolv ing the joyst ick pos ition directly and to support applications that use DirectInput.
The legacy joystick used a one shot multi-vibrator on each of the four joystick potentiometers. These one shots were
set up to deliver a pulse that was proportional to the resistor value of the joystick potentiometers. Software would them
poll the one shots to see if they had been set to the original value. The time it took for each axes to return to the original
value was resolved into a position by the legacy software. The SAA7785 ThunderBird Avenger
based one shot circuit to support legacy games that use the PC -AT joyst ick. The joystick button v alues were routed
directly to the system bus where only a decode was required to read the value of the button. Software would poll the
buttons as well. All button and joystick axes data is returned in a single byte wide register.
Game Port Legacy I/O Register
This register is the legacy mode register for the 558 based joystick. When in “analog” mode, this register is aliased to
respond to addresses at base + (0-7) . Reads fr om this regist er will poll the status of the joystick but tons and are used
to resolve the position. Writes to this register will discharge the external capacitors to emulate the 558 one shots. Software can then poll the joystick register bit to resolve eac h of the joys tick ax es positions by timing. The joystick butt on
register bits have meaning in both the digital and analog modes. The axes bits are only valid for analog mode.
TM
emulates the 558
TABLE 3 Game Port 558-Based Register - GAMEPORT (RO)
I/O GMBASED7D6D5D4D3D2D1D0
Offset 1h JOYB_2 JOYB_1 JOYA_2 JOYA_1 JOYB_Y JOYB_X JOYA_Y JOYA_X
POR Value 11110000
Bit Name R/W Function
7 JOYB_2 RO Joystick B button 2 stat us. The joyst ick butt on s tatus bits are cleared when
the respective joystick button is pressed.
6 JOYB_1 RO Joystick B button 1 status.
5 JOYA_2 RO Joystick A button 2 status.
4 JOYA_1 RO Joystick A button 1 status.
3 JOYB_Y RO Joystick B y-c oordinate. Can also be referred to as position 3.
2 JOYB_X RO Joystick B x-c oordinate. Can also be referred to as position 2.
1 JOYA_Y RO Joystick A y-c oordinate. Can also be referred to as position 1.
0 JOYA_X RO Joystick A x-c oordinate. Can also be referred to as position 0.
1999 Nov 12 18
Philips Semiconductors Preliminary Specification
ThunderBird AvengerTM PCI Audio SAA7785
Accelerator
SAA7785 SIGNAL DEFINITIONS
PCI LOCAL BUS INTERFACE SIGNALS
AD[31:0] PCI Address/Data
AD[31:0] contains a physical byte address during the first clock of a PCI transaction, and data
during subsequent clocks.
When the SAA7785 is a PCI master, AD[31:0] are outputs during the address phase of a transaction. They are either inputs or outputs during the data phase, depending on the type of PCI
cycle in process.
When the SAA7785 is a PCI slave, AD[31:0] are inputs during the address phase. They are
either inputs or outputs during the data phase, depending on the type of PC I cycle in process.
C/BE#[3:0] PCI Bus Command and Byte Enables
C/BE#[3:0] defines the bus command during the first cloc k of a PCI transaction, and the byte
enables during subsequent clocks.
C/BE#[3:0] are outputs when the SAA7785 is a PCI bus master and inputs when it is a PCI bus
slave.
DEVSEL# PCI Bus Device Select
When the SAA7785 is a PCI bus master the SAA7785 uses DEVSEL# to determine whether a
master abort should occur if DEVSEL# is not sampled active by clock 5 of the transaction, or to
determine whether a cycle is to be aborted or retried when a target-initiated termination occurs.
When the SAA7785 is a PCI bus slave, DEVSEL# is an output which the SAA7785 drives LOW
during the second PCLK after FRAME# assert ion to the end of a transac tion if t he SAA7785 is
selected.
FRAME# PCI Bus Cycle Frame
When the SAA7785 is a PCI mas t er, FRAME# is an output which indicates the beginning of a
SAA7785-initiated bus transaction. While FRAME# is asserted data transfers continue. When
FRAME# is deasserted the transaction is in the final data phase.
When the SAA7785 is a PCI s lave, FRAME# is an input that initiates an I/ O, memory or c onfiguration register access if the SAA7785 is selected for the transaction. The SAA7785 latches the
C/BE#[3:0] and AD[31:0] signals on the PCLK edge on which it first samples FRAME# active.
IRDY# PCI Bus Initiator Ready
When the SAA7785 is a PCI mast er, IRDY # is an output which indicates the SA A7785’s ability
to complete the data phase of the current transaction. It is always asserted from the PCLK
cycle after FRAME# is asserted to the last clock of the transaction.
When the SAA7785 is a PCI slave, IRDY# is an input which causes the SAA7785 to hold-off
completion of a read or write cycle until sampled active.
1999 Nov 12 19
Philips Semiconductors Preliminary Specification
ThunderBird AvengerTM PCI Audio SAA7785
Accelerator
STOP# PCI Bus Stop (Target Initiated Termination)
When the SAA7785 is a PCI mas t er, STOP# is an input which causes the SAA7785 t o complete, abort or retry the transfer, depending on the stat e of TRDY# and DEVS EL#.
When the SAA7785 is a PCI slave, it drives STOP# as active (LOW) to terminate or retry a
transaction.
TRDY# PCI Bus Target Ready
When the SAA7785 is a PCI master, TRDY# is an input which indicates the target agent’s ability to complete the data phase of the transaction. After initiation of a PCI bus transaction, the
SAA7785 inserts wait cycles until TRDY# is sampled active.
When the SAA7785 is a PCI slav e, it drives TRDY# act ive to indicate that the SAA7785 has
sampled the data from AD[31:0] during a write phase, or presented valid data on AD[31:0] during a read phase.
PAR PCI Bus Parity
When the SAA7785 is a PCI master, it drives PAR to reflect the correct value for even parity on
the AD[31:0] and C/BE#[3:0] buses one clock after the address phase and after each write data
phases.
When the SAA7785 is a PCI slav e, it drives PAR to ref lect t he correct value for even parity on
the AD[31:0] and C/BE#[3:0] buses one clock af ter completion of each read data phase.
PCREQ# PC/PCI DMA Request
This signal requests DMA series from an external chipset that supports PC/PCI protocols. The
SAA7785 chip asserts PCGNT# according to the desired DMA channel required by either the
SoundBlaster or AC97 interfaces. The requested channel is encoded serially on the PCGNT#
pin.
The SAA7785 will become the bus ow ner w hen it r ece ives an ass erted PCGNT# signal. This
handshaking is synchronous to PCLK.
PCGNT# PC/PCI DMA Grant
An asserted PCGNT# pin indicates that t he external P C/ PCI master arbiter has granted DMA
services to the encoded DMA channel to the requesting DMA agent on the SAA7785 chip.
REQ# PCI Bus Request
This signal controls the PCI bus arbitration between the SAA7785 chip and the PC I mas ter
arbiter. When REQ# is asserted, the SAA7785 indicates a desire to become the PCI bus owner.
The SAA7785 will become the bus owner when it rec eives an ass erted grant signals (GNT# is
LOW). This handshaking is synchronous to PCLK.
REQ# is three-stated while RST# is active.
1999 Nov 12 20
Philips Semiconductors Preliminary Specification
ThunderBird AvengerTM PCI Audio SAA7785
Accelerator
GNT# PCI Bus Grant
An asserted GNT# pin indicates that the PCI master arbiter has granted bus ownership to the
SAA7785 chip.
INTA# PCI Bus Interrupt A
The interrupt output is a PCI compatible active low level sensitive interrupt. It is only used if the
SAA7785 is used in a non Common Architecture system. Otherwise it is tri-stated. I t is driven
low when any of the internal interrupts are asserted.
PERR# PCI Bus Parity Error
This signal indicates a data parity error for any cycle type other than a Special Cycle command.
PERR# is made active two clocks after the completion of the data phase which caused the parity error. This error signal may result in the generation of a non-maskable interrupt (NMI) or
other high priority interrupt sent to the CPU.
SERR# PCI Bus System Error
This signal indicates an address parity error, data parity errors on Special Cycle commands or
any other catastrophic system error. SERR# is an open-drain bidirectional pin which is driven
low for a single PCLK cycle by the agent reporting the error. This error may result in the generation of a non-maskable interrupt (NMI) or other high priority interrupt sent to the CPU.
IDSEL Initialization Device Select
IDSEL is used as a chip select during configuration register read and write operations. One
system board address line from AD[31:11] is used as IDSEL to select the SAA7785 configuration space in the SAA7785 chip when used on the PCI bus.
CLKRUN# PCI Bus Clock Run Request
The SAA7785 uses CLKRUN# according to the Mobile PCI protocol to start the PCI clock or
keep the clock running whenever an internal PCI device requires it .
PCLK PCI Bus Clock Input
PCLK is the PCI bus clock input. It is used to synchronize all PCI bus operations and typically
runs at 33MHz.
RST# PCI Bus Reset
An active low version of the system reset, this signal causes the PCI interface to return to the
idle states in all state machines and asynchronously three-states all PCI bus signals. All registers will be reset to their default values as well. The CODEC interface line should be all driven
inactive along with the external memory interface. This reset will assert the DSP reset.
PME# PCI Bus Power Management Event
Reserved.
1999 Nov 12 21
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