Philips saa7390 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

SAA7390

High performance Compact Disc-Recordable (CD-R) controller

Preliminary speciﬁcation File under Integrated Circuits, IC01

1996 Jul 02

Philips Semiconductors Preliminary speciﬁcation

High performance Compact Disc-Recordable (CD-R) controller

CONTENTS

1 FEATURES

1.1 General

1.2 Interface logic (CD-ROM operation)

1.3 Hardware third-level error correction

1.4 Interface logic (CD-R operation)

1.5 DRAM buffer controller (256 kbytes × 8, 1 Mbyte × 8, 4 Mbytes × 8)

1.6 Additional product support

2 GENERAL DESCRIPTION 3 QUICK REFERENCE DATA 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING 7 FUNCTIONAL DESCRIPTION

7.1 Input clock doubler

7.2 Block encoder

7.3 Front-end

7.4 Track descriptor block

7.5 Buffer manager

8 MICROCONTROLLER INTERFACE

8.1 Microprocessor interface status register

8.2 Microcontroller interface command register

8.3 Microprocessor interrupts

8.4 Microcontroller RAM organization

9 FRONT PANEL AND MISCELLANEOUS

CONTROL SIGNALS

9.1 S2B UART registers

9.2 SPI UART registers

9.3 Track Descriptor Block (TDB) generation

9.4 Miscellaneous control registers

10 FRONT-END

10.1 Minute-second frame addressing and header information

10.2 Front-end status and control

11 BUFFER MANAGER

SAA7390

11.1 Front-end to buffer manager interface

11.2 Microcontroller to buffer manager interface

11.3 ECC to buffer manager interface

11.4 SCSI to buffer manager interface

11.5 Miscellaneous buffer manager considerations

11.6 Host interface related registers

11.7 CDB2 related registers 12 FRAME BUFFER ORGANIZATION 13 SUMMARY OF CONTROL REGISTER MAP 14 LIMITING VALUES 15 OPERATING CHARACTERISTICS

15.1 I2S-bus timing; data mode

15.2 EIAJ timing; audio mode

15.3 R-W timing (see Fig.17)

15.4 C-flag timing (see Fig.18)

15.5 S2B interface timing

15.6 SPI interface timing

15.7 Microprocessor interface

15.8 Host interface

15.9 DRAM interface (the SAA7390 is designed to operate with standard 70 ns DRAMs)

16 PACKAGE OUTLINE 17 SOLDERING

17.1 Introduction

17.2 Reflow soldering

17.3 Wave soldering

17.4 Repairing soldered joints

18 DEFINITIONS 19 LIFE SUPPORT APPLICATIONS

1996 Jul 02 2

Philips Semiconductors Preliminary speciﬁcation

High performance Compact Disc-Recordable (CD-R) controller

1 FEATURES

1.1 General

• 8× speed CD-ROM, 4× speed Compact Disc-Recordable (CD-R) controller

• 16.9 Mbytes/s burst rate to host controller

• High performance CD-ROM and CD-R interface logic

• 128 pin QFP package.

1.2 Interface logic (CD-ROM operation)

• Full 8× speed hardware operation

• Block decoder

• Sector sequencer

• CRC checking of Mode 1 and Mode 2, Form 1 sectors

• 212 ms watch-dog timer

• Sub-code interface with synchronization

• C-flag interface for absolute time stamp.

1.3 Hardware third-level error correction

• Third-level correction provides superior performance in unfavourable conditions

• Full hardware error correction to reduce microcontroller overhead

• Corrections are automatically written to the DRAM frame buffer.

1.4 Interface logic (CD-R operation)

• Block encoder (using a modified CDB2).

1.5 DRAM buffer controller (256 kbytes × 8,

1 Mbyte × 8, 4 Mbytes × 8)

• DRAM buffer manager

• Ten level arbitration logic

• Utilizes low cost 70 ns DRAMs

• Page mode DRAM access for high-speed error

correction and host interface data transfers

• Data organization by 3 kbytes frames.

1.6 Additional product support

SAA7390

• Dedicated Serial Peripheral Interface (SPI)

• Third level error correction and encoding

• 80C32 microcontroller interface

• 53CF90 or 53CF92A/B fast SCSI processor interface

(may also use ATAPI processor).

2 GENERAL DESCRIPTION

The SAA7390 is a high integration ASIC that incorporates all of the logic necessary to connect a CD-60 based decoder to a SCSI or ATAPI host. It also supports a data path from the host to the CDCEP (compact disc encoder) for CD-R applications. An 80C32 microcontroller and a 53CF94/92A (or an ATAPI interface device) are required to provide the full block encode/decode functions. The following functions are supported:

• Input clock doubler

• Block encoder (using a modified CDB2)

• Block decoder

• CRC checking of Mode 1 and Mode 2, Form 1 sectors

• Red book audio pass through to SCSI or ATAPI

• Sub-code and Q-channel support

• Dedicated S2B interface UART

• Dedicated SPI interface UART

• Up to 4 Mbytes DRAM buffer manager

• Third-level error correction and encoding

• Automatic storage of audio and data

• 80C32 microcontroller interface

• 53CF90 or 53CF92A/B fast SCSI or Wapiti ATAPI

processor interface.

The SAA7390 uses a 33.8688 MHz clock and is capable of accepting data at eight times (n = 8 or 1.4 Mbytes/s) the normal CD-ROM data rate. The minimum host burst rate capability of the SAA7390 is 5 Mbytes/s.

Third level error correction hardware is included to improve the correction efficiency of the system. The buffer manager hardware utilizes a ten-level arbitration unit and can stop the clock to the static microcontroller to emulate a wait condition when necessary. The host interface is capable of burst rates to 16.9 Mbytes/s.

• Input clock doubler

• All control registers mapped into 80C32 special function

memory space

• Red book audio pass through to host interface

• Sub-code and Q-channel support

1996 Jul 02 3

Philips Semiconductors Preliminary speciﬁcation

High performance Compact

SAA7390

Disc-Recordable (CD-R) controller

The SAA7390 comprises four major functional blocks:

• The front-end block connects to the external CD-60 based decoder and fully processes the incoming data stream

• The buffer manager block provides the address generation and timing control for the external DRAMs

• The ECC block performs the error correction functions in hardware on the data stored in the DRAM buffer.

• The block encoder function (realized via a modified CDB2) serializes the data from the buffer, appends the sync pattern, header, sub-header, third level ECC parity and EDC bytes as necessary, performs the required scrambling and outputs them to the CDCEP using a special data clock (98 clock cycles per word selection period).

3 QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

amb

stg

digital supply voltage 4.5 5.0 5.5 V operating ambient temperature 0 − 70 °C storage temperature −55 − +150 °C

4 ORDERING INFORMATION

TYPE

NUMBER

SAA7390GP

Note

1. This device uses a Symbios logic package.

(1)

NAME DESCRIPTION VERSION

SQFP128 plastic quad ﬂat package; 128 leads (lead length 1.6 mm);

body 14 × 20 × 2.8 mm

PACKAGE

SOT387-2

1996 Jul 02 4

Philips Semiconductors Preliminary speciﬁcation

High performance Compact Disc-Recordable (CD-R) controller

5 BLOCK DIAGRAM

handbook, full pagewidth

data subcode

CD

DECODER

BASIC

ENGINE

DATA

CONVERTER

AND SUB-CODE

UART

data subcode C-flag

WRITE I/F

LAYERED

CORRECTOR

SAA7390

BUFFER MANAGER

ERROR

256K × 8 to 4M × 8

DRAM BUFFER

ENCODE

MICROCONTROLLER INTERFACE

BUFFER

MAPPER

SPI UART

GENERIC

EXTERNAL

INTERFACE

S2B UART

SAA7390

SCSI 

or 

ATAPI

interface

S2B

interface

MGE518

80C32 MICROCONTROLLER

128K × 8 ROM

SPI

interface

Fig.1 Block diagram (simplified).

6 PINNING

All input and bidirectional signals are TTL level with Schmitt-trigger logic, with the exception of OSCIN. All output signals are TTL levels unless otherwise stated. (PD = internal pull-down; PU = internal pull-up).

SYMBOL PIN I/O TYPE DESCRIPTION

DA0 1 O DRAM address bus; bit DA0 DA1 2 O DRAM address bus; bit DA1 DA2 3 O DRAM address bus; bit DA2 V

SS1

4 − ground 1 DA3 5 O DRAM address bus; bit DA3 DA4 6 O DRAM address bus; bit DA4 DA5 7 O DRAM address bus; bit DA5 V

SS2

8 − ground 2 DA6 9 O DRAM address bus; bit DA6

1996 Jul 02 5

Philips Semiconductors Preliminary speciﬁcation

High performance Compact

SAA7390

Disc-Recordable (CD-R) controller

SYMBOL PIN I/O TYPE DESCRIPTION

DA7 10 O DRAM address bus; bit DA7 V

DD1

DA8 12 O DRAM address bus; bit DA8 DA9 13 O DRAM address bus; bit DA9 DA10 14 O DRAM address bus; bit DA10 RAS 15 O DRAM row address section; active LOW CAS 16 O DRAM column address selection; active LOW DWR 17 O DRAM write; active LOW DOE 18 O DRAM output enable; active LOW DD0 19 I/O PD DRAM data bus; bit DD0 V

DD2

DD1 21 I/O PD DRAM data bus; bit DD1 DD2 22 I/O PD DRAM data bus; bit DD2 DD3 23 I/O PD DRAM data bus; bit DD3 DD4 24 I/O PD DRAM data bus; bit DD4 V

SS3

DD5 26 I/O PD DRAM data bus; bit DD5 DD6 27 I/O PD DRAM data bus; bit DD6 DD7 28 I/O PD DRAM data bus; bit DD7 COM_IN 29 I serial data in from basic engine COM_OUT 30 O serial data out to basic engine COM_CLK 31 O serial data clock COM_ACK 32 I serial data acknowledge TRAYSW 33 I PU active LOW when tray is in EJECT 34 I PU opens tray; active LOW LQDATA 35 O latched qualiﬁed data LWCLK 36 O latched word clock V

DD3

LED 38 O CMOS; 24 mA panel LED; active LOW; open drain; 24 mA (min.) sink capability V

SS4

SCLK 40 O audio data clock V

SS5

SYSRES 42 O system reset; active HIGH SYSRES 43 O system reset; active LOW V

DD4

GPIO3 45 I/O PD general purpose input/output 3 GPIO4 46 I/O PD general purpose input/output 4 VOLUP 47 I PU volume up; active LOW VOLDN 48 I PU volume down; active LOW UC_AD0 49 I/O microprocessor multiplexed address/data bus; bit UC_AD0 UC_AD1 50 I/O microprocessor multiplexed address/data bus; bit UC_AD1

11 − power supply 1

20 − power supply 2

25 − ground 3

37 − power supply 3

39 − ground 4

41 − ground 5

44 − power supply 4

1996 Jul 02 6

Philips Semiconductors Preliminary speciﬁcation

High performance Compact

SAA7390

Disc-Recordable (CD-R) controller

SYMBOL PIN I/O TYPE DESCRIPTION

UC_AD2 51 I/O microprocessor multiplexed address/data bus; bit UC_AD2 UC_AD3 52 I/O microprocessor multiplexed address/data bus; bit UC_AD3 V

SS6

UC_AD4 54 I/O microprocessor multiplexed address/data bus; bit UC_AD4 UC_AD5 55 I/O microprocessor multiplexed address/data bus; bit UC_AD5 UC_AD6 56 I/O microprocessor multiplexed address/data bus; bit UC_AD6 UC_AD7 57 I/O microprocessor multiplexed address/data bus; bit UC_AD7 V

DD5

UC_LA0 59 O latched lower address; bit UC_LA0 UC_LA1 60 O latched lower address; bit UC_LA1 UC_LA2 61 O latched lower address; bit UC_LA2 V

SS7

UC_LA3 63 O latched lower address; bit UC_LA3 UC_LA4 64 O latched lower address; bit UC_LA4 UC_LA5 65 O latched lower address; bit UC_LA5 UC_LA6 66 O latched lower address; bit UC_LA6 UC_LA7 67 O latched lower address; bit UC_LA7 V

SS8

PCLK 69 O 33.8688 MHz microprocessor clock V

DD6

ALE 71 I address latch enable UC_WR 72 I write enable UC_RD 73 I read enable INT 74 O CMOS interrupt to microcontroller; active LOW; open drain UC_A8 75 I upper address; bit UC_A8 UC_A9 76 I upper address; bit UC_A9 UC_A10 77 I upper address; bit UC_A10 SYS_SYNC 78 I system synchronization from basic engine UC_A11 79 I upper address; bit UC_A11 UC_A12 80 I upper address; bit UC_A12 UC_A13 81 I upper address; bit UC_A13 COM_SYNC 82 I communication synchronization from basic engine UC_A14 83 I upper address; bit UC_A14 UC_A15 84 I upper address; bit UC_A15 SD0 85 I/O internal data bus; bit SD0 V

DD6

SD1 87 I/O internal data bus; bit SD1 SD2 88 I/O internal data bus; bit SD2 V

SS9

SD3 90 I/O internal data bus; bit SD3 SD4 91 I/O internal data bus; bit SD4

53 − ground 6

58 − power supply 5

62 − ground 7

68 − ground 8

70 − power supply 6

86 − power supply 6

89 − ground 9

1996 Jul 02 7

Philips Semiconductors Preliminary speciﬁcation

High performance Compact

SAA7390

Disc-Recordable (CD-R) controller

SYMBOL PIN I/O TYPE DESCRIPTION

SD5 92 I/O internal data bus; bit SD5 SD6 93 I/O internal data bus; bit SD6 SD7 94 I/O internal data bus; bit SD7 V

SS10

DREQ 96 I PD DMA request DACK 97 O DMA acknowledge; active LOW HOSTRD 98 O read enable; active LOW HOSTWR 99 O write enable; active LOW HOSTSEL 100 O chip select; active LOW CSAB 101 I word strobe for write data CCLAB 102 I clock for write data CDAAB 103 O write data stream RXS2B 104 I PU receive data TXS2B 105 O transmit data CPR 106 O ready to accept data; active LOW SCSIRST 107 I reset from SCSI bus; active LOW POR 108 I power-on reset; active LOW TCL_GPIO1 109 I/O PD general purpose input/output 1 (also used as test-mode clock) SPR 110 I ready to send data; active LOW TDA_GPIO2 111 I/O PD general purpose input/output 2 (also used as test-mode data) HFD 112 I laser on and focused status; active LOW KILL 113 I PU mute audio; active LOW V

SS11

MCOUT 115 O motor control output from PWM MCIN 116 I PD motor control input from decoder RXSUB 117 I PU sub-code input CFLAG 118 I PU C1 and C2 status V

SS12

OSCIN 120 I input clock from decoder V

DD7

CLAB 122 I clock input DAAB 123 I data input WSAB 124 I word strobe input EFAB 125 I error ﬂags V

SS13

CLK34 127 O 33.8688 MHz output clock V

DD8

95 − ground 10

114 − ground 11

119 − ground 12

121 − power supply 7

126 − ground 13

128 − power supply 8

1996 Jul 02 8

Philips Semiconductors Preliminary speciﬁcation

High performance Compact Disc-Recordable (CD-R) controller

handbook, full pagewidth

CDAAB

RXS2B

TXS2B

CPR

SCSIRST

POR

TCL_GPIO1

SPR

TDA_GPIO2

HFD KILL

SS11

MCOUT

MCIN

RXSUB

CFLAG

SS12

OSCIN

DD7

CLAB DAAB

WSAB

EFAB

SS13

CLK34

DD8

103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128

CCLAB

CSAB

HOSTSEL

HOSTWR 9998979695949392919089888786858483828180797877767574737271706968676665

102

101

100

432

SS1

DA0

DA1

DA2

HOSTRD

DACK

DA3

DA4

DREQ

DA5

SS10

SS2

SD7

DA6

SD6

DA7

SD5

DD1

SD4

DA8

SD3

DA9

DA10

SS9

SD2

RAS

SD1

CAS

DD6

SD0

SAA7390

DWR

DOE

UC_A15

UC_A14

DD0VDD2

UC_A12

COM_SYNC

UC_A13

DD1

DD2

DD3

UC_A11

SYS_SYNC

SS3

DD4

UC_A10

UC_A9

DD5

DD6

UC_A8

DD7

INT

UC_RD

COM_IN

COM_OUT

UC_WR

ALE

COM_CLK

COM_ACK

DD6

PCLK

EJECT

TRAYSW

SS8

UC_LA7

LWCLK

LQDATA

SAA7390

UC_LA6

UC_LA5

UC_LA4

UC_LA3 V

SS7

UC_LA2

UC_LA1

UC_LA0 V

DD5

UC_AD7

57 56

UC_AD6 UC_AD5

55 54

UC_AD4 V

SS6

UC_AD3

UC_AD2

UC_AD1

UC_AD0

VOLDN

VOLUP

GPIO4

GPIO3 V

DD4

SYSRES

43 42

SYSRES V

41 40

SCLK V

MGE517

LED

DD3

SS5

SS4

Fig.2 Pin configuration.

1996 Jul 02 9

Philips Semiconductors Preliminary speciﬁcation

High performance Compact Disc-Recordable (CD-R) controller

left

output

AUDIO

TDA8425

PROCESSOR

RAM

output

DAC

AND

CD-ROM

ENCODER

right

TDA1545A

SAA7390

DECODER

ATAPI

interface

WAPITI

53CF90

SCSI-2

interface

53CF92A

53CF92B

ATAPI/SCSI

INTERFACE

80C32

MICRO

CD-ROM

SAA7390

MGE519

book, full pagewidth

DISC

COMPACT

DISC MOTOR

LO9465

DECODER

CDR650

S83C752

CONTROLLER

L2465

CD LOADER

DISC

COMPACT

ENCODER

SIGNAL

PROCESSOR

TDA1371

TDA1372

MICRO

SERVO

DIGITAL

CONTROLLER

SERVO

DIGITAL

DRIVERS

CDM24

3-BEAM

MECHANISM

OQ8845

OQ8844

Fig.3 Double-speed write quad-speed play CD-R system D65420 with ATAPI or SCSI-2 interface.

1996 Jul 02 10

Philips Semiconductors Preliminary speciﬁcation

High performance Compact Disc-Recordable (CD-R) controller

7 FUNCTIONAL DESCRIPTION

7.1 Input clock doubler

To facilitate compatibility of the SAA7390 with all of the available CD decoders, a clock doubler has been included. This clock doubler may take a 16.9344 MHz clock and double this when requested to do so by the microcontroller. Logic has been included to remove the possibility of a ‘runt’ clock pulse when the doubler is engaged. Once engaged, the only way to disengage it is via a reset condition.

7.2 Block encoder

To support the write function, a modified version of the CDB2 function has been included. The block encoder accepts parallel data from the buffer manager, serializes it, calculates the CRC and third-level ECC parity bytes and appends them when and where necessary. The RAM required during the parity calculation is included on the SAA7390.

The following modifications to the CDB2 have been made:

• Word select in bypass mode has been inverted to match the data mode

• The ‘end-of-frame’ signal is now generated during the bypass and CD-ROM mode and will interrupt the microcontroller at the end of each frame

• The ‘end-of-frame’ signal is also used to correctly synchronize between bypass mode and regular data mode at the end of a frame. The modes programmed into the CDB2 command, header, sub-header and block size registers will automatically switch in or out at the end of frame

• DRQ in CCMD is also synchronized to frame boundaries using the ‘end-of-frame’ signal. This change is valid for both bypass and regular data modes.

7.3 Front-end

The front-end section of the SAA7390 is identical to the front-end of the mini-SEQUOIA (also found on the SAA7385), with the exception of the Serial Peripheral Interface (SPI). The front-end is comprised of many sub-sections.

7.3.1 B

The block decoder first reverses the bits of each received byte and then runs them through a linear feedback shift register to be de-scrambled. The polynomial used to

de-scramble the serial data is as follows: X

LOCK DECODER

+X+1

SAA7390

It also detects and tests the synchronization field and will start the data clock when commanded. The de-scrambled header is assembled into four registers with header ready and header error status (see HDRRDY and HDRERR in RDDSTAT). The data clock does not have to be enabled to receive valid headers.

Also included in this section is the logic required to decide when to automatically start collecting data and sub-code information based on the contents of the Q-channel registers.

7.3.2 S The sector sequencer de-serializes the data and error

flags from the block decoder and determines when to:

• Write data to the buffer

• Write flags to the buffer

• Test the header to determine the Mode

• Test the sub-header to determine the Form

• Test the CRC

• End the sector and write the status byte to the buffer.

Included in the sector sequencer is the CRC generator which checks each Yellow book or Green book sector as it is shifted into the SAA7390 in accordance with the following polynomial:

32+X31+X16+X15+X4+X3

X The status of each sector is saved and written to the buffer

at the end of the sector.

7.3.3 S A UART which samples asynchronous bits on a 24 clocks

per bit basis is included. This is required because the CD-60 based decoders output the sub-code data at nominally 24 clocks per bit, but not synchronized to the data. Also included is a sub-code synchronization detector which senses the beginning of each new sector of sub-code information. The serial sub-code information is assembled into bytes in the following order:

Data bits 7 to 0 = 0, Q, R, S, T, U, V and W.

As each byte is assembled, it is sent to the buffer manager to be written to the DRAM buffer. At the same time, the Q-channel bits are assembled into bytes and sent to the buffer. All Q-channel bytes except CRC are sorted in registers for use by the microcontroller. The Q-channel CRC (last two bytes) is checked just before the end of the sub-code sector. If the CRC check fails, BADQ in RDDSTAT is available to the microcontroller and is written into the buffer at the end of the sector.

ECTOR SEQUENCER

+X+1

UB-CODE RECEIVE AND Q-CHANNEL EXTRACTOR

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Philips Semiconductors Preliminary speciﬁcation

High performance Compact Disc-Recordable (CD-R) controller

When the ten Q-channel registers have been updated, QFRMRDY in RDDSTAT is set. The ten Q-channel registers are valid while QFRMRDY is set. In the audio mode, HDRRDY in RDDSTAT generates this interrupt, but the QFRMRDY bit will still be available as status to the microcontroller.

7.3.4 C-

The C-flag bits, or corrector flags, are also 24 data clocks long and reception of these bits is achieved using the same method as for the sub-code; in this event, the C-flag data is synchronized to the data.

The difference is that only one bit is used; F1, the absolute time synchronization information. When in audio mode and ENABRED in FECTL is set, receipt of F1 set will start the internal data clock after the next rising edge of word strobe (WSAB) which is the left channel sample when the CD-60 decoder is programmed for EIAJ audio format. When in audio mode, the Q-channel information provides the MSF address and the F1 flag provides the start of frame information; together these provide an absolute byte address on the disc.

7.3.5 S2B UART

This UART is provided for communication with a second slave microcontroller. It is hard-wired for one start-bit, eight data bits, a parity bit and one stop bit. Parity testing can be programmed to be either odd parity or even parity. Parity error and over-run status are provided via PE and OVRRUN in S2BSTAT. Selectable baud rates of

31.25, 62.5 and 187.5 kbaud are available via S2BSEL1

and S2BSEL0 in BRGSEL. Once the start-bit is found, the data sampling time does not adapt dynamically, therefore parity errors may occur depending on the baud rate selected.

FLAG RECEIVER

SAA7390

7.3.6 SPI UART This UART is provided for communication with a second

slave microcontroller used in Philips CD-R engines.

7.3.7 W A pair of counters are included which output a 967 µs reset

pulse to the entire chip and the SYSRES and SYSRES pins if the timer is not reset during the 212 ms time-out period. The watch-dog timer is reset by setting RWMD in FECTL HIGH then LOW. If RWMD is left HIGH, the watch-dog function is disabled.

7.3.8 G The final block of logic in the front-end consists of:

a programmable, linear pulse-width modulator for spindle-motor control; an address de-multiplexer for the address/data bus of the microcontroller; plus audio multiplexing and muting circuitry for full control of Red book audio data to an external Digital-to-Analog Converter (DAC).

7.4 Track descriptor block

Logic has been included to simplify the creation of the track descriptor block. This is achieved by allowing one frame to be repeated a selectable number of times. Once this repeated pattern is complete, the normal data is then sent to the front-end.

ATCH-DOG TIMER

LUE LOGIC (GLIC)

1996 Jul 02 12

Philips Semiconductors Preliminary speciﬁcation

High performance Compact Disc-Recordable (CD-R) controller

7.5 Buffer manager

The buffer manager provides the arbitration for the different processes that wish to access the DRAM buffer. These processes include the front-end, microcontroller requests, CDB2 accesses, ECC accesses, host interface requests and DRAM refreshing.

To manage a DRAM interface with up to four devices requesting access to the DRAM, the following priority scheme is used. The DRAM control logic will start an access on the next rising edge of the clock after a request is received. If two or more requests are pending then the priority is:

1. Front-end (highest priority)

2. A refresh cycle (required every 15.6 µs) granted

priority for one access

3. Microcontroller requests

4. Host interface requests

5. ECC requests (lowest priority).

SAA7390

A burst access by ECC or host interface will only be interrupted by a higher priority access request.

In addition to the priority logic, logic is required for the front-end sources of data. The priority is; CDB2 requests (highest) frame data, flag data, sub-code data, Q-channel data and finally status byte. All front-end sources are granted priority over the host interface logic, ECC, refresh and data will be written into the frame store during the next cycle. However, the microcontroller has priority over the lower three front-end sources and will be granted an access after front-end frame data or flag data is written to memory.

The required timing (see Figs 4 to 11) operate with the industry standard 70 ns DRAMs. The interface is designed to operate with 256 kbytes, 1 Mbyte, and 4 Mbytes of DRAM. A single byte access cycles requires five clock cycles of 29.5 ns each, totalling 147.5 ns.

handbook, full pagewidth

CLOCK

RAS

CAS

ADDRESS ROW COL

DATA

DOE

Fig.4 Byte mode single access read cycle.

1996 Jul 02 13

latch data

MGE392

Philips Semiconductors Preliminary speciﬁcation

High performance Compact Disc-Recordable (CD-R) controller

handbook, full pagewidth

CLOCK

RAS

CAS

ADDRESS

DATA

WRITE

ROW COL

SAA7390

DATA

MGE393

handbook, full pagewidth

CLOCK

ADDRESS ROW COL1 COL2 COL3 COL4

DATA

Fig.5 Byte mode single access write cycle.

RAS

CAS

latch latch latch

DOE

MGE394

Fig.6 ECC burst access read cycle.

1996 Jul 02 14

Philips Semiconductors Preliminary speciﬁcation

High performance Compact Disc-Recordable (CD-R) controller

handbook, full pagewidth

CLOCK

RAS

CAS

ADDRESS ROW COL1 COL2 COL3 COL4

DATA

WRITE

DATA1 DATA2 DATA3 DATA4

SAA7390

MGE395

handbook, full pagewidth

CLOCK

RAS

CAS

ADDRESS ROW COL1 COL2 COL3 COL4

DATA

DOE

Fig.7 ECC burst access write cycle.

latch data latch data latch data

MGE396

Fig.8 Host interface fast burst access read cycle (2 clocks).

1996 Jul 02 15

Philips Semiconductors Preliminary speciﬁcation

High performance Compact Disc-Recordable (CD-R) controller

handbook, full pagewidth

CLOCK

RAS

CAS

ADDRESS ROW COL1 COL2 COL3 COL4

DATA

WRITE

DATA1 DATA2 DATA3 DATA4

SAA7390

MGE397

handbook, full pagewidth

CLOCK

RAS

CAS

ADDRESS ROW COL1 COL2 COL3 COL4

DATA

DOE

Fig.9 Host interface fast burst access write cycle (2 clocks).

latch data latch data latch data

MGE520

Fig.10 Host interface standard burst access read cycle (3 clocks).

1996 Jul 02 16

Philips Semiconductors Preliminary speciﬁcation

High performance Compact Disc-Recordable (CD-R) controller

handbook, full pagewidth

CLOCK

RAS

CAS

ADDRESS ROW COL1 COL2 COL3 COL4

DATA

WRITE

DATA1 DATA2 DATA3 DATA4

SAA7390

MGE521

Fig.11 Host interface standard burst access write cycle (3 clocks).

8 MICROCONTROLLER INTERFACE

8.1 Microprocessor interface status register

Table 1 NUM_COR register: 0xF08E; note 1

DATA BYTE

MNEMONIC R/W

76543210

NUM_COR R NUM_COR7 to NUM_COR0

Note

1. Register 0xF08E indicates the number of corrections performed during the most recently executed

CORRECT_P_SYNDROMES or CORRECT_Q_SYNDROMES command. Note that NUM_COR is only valid after completion of the CORRECT_P_SYNDROMES or CORRECT_Q_SYNDROMES command, and becomes invalid upon execution of any other command.

Table 2 ECC_STATUS register: 0xF086; note 1

DATA BYTE

MNEMONIC R/W

765 4 3 2 1 0

ECCSTAT R −−−FLG_EQ0 CRC_EQ0 PS_EQ0 QS_EQ0 ECC_ACT

Note

1. Register 0xF086 provides status information on the current or last ECC command.

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Table 3 ECCSTAT deﬁnitions

MNEMONIC DESCRIPTION

ECC_ACT asserted while a command other than ASSERT_ABORT or RELEASE_ABORT remains active QS_EQ0 asserted when all Q syndromes are zero PS_EQ0 asserted when all P syndromes are zero CRC_EQ0 asserted when the CRC remainder calculated by the CRC_CALCULATE command is all zeros FLG_EQ0 asserted when all ﬂag bytes in ECC RAM are zero

8.2 Microcontroller interface command register

Table 4 ECCCTL register: 0xF085; note 1

MNEMONIC R/W

76543210

ECCCTL R/W −−−−ECC_COMMAND3 to ECC_COMMAND0

Note

1. The ECC_COMMAND definitions are explained in Table 5.

DATA BYTE

Table 5 Deﬁnitions of ECC_COMMAND3 to ECC_COMMAND0

EEC_COMMAND DESCRIPTION

0000 ASSERT_ABORT 0001 RELEASE_ABORT 0010 CALCULATE_SYNDROMES (not Mode 2, Form 1)

0011 CALCULATE_SYNDROMES (Mode 2, Form 1) 0100 CRC_RECALCULATE (not Mode 2, Form 1) 0101 CRC_RECALCULATE (Mode 2, Form 1)

0110 COPY_RESULTS (not Mode 2, Form 1)

0111 COPY_RESULTS (Mode 2, Form 1) 1000 CORRECT_P_SYNDROMES 1001 CORRECT_Q_SYNDROMES

1100 TEST_ECC_ROM

1101 TEST_ECC_RAM_READ

1110 TEST_ECC_RAM_WRITE

Table 6 Command descriptions

COMMAND DESCRIPTION

ASSERT_ABORT Terminates any currently active operation and re-initializes the ECC logic. Remains in

reset state until occurrence of the RELEASE_ABORT command. At power-on reset, the ECC is in the ASSERT_ABORT state. All microprocessor status bits are reset when the ECC is in the ASSERT_ABORT state.

RELEASE_ABORT Terminates the ASSERT_ABORT command and enables activation of other

commands.

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COMMAND DESCRIPTION

CRC_RECALCULATE Calculate CRC remainder buffer data, storing result in ECC RAM and updating

microprocessor status bit CRC_EQ0. Mode 2, Form 1 uses address 16 : 2075, or 0 : 2067; note 1

CALCULATE_SYNDROMESPrepares buffer for correction, calculates P and Q syndromes, and copies error ﬂags

and CRC remainder from buffer to ECC RAM. The microprocessor status bits PS_EQ0, QS_EQ0 and FLAGS_EQ0 are updated at the end of this operation.

1. Copy header from buffer to ECC RAM (Mode 2, Form 1 only)

2. Write to the buffer. Not Mode 2, Form 1:

Address 0 → 0x00; Address1:10→0xFF; Address 11 → 0x00; Address 2068 : 2075 → 0x00

Mode 2, Form 1:

Address 0 → 0x00; Address1:10→0xFF; Address 11 : 15 → 0x00

3. Read header and frame data from buffer to calculate P and Q syndromes psyn[0 : 85].s1, psyn[0 : 85].s0, qsyn[0 : 51].s1 and qsyn[0 : 51].s0, storing results in ECC RAM

4. Copy error ﬂags from buffer to ECC RAM

5. Copy CRC remainder from buffer to ECC RAM

6. Update microprocessor status bits PS_EQ0, QS_EQ0 and FLAGS_EQ0.

COPY_RESULTS

Copies current ECC RAM contents to the buffer memory:

1. Copy header ﬂags from ECC RAM to buffer (Mode 2, Form 1 only)

2. Copy error Flags from ECC RAM to buffer

3. Copy CRC remainder from ECC RAM to buffer

4. Copy P syndromes from ECC RAM to buffer

5. Copy Q syndromes from ECC RAM to buffer.

CORRECT_P_SYNDROMESScan all P syndromes and perform P-syndrome calculation. The microprocessor status

bits PS_EQ0, QS_EQ0 and FLAGS_EQ0 are updated at the end of this operation.

CORRECT_Q_SYNDROMESScan all Q syndromes and perform Q-syndrome calculation. The microprocessor

status bits PS_EQ0, QS_EQ0 and FLAGS_EQ0 are updated at the end of this operation.

TEST_ECC_ROM Read each exponent and log in the alpha ROM to the NUM_COR register. This

command may only be terminated by the ASSERT_ABORT command. TEST_ECC_RAM_READ Read ECC RAM addresses 0 : 591 and copy to buffer addresses 0 : 591. TEST_ECC_RAM_WRITE Read buffer addresses 0 : 591 and copy to ECC RAM addresses 0 : 591.

Note

1. 16 : 2075 and 0 : 2067 are address frame offsets. The frame buffer organization is shown in Table 76.

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8.3 Microprocessor interrupts

An interrupts pulse is generated upon completion of any of the following commands:

• CALCULATE_SYNDROMES (not Mode 2, Form 1)

• CALCULATE_SYNDROMES (Mode 2, Form 1)

• CRC_RECALCULATE (not Mode 2, Form 1)

• CRC_RECALCULATE (Mode 2, Form 1)

• COPY_RESULTS (not Mode 2, Form 1)

• COPY_RESULTS (Mode 2, Form 1)

• CORRECT_P_SYNDROMES

• CORRECT_Q_SYNDROMES

• TEST_ECC_ROM

• TEST_ECC_RAM_READ

• TEST_ECC_RAM_WRITE.

If a command is aborted by the ASSERT_ABORT command, a spurious interrupt may be generated within five clock cycles of the ASSERT_ABORT command.

Table 7 Command execution times; note 1

COMMAND CYCLES

CALCULATE_SYNDROMES (not Mode 2, Form 1) 5604 186.8 2658 CALCULATE_SYNDROMES (Mode 2, Form 1) 5600 186.7 2654 CRC_RECALCULATE (not Mode 2, Form 1) 4136 137.9 2068 CRC_RECALCULATE (Mode 2, Form 1) 4120 137.3 2060 COPY_RESULTS (not Mode 2, Form 1) 1148 38.3 574 COPY_RESULTS (Mode 2, Form 1) 1156 38.5 578 CORRECT_P_SYNDROMES

(maximum addition per correction) CORRECT_Q_SYNDROMES

(maximum addition per correction) TEST_ECC_RAM_READ 1184 39.5 592 TEST_ECC_RAM_WRITE 1184 39.5 592

Note

1. All times indicated reflect two clock cycles per memory access for all accesses other than P and Q corrections. P and Q corrections reflect seven clock cycles per memory access. Execution times will be extended due to refresh timing, other buffer traffic, and configuration of nibble-wide memory.

8.3.1 I

NTERRUPT REGISTER DEFINITIONS

1466

157 888

167

TIME (µs)

at 33 MHz

48.9

5.2

29.6

5.6

MEMORY

ACCESSES

0 2

Two registers are used to control the operation of the interrupt logic. The register INTRMSK allows each interrupt to be enabled or disabled. INTRMSK and INTRFLG are cleared on reset to initially disable and clear all interrupts; the output latch controlling the INT line is set on a reset; this must be cleared by writing 0x00 to INTRFLG. To enable an interrupt, the bit that corresponds to the interrupt in INTRFLG must be set. The INTRFLG register shows the status of the interrupts. If any bit is HIGH then an interrupt has occurred since the last time the bit was cleared. Writing a zero to any

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bit location in INTRFLG will clear the corresponding interrupt. If a masked interrupt occurs, the microcontroller can still detect the occurrence because the event is still posted in INTRFLG.

Table 8 Interrupt mask register: 0xF0FB

MNEMONIC R/W

76543210

INTRMSK R/W MASK7 MASK6 MASK5 MASK4 MASK3 MASK2 MASK1 MASK0

Each bit in register 0xF0FB corresponds to the interrupt at the same bit location in register 0xF0FC. To enable an interrupt, the bit in this register must be set HIGH.

Table 9 Interrupt ﬂag register: F0FC; note 1

MNEMONIC R/W

765 43210

INTRFLG R/W CDB2INT FETXINT FERXINT ECC_COR FE_HDR FE2352 STR_LST FRM_STR

Note

1. If any bit is set in this register an interrupt is sent to the microcontroller. Table 10 shows when the interrupts are asserted; assuming the corresponding mask bit is set.

DATA BYTE

Table 10 INTRFLG ﬁeld descriptions

FIELD DESCRIPTION

FRM_STR set one when one complete frame is stored STR_LST set at the start of the last frame FE_2352 set if the front-end data exceeds 2352 bytes FE_HDR front-end interrupt for header (or Q channel) ready ECC_COR ECC interrupt for correction complete RFERXINT front-end interrupt for receive ready FETXINT front-end interrupt for transmit ready CDB2INT CDB2 interrupts: see CSTAT (Table 78) for bit descriptions

8.4 Microcontroller RAM organization

MICFRM# is used to determine the frame address for the microcontroller access through the frame window 0x8000 to 0x8FFF. To obtain the actual byte location within the buffer RAM, the lower 12 bits of the microcontroller address form the relative offset and hence the absolute address is found.

Note that the microcontroller has the option of addressing memory in a linear fashion using the 32 kbytes address

space between 0x000 and 0x7FFF. If this 32 kbytes page is used, the PAGEREG must be programmed with the required page address. PAGEREG is used to select the required page when the microcontroller makes a linear access to the buffer memory using the address space 0x7000 to 0x7FFF. The actual address is the fifteen LSBs from the microcontroller plus 32768 times the value in PAGEREG.

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Table 11 Microcontroller frame number address registers: 0xF0F6 and 0xF0F7; note 1

MNEMONIC R/W

76543210

MICFRM# R/W FRAME7 FRAME6 FRAME5 FRAME4 FRAME3 FRAME2 FRAME1 FRAME0 MICFRM# R/W −−−−−FRAME10 FRAME9 FRAME8

Note

1. Registers 0xF0F6 and 0xF0F7 provide the frame number address for the microcontroller access to memory. The counter associated with these registers is loaded after the most significant byte is written; the least significant byte must be written first to ensure that the counter is loaded correctly. If a DRAM access is in progress that uses the address from the counter, the update will be delayed until the access is complete.

Table 12 Microcontroller address page register: 0xF0FF; note 1

MNEMONIC R/W

76 5 43210

PAGEREG R/W − MA_21 MA_20 MA_19 MA_18 MA_17 MA_16 MA_15

Note

1. Register 0xF0FF is used by the buffer manager for the upper address lines when the microcontroller addresses non-frame memory. These registers overlap frame memory, so register 0xF0FF must be programmed with an address in the top part of the memory if no overlap is required. The microcontroller page address line is selected from this register. The outputs are used directly to control DRAM access cycles, and will affect any current DRAM cycle in progress.

DATA BYTE

It is possible to access three contiguous frames from the microcontroller by reading the three data sector windows, 0x8000 to 0x8FFF, 0x9000 to 0x9FFF and 0xA000 to 0xAFFF. This function is required for the decoding of the sub-code information. If the ‘next’ frame wraps past the last frame pointer (LASTFRM) then the pointers are modified to wrap back to the start pointer onwards (FEFRM#); this section is transparent to the microcontroller.

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handbook, halfpage

0000

SCRATCH PAD RAM

7FFF

8000

DATA SECTOR WINDOW

9000

DATA SECTOR WINDOW

A000

DATA SECTOR WINDOW

AFFF

SAA7390

80C32

(FRAME 0)

(FRAME 1)

(FRAME 2)

F000

FFFF

SAA7390

CONTROL REGISTERS

MGE522

Fig.12 Address map for the microcontroller.

Table 13 SAA7390 address map details for the 80C32

ADDRESS FUNCTION

0000 to 7FFF This 32 kbytes window is used to address and portion the DRAM buffer. It is intended for non-frame

mapped memory to be addressed through this window. The upper page address bits (to address the full range of the DRAM buffer) are set by the linear address page register (PAGEREG).

8000 to 8FFF All accesses to frame memory use this window to read or write to the buffer memory. The actual

address to the DRAM buffer is Micro Frame Number (MICFRM#) times 3 k plus the 12 LSBs from the 80C32.

9000 to 9FFF This frame window is identical to the frame 0 window with the exception that one is added to the

value from the Micro Frame Number (MICFRM#).

A000-AFFF This frame window is identical to the frame 0 window with the exception that two is added to the

value from the Micro Frame Number (MICFRM#). B000-EFFF Not used; output 3-state. F000-FFFF SAA7390 control registers.

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