INTEGRATED CIRCUITS
DATA SHEET
SAA7377
Digital servo processor and Compact Disc decoder (CD7)
Product specifications |
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1998 Jul 06 |
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File under Integrated Circuits, IC01 |
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Philips Semiconductors |
Product specifications |
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Digital servo processor and Compact Disc
SAA7377
decoder (CD7)
CONTENTS
1FEATURES
2GENERAL DESCRIPTION
3QUICK REFERENCE DATA
4ORDERING INFORMATION
5BLOCK DIAGRAM
6PINNING
7FUNCTIONAL DESCRIPTION
7.1Decoder part
7.1.1Principle operational modes of the decoder
7.1.2Crystal frequency selection
7.1.3Standby modes
7.2Crystal oscillator
7.3Data slicer and clock regenerator
7.4Demodulator
7.4.1Frame sync protection
7.4.2EFM demodulation
7.5Subcode data processing
7.5.1Q-channel processing
7.5.2EIAJ 3 and 4-wire subcode (CD graphics) interfaces
7.5.3V4 subcode interface
7.6FIFO and error corrector
7.6.1Flags output (CFLG)
7.6.2C2FAIL
7.7Audio functions
7.7.1De-emphasis and phase linearity
7.7.2Digital oversampling filter
7.7.3Concealment
7.7.4Mute, full scale, attenuation and fade
7.7.5Peak detector
7.8DAC interface
7.9EBU interface
7.9.1Format
7.10KILL circuit
7.11The VIA interface
7.12Spindle motor control
7.12.1Motor output modes
7.12.2Spindle motor operating modes
7.12.3Loop characteristics
7.12.4FIFO overflow
7.13Servo part
7.13.1Diode signal processing
7.13.2Signal conditioning
7.13.3Focus servo system
7.13.4Radial servo system
7.13.5Off-track counting
7.13.6Defect detection
7.13.7Off-track detection
7.13.8high-level features
7.13.9Driver interface
7.13.10Laser interface
7.13.11Radial shock detector
7.14Microcontroller interface
7.14.1Microprocessor interface (4-wire bus mode)
7.14.2Microcontroller interface (I2C-bus mode)
7.14.3Summary of functions controlled by registers 0 to F
7.14.4Summary of servo commands
7.14.5Summary of servo command parameters
8LIMITING VALUES
9OPERATING CHARACTERISTICS
10OPERATING CHARACTERISTICS (SUBCODE INTERFACE TIMING)
11OPERATING CHARACTERISTICS (I2S-BUS TIMING)
12OPERATING CHARACTERISTICS (MICROCONTROLLER INTERFACE TIMING)
13APPLICATION INFORMATION
14PACKAGE OUTLINE
15SOLDERING
15.1Introduction
15.2Reflow soldering
15.3Wave soldering
15.4Repairing soldered joints
16DEFINITIONS
17LIFE SUPPORT APPLICATIONS
18PURCHASE OF PHILIPS I2C COMPONENTS
1998 Jul 06 |
2 |
Philips Semiconductors |
Product specifications |
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Digital servo processor and Compact Disc
SAA7377
decoder (CD7)
1 FEATURES
∙Single-speed mode
∙Full error correction strategy, t = 2 and e = 4
∙Full CD graphics interface
∙All standard decoder functions implemented digitally on chip
∙FIFO overflow concealment for rotational shock resistance
∙Digital audio interface (EBU), audio only
∙2 and 4 times oversampling integrated digital filter, including fs mode
∙Audio data peak level detection
∙Kill interface for DAC deactivation during digital silence
∙All TDA1301 (DSIC2) digital servo functions, plus extra high-level functions
∙Low focus noise
∙Improved playability on ABEX TCD-721R, TCD-725 and TCD-714 discs
∙Automatic closed loop gain control available for focus and radial loops
∙Pulsed sledge support
∙Microcontroller loading LOW
∙High-level servo control option
∙High-level mechanism monitor
∙Communication may be via TDA1301/SAA7345 compatible bus or I2C-bus
∙On-chip clock multiplier allows the use of 8.4672 MHz crystal.
2 GENERAL DESCRIPTION
The SAA7377 is a single chip combining the functions of a CD decoder IC and digital servo IC. The decoder part is based on the SAA7345 (CD6) with an improved error correction strategy. The servo part is based on the TDA1301T (DSIC2) with improvements incorporated, extra features have also been added.
Supply of this Compact Disc IC does not convey an implied license under any patent right to use this IC in any Compact Disc application.
3 QUICK REFERENCE DATA
SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
TYP. |
MAX. |
UNIT |
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VDD |
supply voltage |
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3.4 |
5.0 |
5.5 |
V |
IDD |
supply current |
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49 |
− |
mA |
fxtal |
crystal frequency |
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8 |
8.4672 |
35 |
MHz |
Tamb |
operating ambient temperature |
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−40 |
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+85 |
°C |
Tstg |
storage temperature |
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−55 |
− |
+125 |
°C |
4 ORDERING INFORMATION
TYPE |
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PACKAGE |
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NUMBER |
NAME |
DESCRIPTION |
VERSION |
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SAA7377GP |
QFP64 |
plastic quad flat package; 64 leads (lead length 1.6 mm); |
SOT393-1 |
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body 14 × 14 × 2.7 mm |
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1998 Jul 06 |
3 |
Philips Semiconductors |
Product specifications |
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Digital servo processor and Compact Disc
SAA7377
decoder (CD7)
5 BLOCK DIAGRAM
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VSSA2 |
VDDA1 |
VSSD1 |
VSSD3 |
VDDD1(P) |
VDDD3(C) |
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VRL |
D1 |
D2 |
D3 |
D4 |
IrefT |
VSSA1 |
VSSA3 |
VDDA2 |
VSSD2 |
VSSD4 |
VDDD2(P) |
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6 |
3 |
4 |
5 |
7 |
10 |
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1 |
12 |
16 |
2 |
19 |
32 |
39 |
49 |
56 |
30 |
47 |
59 |
R1 |
8 |
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PRE- |
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CONTROL |
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ADC |
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R2 |
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PROCESSING |
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FUNCTION |
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RA |
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OUTPUT |
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STAGES |
FO |
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VRH |
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Vref |
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SL |
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GENERATOR |
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CONTROL |
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52 |
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PART |
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64 |
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SCL |
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LDON |
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SDA |
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MICROCONTROLLER |
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RAB |
53 |
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INTERFACE |
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SILD |
54 |
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SAA7377 |
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HFIN |
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33 |
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DIGITAL |
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17 |
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PLL |
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MOTOR |
MOTO1 |
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HFREF |
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34 |
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FRONT END |
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CONTROL |
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14 |
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MOTO2 |
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ISLICE |
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Iref |
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20 |
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EFM |
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TEST1 |
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DEMODULATOR |
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ERROR |
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23 |
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TEST2 |
TEST |
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CORRECTOR |
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TEST3 |
29 |
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FLAGS |
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61 |
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CFLG |
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13 |
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SRAM |
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SELPLL |
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CRIN |
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60 |
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C2FAIL |
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CROUT |
22 |
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AUDIO |
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PROCESSOR |
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24 |
TIMING |
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RAM |
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CL16 |
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ADDRESSER |
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CL11 |
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CL4 |
50 |
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EBU |
31 |
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INTERFACE |
DOBM |
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SBSY |
35 |
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SFSY |
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SUBCODE |
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SUB |
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PROCESSOR |
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PEAK |
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RCK |
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DETECT |
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SCLK |
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DECODER |
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46 |
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58 |
MICRO- |
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SERIAL DATA |
WCLK |
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STATUS |
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45 |
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CONTROLLER |
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INTERFACE |
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INTERFACE |
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VERSATILE PINS |
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DATA |
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44 |
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INTERFACE |
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KILL |
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TEST4 |
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RESET |
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62 |
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42 |
41 |
40 |
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MGR291 |
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V1 |
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V2 |
V3 |
V4 |
V5 |
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KILL |
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Fig.1 Block diagram.
1998 Jul 06 |
4 |
Philips Semiconductors |
Product specifications |
|
|
Digital servo processor and Compact Disc
SAA7377
decoder (CD7)
6 PINNING
SYMBOL |
PIN |
DESCRIPTION |
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V |
1(1) |
analog ground 1 |
SSA1 |
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V |
2(1) |
analog supply voltage 1 |
DDA1 |
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D1 |
3 |
unipolar current input (central diode signal input) |
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D2 |
4 |
unipolar current input (central diode signal input) |
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D3 |
5 |
unipolar current input (central diode signal input) |
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VRL |
6 |
reference voltage input for ADC |
D4 |
7 |
unipolar current input (central diode signal input) |
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R1 |
8 |
unipolar current input (satellite diode signal input) |
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R2 |
9 |
unipolar current input (satellite diode signal input) |
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IrefT |
10 |
current reference output for ADC calibration |
VRH |
11 |
reference voltage output from ADC |
V |
12(1) |
analog ground 2 |
SSA2 |
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SELPLL |
13 |
selects whether internal clock multiplier PLL is used |
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ISLICE |
14 |
current feedback output from data slicer |
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HFIN |
15 |
comparator signal input |
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V |
16(1) |
analog ground 3 |
SSA3 |
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HFREF |
17 |
comparator common mode input |
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Iref |
18 |
reference current output pin (nominally 0.5VDD) |
V |
19(1) |
analog supply voltage 2 |
DDA2 |
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TEST1 |
20 |
test control input 1; this pin should be tied LOW |
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CRIN |
21 |
crystal/resonator input |
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CROUT |
22 |
crystal/resonator output |
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TEST2 |
23 |
test control input 2; this pin should be tied LOW |
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CL16 |
24 |
16.9344 MHz system clock output |
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CL11 |
25 |
11.2896 or 5.6448 MHz clock output (3-state) |
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RA |
26 |
radial actuator output |
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FO |
27 |
focus actuator output |
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SL |
28 |
sledge control output |
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TEST3 |
29 |
test control input 3; this pin should be tied LOW |
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V |
30(1) |
digital supply voltage 1 for periphery |
DDD1(P) |
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DOBM |
31 |
bi-phase mark output (externally buffered; 3-state) |
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V |
32(1) |
digital ground 1 |
SSD1 |
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MOTO1 |
33 |
motor output 1; versatile (3-state) |
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MOTO2 |
34 |
motor output 2; versatile (3-state) |
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SBSY |
35 |
subcode block sync output (3-state) |
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SFSY |
36 |
subcode frame sync output (3-state) |
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RCK |
37 |
subcode clock input |
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SUB |
38 |
P-to-W subcode output bits (3-state) |
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V |
39(1) |
digital ground 2 |
SSD2 |
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V5 |
40 |
versatile output pin 5 |
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1998 Jul 06 |
5 |
Philips Semiconductors |
Product specifications |
|
|
Digital servo processor and Compact Disc
SAA7377
decoder (CD7)
|
SYMBOL |
PIN |
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DESCRIPTION |
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V4 |
41 |
versatile output pin 4 |
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V3 |
42 |
versatile output pin 3 (open-drain) |
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KILL |
43 |
kill output (programmable; open-drain) |
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TEST4 |
44 |
test output pin; this pin should be left unconnected |
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DATA |
45 |
serial data output (3-state) |
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WCLK |
46 |
word clock output (3-state) |
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V |
47(1) |
digital supply voltage 2 for periphery |
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DDD2(P) |
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SCLK |
48 |
serial bit clock output (3-state) |
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V |
49(1) |
digital ground 3 |
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SSD3 |
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CL4 |
50 |
4.2336 MHz microcontroller clock output |
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SDA |
51 |
microcontroller interface data I/O line (open-drain output) |
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SCL |
52 |
microcontroller interface clock line input |
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RAB |
53 |
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and load control line input (4-wire bus mode) |
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microcontroller interface R/W |
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SILD |
54 |
microcontroller interface |
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R/W and load control line input (4-wire-bus mode) |
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n.c. |
55 |
not connected |
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VSSD4 |
56(1) |
digital ground 4 |
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57 |
power-on reset input (active LOW) |
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RESET |
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STATUS |
58 |
servo interrupt request line/decoder status register output (open-drain) |
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V |
59(1) |
digital supply voltage 3 for core |
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DDD3(C) |
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C2FAIL |
60 |
indication of correction failure output (open-drain) |
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CFLG |
61 |
correction flag output (open-drain) |
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V1 |
62 |
versatile input pin 1 |
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V2 |
63 |
versatile input pin 2 |
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LDON |
64 |
laser drive on output (open-drain) |
|||||
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Note
1. All supply pins must be connected to the same external power supply voltage.
1998 Jul 06 |
6 |
Philips Semiconductors |
Product specifications |
|
|
Digital servo processor and Compact Disc
SAA7377
decoder (CD7)
VSSA1 1
VDDA1 2 D1 3
D2 4
D3 5
VRL 6
D4 7
R1 8
R2 9
IrefT 10
VRH 11
VSSA2 12 SELPLL 13
ISLICE 14
HFIN 15
VSSA3 16
LDON |
|
V2 |
|
V1 |
|
CFLG |
|
C2FAIL |
|
DDD3(C) |
STATUS |
|
RESET |
|
SSD4 |
n.c. |
|
SILD |
|
RAB |
|
SCL |
|
SDA |
|
CL4 |
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SSD3 |
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V |
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V |
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V |
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64 |
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63 |
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62 |
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61 |
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60 |
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59 |
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58 |
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57 |
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56 |
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55 |
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54 |
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53 |
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52 |
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51 |
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50 |
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49 |
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SAA7377
17 |
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18 |
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19 |
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20 |
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21 |
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22 |
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23 |
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24 |
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25 |
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26 |
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27 |
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28 |
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29 |
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30 |
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31 |
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32 |
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HFREF |
|
ref |
DDA2 |
TEST1 |
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CRIN |
|
CROUT |
|
TEST2 |
|
CL16 |
|
CL11 |
|
RA |
|
FO |
|
SL |
|
TEST3 |
|
DDD1(P) |
DOBM |
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SSD1 |
|||
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I |
V |
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V |
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V |
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48 |
SCLK |
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47 |
VDDD2(P) |
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46 |
WCLK |
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|
45 |
DATA |
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44 |
TEST4 |
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43 |
KILL |
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42 |
V3 |
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41 |
V4 |
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40 |
V5 |
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39 |
VSSD2 |
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38 |
SUB |
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37 |
RCK |
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36 |
SFSY |
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35 |
SBSY |
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34 |
MOTO2 |
|
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33 |
MOTO1 |
|
MGR292 |
Fig.2 Pin configuration.
1998 Jul 06 |
7 |
Philips Semiconductors |
Product specifications |
|
|
Digital servo processor and Compact Disc
SAA7377
decoder (CD7)
7 FUNCTIONAL DESCRIPTION
7.1Decoder part
7.1.1PRINCIPLE OPERATIONAL MODES OF THE DECODER
The decoding part operates at single-speed and supports a full audio specification.
A simplified data flow through the decoder part is illustrated in Fig.6.
7.1.2CRYSTAL FREQUENCY SELECTION
The SAA7377, which has an internal phase-locked loop clock multiplier, can be used with 33.8688, 16.9344 or 8.4672 MHz crystal frequencies by setting register B and SELPLL as shown in Table 1. The internal clock multiplier, controlled by SELPLL, should only be used if a
8.4672 MHz crystal, ceramic resonator or external clock is present. It should be noted that the CL11 output is a 5.6448 MHz clock if a 16.9344 MHz external clock is used.
Table 1 Crystal frequency selection
REGISTER B |
SELPLL |
CRYSTAL FREQUENCY |
|
(MHz) |
|||
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||
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|
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|
00xx |
0 |
33.8688 |
|
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00xx |
1 |
8.4672 |
|
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01xx |
0 |
16.9344 |
|
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|
|
7.1.3STANDBY MODES
The SAA7377 may be placed in two standby modes selected by register B (it should be noted that the device core is still active)
Standby 1: “CD-STOP” mode. Most I/O functions are switched off.
Standby 2: “CD-PAUSE” mode. Audio output features are switched off, but the motor loop, the motor output and the subcode interfaces remain active. This is also called a “Hot Pause”.
In the standby modes the various pins will have the following values;
MOTO1 and MOTO2: put in high-impedance, PWM mode (standby 1 and RESET, operating in standby 2). Put in high-impedance, PDM mode (standby 1 and RESET, operating in standby 2).
SCL, SDA, SILD and RAB: no interaction. Normal operation continues.
SCLK, WCLK, DATA, CL11 and DOBM: 3-state in both standby modes. Normal operation continues after reset.
CRIN, CROUT, CL16 and CL4: no interaction. Normal operation continues.
V1, V2, V3, V4, V5, CFLG and C2FAIL: no interaction. Normal operation continues.
7.2Crystal oscillator
The crystal oscillator is a conventional 2 pin design operating between 8 and 35 MHz. This oscillator is capable of operating with ceramic resonators and also with both fundamental and third overtone crystals. External components should be used to suppress the fundamental output of the third overtone crystals as shown in Figs 3 and 4. Typical oscillation frequencies required are 8.4672, 16.9344 or 33.8688 MHz depending on the internal clock settings used and whether or not the clock multiplier is enabled.
SAA7377 |
|
OSCILLATOR |
|
CROUT |
CRIN |
8.4672 MHz |
|
330 Ω |
|
100 kΩ |
|
22 pF |
22 pF |
MGR293 |
|
Fig.3 8.4672 MHz fundamental configuration.
SAA7377 |
|
|
|
OSCILLATOR |
|
|
|
CROUT |
|
CRIN |
|
33.8688 MHz |
|
||
330 Ω |
|
3.3 μH |
|
100 kΩ |
|||
|
|||
10 pF |
10 pF |
1 nF |
|
MGR294 |
|
|
Fig.4 33.8688 MHz overtone configuration.
1998 Jul 06 |
8 |
Philips Semiconductors |
Product specifications |
|
|
Digital servo processor and Compact Disc
SAA7377
decoder (CD7)
7.3Data slicer and clock regenerator
The SAA7377 has an integrated slice level comparator which can be clocked by the crystal frequency clock, or 8 times the crystal frequency clock (if SELPLL is set HIGH while using an 8.4672 MHz crystal, and register 4 is set to 0xxx). The slice level is controlled by an internal current source applied to an external capacitor under the control of the Digital Phase-Locked Loop (DPLL).
Regeneration of the bit clock is achieved with an internal fully digital PLL. No external components are required and the bit clock is not output. The PLL has two registers
(8 and 9) for selecting bandwidth and equalization.
For certain applications an off-track input is necessary. This is internally connected from the servo part (its polarity can be changed by the foc_parm1 parameter), but may be input via the V1 pin if selected by register C. If this flag is HIGH, the SAA7377 will assume that its servo part is following on the wrong track and will flag all incoming HF data as incorrect.
7.4Demodulator
7.4.1FRAME SYNC PROTECTION
A double timing system is used to protect the demodulator from erroneous sync patterns in the serial data.
The master counter is only reset if:
∙A sync coincidence detected; sync pattern occurs 588 ±1 EFM clocks after the previous sync pattern
∙A new sync pattern is detected within ±6 EFM clocks of its expected position.
The sync coincidence signal is also used to generate the PLL lock signal, which is active HIGH after 1 sync coincidence found, and reset LOW if, during 61 consecutive frames, no sync coincidence is found. The PLL lock signal can be accessed via the SDA or STATUS pins selected by register 2 and 7.
Also incorporated in the demodulator is a Run Length 2 (RL2) correction circuit. Every symbol detected as RL2 will be pushed back to RL3. To do this, the phase error of both edges of the RL2 symbol are compared and the correction is executed at the side with the highest error probability.
7.4.2EFM DEMODULATION
The 14-bit EFM data and subcode words are decoded into 8-bit symbols.
|
|
|
|
|
crystal |
|
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|
clock |
|
|
HF |
2.2 kΩ |
|
HFIN |
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|
input |
2.2 nF |
|
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47 pF |
|
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D |
Q |
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|||
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HFREF |
|
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22 kΩ |
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DPLL |
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Iref |
1/2VDD |
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22 nF |
100 |
μA |
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|||
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VSSA |
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VSS |
|
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100 nF |
ISLICE |
|
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VDD |
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|
MGA368 - 1 |
||
|
VSSA |
|
100 μA |
|
|
Fig.5 Data slicer showing typical application components.
1998 Jul 06 |
9 |
_
06 Jul 1998
1
V4
|
|
0 |
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SBSY |
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|||
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|
CD GRAPHICS |
|
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|
||||
|
0 : reg D = xx01 |
|
INTERFACE |
|
SFSY |
|
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||||||
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SUB |
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V4 SUBCODE |
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MICROCONTROLLER |
|
|
SDA |
||||
INTERFACE |
|
reg F |
|
|
INTERFACE |
|
|||||||
|
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|
SUBCODE |
|
|
PROCESSOR |
EBU |
DOBM |
|
INTERFACE |
|
|
|
reg A
output from |
DIGITAL PLL AND |
|
data slicer |
|
DEMODULATOR |
|
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|
10
|
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1 : reg 3 = xx10 |
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(1fs mode) |
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FIFO |
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0 : reg 3 ¹ xx10 |
|
1 : no pre-emphasis detected |
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||
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OR reg D = 01xx (de-emphasis signal at V5) |
||||
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0 : pre-emphasis detected |
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AND reg D ¹ 01xx |
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1 |
PHASE |
1 |
|
|
SCLK |
|
ERROR |
FADE/MUTE/ |
DIGITAL |
0 |
COMPENSATION |
0 |
1 |
I2S-BUS |
||
WCLK |
|||||||||
CORRECTOR |
INTERPOLATE |
FILTER |
|
0 |
INTERFACE |
||||
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DATA |
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reg 3 |
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reg 3 |
MGD039 |
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KILL |
KILL |
DE-EMPHASIS |
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V3 |
FILTER |
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reg C |
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|
Fig.6 Simplified data flow of decoder functions.
(CD7) decoder |
processor servo Digital |
|
Disc Compact and |
SAA7377
Semiconductors Philips
specifications Product
Philips Semiconductors |
Product specifications |
|
|
Digital servo processor and Compact Disc
SAA7377
decoder (CD7)
7.5Subcode data processing
7.5.1Q-CHANNEL PROCESSING
The 96-bit Q-channel word is accumulated in an internal buffer. The last 16 bits are used internally to perform a Cyclic Redundancy Check (CRC). If the data is good, the SUBQREADY-I signal will go LOW. SUBQREADY-I can be read via the SDA or STATUS pins, selected via register 2. Good Q-channel data may be read from SDA.
7.5.2EIAJ 3 AND 4-WIRE SUBCODE (CD GRAPHICS)
INTERFACES
Data from all the subcode channels (P-to-W) may be read via the subcode interface, which conforms to
EIAJ CP-2401. The interface is enabled and configured as either a 3-wire or 4-wire interface via register F. The subcode interface output formats are illustrated in Fig.7, where the RCK signal is supplied by another device such as a CD graphics decoder.
7.5.3V4 SUBCODE INTERFACE
Data of subcode channels, Q-to-W, may be read via pin V4 if selected via register D. The format is similar to RS232 and is illustrated in Fig.8. The subcode sync word is formed by a pause of 200 μs minimum. Each subcode byte starts with a logic 1 followed by 7 bits (Q-to-W). The gap between bytes is variable between 11.3 μs and 90 μs.
The subcode data is also available in the EBU output (DOBM) in a similar format.
SF0 |
SF1 |
SF2 |
SF3 |
SF97 |
SF0 |
SF1 |
SBSY
SFSY
RCK
|
|
P-W |
P-W |
P-W |
|
|
SUB |
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|
EIAJ 4-wire subcode interface |
|
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|
SF0 |
SF1 |
SF2 |
SF3 |
SF97 |
SF0 |
SF1 |
SFSY |
|
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RCK |
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P-W |
P-W |
P-W |
|
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SUB |
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EIAJ 3-wire subcode interface |
|
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SFSY |
|
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RCK |
|
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P |
Q R |
S T U V |
W |
|
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|
SUB |
|
|
|
|
MBG410 |
Fig.7 EIAJ subcode (CD graphics) interface format.
1998 Jul 06 |
11 |
Philips Semiconductors |
Product specifications |
|
|
Digital servo processor and Compact Disc
SAA7377
decoder (CD7)
|
|
|
200 μs |
|
11.3 |
|
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|
|
11.3 μs min |
|
|||||
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min |
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μs |
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90 μs max |
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W96 |
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1 |
Q |
|
R |
S |
T |
U |
V |
W |
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|
1 |
Q |
MGD038
Fig.8 Subcode format and timing on pin V4.
7.6FIFO and error corrector
The SAA7377 has a ±8 frame FIFO. The error corrector is a t = 2, e = 4 type, with error corrections on both C1
(32 symbol) and C2 (28 symbol) frames. Four symbols are used from each frame as parity symbols. This error corrector can correct up to two errors on the C1 level and up to four errors on the C2 level.
The error corrector also contains a flag processor. Flags are assigned to symbols when the error corrector cannot ascertain if the symbols are definitely good. C1 generates output flags which are read after (de-interleaving) by C2, to help in the generation of C2 output flags.
The C2 output flags are used by the interpolator for concealment of uncorrectable errors. They are also output via the EBU signal (DOBM).
7.6.1FLAGS OUTPUT (CFLG)
The flags output pin CFLG (open-drain) shows the status of the error corrector and interpolator and is updated every frame (7.35 kHz). In the SAA7377 chip a 1-bit flag is present on the CFLG pin as illustrated in Fig.9. This signal shows the status of the error corrector and interpolator.
The first flag bit, F1, is the absolute time sync signal, the FIFO-passed subcode sync and relates the position of the subcode sync to the audio data (DAC output). This flag may also be used in a super FIFO or in the synchronization of different players. The output flags can be made available at bit 4 of the EBU data format (LSB of the 24-bit data word), if selected by register A.
|
|
|
33.9 μs |
11.3 |
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33.9 μs |
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||||
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μs |
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F8 |
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F1 |
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F2 |
F3 |
F4 |
F5 |
F6 |
F7 |
F8 |
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F1 |
MGD037
Fig.9 Flag output timing diagram.
1998 Jul 06 |
12 |
Philips Semiconductors |
Product specifications |
|
|
Digital servo processor and Compact Disc
SAA7377
decoder (CD7)
Table 2 |
Output flags |
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F1 |
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F2 |
F3 |
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F4 |
F5 |
F6 |
F7 |
F8 |
DESCRIPTION |
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0 |
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x |
x |
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x |
x |
x |
x |
x |
no absolute time sync |
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1 |
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x |
x |
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x |
x |
x |
x |
x |
absolute time sync |
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x |
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0 |
0 |
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x |
x |
x |
x |
x |
C1 frame contained no errors |
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x |
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0 |
1 |
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x |
x |
x |
x |
x |
C1 frame contained 1 error |
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x |
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1 |
0 |
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x |
x |
x |
x |
x |
C1 frame contained 2 errors |
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x |
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1 |
1 |
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x |
x |
x |
x |
x |
C1 frame uncorrectable |
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x |
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x |
x |
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0 |
0 |
x |
x |
0 |
C2 frame contained no errors |
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x |
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x |
x |
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0 |
0 |
x |
x |
1 |
C2 frame contained 1 error |
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x |
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x |
x |
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0 |
1 |
x |
x |
0 |
C2 frame contained 2 errors |
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x |
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x |
x |
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0 |
1 |
x |
x |
1 |
C2 frame contained 3 errors |
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x |
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1 |
0 |
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0 |
C2 frame contained 4 errors |
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x |
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1 |
1 |
x |
x |
1 |
C2 frame uncorrectable |
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x |
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x |
x |
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x |
x |
0 |
0 |
x |
no interpolations |
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x |
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x |
x |
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x |
x |
0 |
1 |
x |
at least one 1 sample interpolation |
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x |
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x |
x |
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x |
x |
1 |
0 |
x |
at least one hold and no interpolations |
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x |
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x |
x |
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x |
x |
1 |
1 |
x |
at least one hold and one 1 sample interpolation |
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7.6.2C2FAIL
The C2FAIL pin indicates that invalid data has occurred on the I2S-bus interface. However, due to the structure of the corrector it is impossible to determine which byte has failed. C2FAIL will go LOW for 140 ms when invalid data is detected, this data may then occur 15 ms before or after the pin is activated.
7.7Audio functions
7.7.1DE-EMPHASIS AND PHASE LINEARITY
When pre-emphasis is detected in the Q-channel subcode, the digital filter automatically includes a de-emphasis filter section. When de-emphasis is not required, a phase compensation filter section controls the phase of the digital oversampling filter to £ ±1° within the band 0 to 16 kHz. With de-emphasis the filter is not phase linear.
If the de-emphasis signal is set to be available at V5, selected via register D, then the de-emphasis filter is bypassed.
7.7.2DIGITAL OVERSAMPLING FILTER
The SAA7377 contains a 2 to 4 times oversampling IIR filter. The filter specification of the 4 times oversampling filter is given in Table 3.
These attenuations do not include the sample-and-hold at the external DAC output or the DAC post filter. When using the oversampling filter, the output level is scaled -0.5 dB down, to avoid overflow on full-scale sine wave inputs
(0 to 20 kHz).
Table 3 Filter specification
PASS BAND |
STOP BAND |
ATTENUATION |
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0 to 9 kHz |
- |
£0.001 dB |
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19 to 20 kHz |
- |
£0.03 dB |
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- |
24 kHz |
³25 dB |
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- |
24 to 27 kHz |
³38 dB |
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- |
27 to 35 kHz |
³40 dB |
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- |
35 to 64 kHz |
³50 dB |
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- |
64 to 68 kHz |
³31 dB |
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- |
68 kHz |
³35 dB |
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- |
69 to 88 kHz |
³40 dB |
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1998 Jul 06 |
13 |
Philips Semiconductors |
Product specifications |
|
|
Digital servo processor and Compact Disc
SAA7377
decoder (CD7)
7.7.3CONCEALMENT
A 1-sample linear interpolator becomes active if a single sample is flagged as erroneous but cannot be corrected. The erroneous sample is replaced by a level midway between the preceding and following samples. Left and right channels have independent interpolators. If more than one consecutive non-correctable sample is found, the last good sample is held. A 1-sample linear interpolation is then performed before the next good sample (see Fig.10).
7.7.4MUTE, FULL SCALE, ATTENUATION AND FADE
A digital level controller is present on the SAA7377 which performs the functions of soft mute, full scale, attenuation and fade; these are selected via register 0:
Mute: signal reduced to 0 in a maximum of 128 steps; 3 ms.
Attenuate: signal scaled by −12 dB.
Full scale: ramp signal back to 0 dB level. From mute takes 3 ms.
Fade: activates a 128 stage counter which allows the signal to be scaled up/down by 0.07 dB steps
128 = full scale.
120 = −0.5 dB (i.e. full scale if oversampling filter used).
32 = −12 dB.
0 = mute.
7.7.5PEAK DETECTOR
The peak detector measures the highest audio level (absolute value) on positive peaks for left and right channels. The 8 most significant bits are output in the Q-channel data in place of the CRC bits. Bits 81 to 88 contain the left peak value (bit 88 = MSB) and
bits 89 to 96 contain the right peak value (bit 96 = MSB). The values are reset after reading Q-channel data via SDA.
Interpolation |
Hold |
Interpolation |
OK |
Error |
OK |
Error |
Error |
Error |
OK |
OK |
MGA372
Fig.10 Concealment mechanism.
1998 Jul 06 |
14 |
Philips Semiconductors |
Product specifications |
|
|
Digital servo processor and Compact Disc
SAA7377
decoder (CD7)
7.8DAC interface
The SAA7377 is compatible with a wide range of digital-to-analog converters (DACs). Nine formats are supported and are given in Table 4. Figures 11 and 12 show the Philips I2S-bus and the EIAJ data formats respectively. All formats are MSB first and fs is 44.1 kHz. The polarity of the WCLK and the data can be inverted; selectable by register 7.
Table 4 DAC interface formats
REGISTER 3 |
SAMPLE |
NUMBER OF |
SCLK (MHz) |
FORMAT |
INTERPOLATION |
|
FREQUENCY |
BITS |
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1110 |
fs |
16/18(1) |
2.1168 |
Philips I2S-bus; 16/18 bits(1) |
yes |
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0010 |
fs |
16 |
2.1168 |
EIAJ 16 bits |
yes |
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0110 |
fs |
18 |
2.1168 |
EIAJ 18 bits |
yes |
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0000 |
4fs |
16 |
8.4672 |
EIAJ 16 bits |
yes |
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0100 |
4fs |
18 |
8.4672 |
EIAJ 18 bits |
yes |
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1100 |
4fs |
18 |
8.4672 |
Philips I2S-bus; 18 bits |
yes |
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0011 |
2fs |
16 |
4.2336 |
EIAJ 16 bits |
yes |
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0111 |
2fs |
18 |
4.2336 |
EIAJ 18 bits |
yes |
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1111 |
2fs |
18 |
4.2336 |
Philips I2S-bus; 18 bits |
yes |
Note
1.In this mode the first 16 bits contain data, but if any of the fade, attenuate or de-emphasis filter functions are activated then the first 18 bits contain data.
1998 Jul 06 |
15 |
_
06 Jul 1998
SCLK
DATA |
1 |
0 |
15 |
14 |
1 |
0 |
|
15 |
14 |
LEFT CHANNEL DATA (WCLK NORMAL POLARITY)
WCLK
MGD036
Fig.11 Philips I2S-bus data format (16-bit word length shown).
16
SCLK
DATA |
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0 |
17 |
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0 |
17 |
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LEFT CHANNEL DATA
WCLK
MGD035
Fig.12 EIAJ data format (18-bit word length shown).
(CD7) decoder |
processor servo Digital |
|
Disc Compact and |
SAA7377
Semiconductors Philips
specifications Product
Philips Semiconductors |
Product specifications |
|
|
Digital servo processor and Compact Disc
SAA7377
decoder (CD7)
7.9EBU interface
The bi-phase mark digital output signal at pin DOBM is in accordance with the format defined by the IEC958 specification. The DOBM pin can be held LOW and selected via register A.
7.9.1FORMAT
The digital audio output consists of 32-bit words (‘subframes’) transmitted in bi-phase mark code (two transitions for a logic 1 and one transition for a logic 0). Words are transmitted in blocks of 384. Table 5 gives the formats.
Table 5 Format
FUNCTION |
BITS |
DESCRIPTION |
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Sync |
0 to 3 |
− |
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Auxiliary |
4 to 7 |
not used; normally zero |
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Error flags |
4 |
CFLG error and interpolation flags when selected by register A |
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Audio sample |
8 to 27 |
first 4 bits not used (always zero). 2’s compliment. LSB = bit 12, MSB = bit 27 |
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Validity flag |
28 |
valid = logic 0 |
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User data |
29 |
used for subcode data (Q-to-W) |
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Channel status |
30 |
control bits and category code |
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Parity bit |
31 |
even parity for bits 4 to 30 |
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Table 6 Description of Table 5
FUNCTION |
DESCRIPTION |
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Sync |
The sync word is formed by violation of the bi-phase rule and therefore does not contain any data. |
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Its length is equivalent to 4 data bits. The 3 different sync patterns indicate the following situations: |
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sync B: start of a block (384 words), word contains left sample; sync M: word contains left sample |
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(no block start) and sync W: word contains right sample. |
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Audio sample |
Left and right samples are transmitted alternately. |
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Validity flag |
Audio samples are flagged (bit 28 = 1) if an error has been detected but was uncorrectable. This |
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flag remains the same even if data is taken after concealment. |
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User data |
Subcode bits Q-to-W from the subcode section are transmitted via the user data bit. This data is |
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asynchronous with the block rate. |
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Channel status |
The channel status bit is the same for left and right words. Therefore a block of 384 words contains |
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192 channel status bits. The category code is always CD. The bit assignment is given in Table 7. |
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Table 7 Bit assignment
FUNCTION |
BITS |
DESCRIPTION |
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Control |
0 to 3 |
copy of CRC checked Q-channel control bits 0 to 3; bit 2 is logic 1 when copy |
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permitted; bit 3 is logic 1 when recording has pre-emphasis |
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Reserved mode |
4 to 7 |
always zero |
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Category code |
8 to 15 |
CD: bit 8 = logic 1, all other bits = logic 0 |
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Clock accuracy |
28 to 29 |
set by register A; 10 = level I; 00 = level II; 01 = level III |
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Remaining |
16 to 27 and |
always zero |
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30 to 191 |
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1998 Jul 06 |
17 |