13APPLICATION INFORMATION
14PACKAGE OUTLINE
15SOLDERING
15.1Introduction
15.2Reflow soldering
15.3Wave soldering
15.4Repairing soldered joints
16DEFINITIONS
17LIFE SUPPORT APPLICATIONS
18PURCHASE OF PHILIPS I2C COMPONENTS
1995 Dec 062
Philips SemiconductorsPreliminary specification
Single-chip digital servo processor and
Compact Disc decoder (CD7)
1FEATURES
• CD ROM mode
• Single and double-speed modes
• Lock-to-disc mode
• Full error correction strategy, t = 2 and e = 4
• Full CD graphics interface
• All standard decoder functions implemented digitally on
chip
• FIFO overflow concealment for rotational shock
resistance
• Digital audio interface (EBU), audio and data
• 2 and 4 times oversampling integrated digital filter,
including f
• Audio data peak level detection
• Kill interface for DAC deactivation during digital silence
• All TDA1301 (DSIC2) digital servo functions, plus extra
high-level functions
• Low focus noise
• Improved playability on ABEX TCD-721R, TCD-725 and
TCD-714 discs
mode
s
SAA7372
• Automatic closed loop gain control available for focus
and radial loops
• Pulsed sledge support
• Microcontroller loading LOW
• High-level servo control option
• High-level mechanism monitor
• Communication may be via TDA1301/SAA7345
compatible bus or I
• On-chip clock multiplier allows the use of 8.4672 MHz
crystal.
2GENERAL DESCRIPTION
The SAA7372 is a single chip combining the functions of a
CD decoder IC and digital servo IC. The decoder part is
based on the SAA7345 (CD6) with an improved error
correction strategy. The servo part is based on the
TDA1301T (DSIC2) with improvements incorporated,
extra features have also been added.
Supply of this Compact Disc IC does not convey an implied
license under any patent right to use this IC in any
Compact Disc application.
Single-chip digital servo processor and
Compact Disc decoder (CD7)
5BLOCK DIAGRAM
handbook, full pagewidth
SELPLL
CROUT
V
RH
SCL
SDA
RAB
SILD
HFIN
HFREF
ISLICE
I
TEST1
TEST2
TEST3
CRIN
CL16
CL11
CL4
SBSY
SFSY
SUB
RCK
R1
R2
ref
8
9
11
52
51
53
54
15
17
14
18
20
23
29
13
21
22
24
25
50
35
36
38
37
V
D1 D2 D3 D4
RL
6
V
ref
GENERATOR
MICROCONTROLLER
FRONT END
TEST
TIMING
V
I
SSA1VSSA3VDDA2VSSD2VSSD4VDDD2(P)
refT
345710112 16 219 32 39 49 56 3047 59
ADC
INTERFACE
DIGITAL
PLL
EFM
DEMODULATOR
SRAM
RAM
ADDRESSER
SUBCODE
PROCESSOR
V
SSA2VDDA1VSSD1VSSD3VDDD1(P)VDDD3(C)
PRE-
PROCESSING
FUNCTION
CONTROL
PART
CONTROL
OUTPUT
STAGES
SAA7372
MOTOR
CONTROL
ERROR
CORRECTOR
FLAGS
AUDIO
PROCESSOR
EBU
INTERFACE
PEAK
DETECT
SAA7372
26
RA
27
FO
28
SL
64
LDON
33
MOTO1
34
MOTO2
61
CFLG
60
C2FAIL
31
DOBM
STATUS
RESET
1995 Dec 064
58
57
DECODER
MICRO-
CONTROLLER
INTERFACE
VERSATILE PINS
INTERFACE
62 63 42 41 4043
V1 V2 V3 V4 V5KILL
Fig.1 Block diagram.
KILL
SERIAL DATA
INTERFACE
MGC973
48
SCLK
46
WCLK
45
DATA
44
EF
Philips SemiconductorsPreliminary specification
Single-chip digital servo processor and
Compact Disc decoder (CD7)
6PINNING
SYMBOLPINDESCRIPTION
(1)
V
V
SSA1
DDA1
1
(1)
2
D13unipolar current input (central diode signal input)
D24unipolar current input (central diode signal input)
D35unipolar current input (central diode signal input)
V
RL
6reference voltage input for ADC
D47unipolar current input (central diode signal input)
R18unipolar current input (satellite diode signal input)
R29unipolar current input (satellite diode signal input)
I
V
V
refT
RH
SSA2
10current reference output for ADC calibration
11reference voltage output from ADC
(1)
12
SELPLL13selects whether internal clock multiplier PLL is used
ISLICE14current feedback output from data slicer
HFIN15comparator signal input
(1)
V
SSA3
16
HFREF17comparator common mode input
I
ref
V
DDA2
18reference current output pin (nominally 0.5VDD)
(1)
19
TEST120test control input 1; this pin should be tied LOW
CRIN21crystal/resonator input
CROUT22crystal/resonator output
TEST223test control input 2; this pin should be tied LOW
CL162416.9344 MHz system clock output
CL112511.2896 or 5.6448 MHz clock output (3-state)
RA26radial actuator output
FO27focus actuator output
SL28sledge control output
TEST329test control input 3; this pin should be tied LOW
(1)
V
DDD1(P)
30
DOBM31bi-phase mark output (externally buffered; 3-state)
V
V441versatile output pin 4
V342versatile output pin 3 (open-drain)
KILL43kill output (programmable; open-drain)
EF44C2 error flag; output only defined in CD ROM modes and 1f
DATA45serial data output (3-state)
WCLK46word clock output (3-state)
V
DDD2(P)
47
digital supply voltage 2 for periphery
(1)
SCLK48serial bit clock output (3-state)
V
SSD3
49
digital ground 3
(1)
CL4504.2336 MHz microcontroller clock output
SDA51microcontroller interface data I/O line (open-drain output)
SCL52microcontroller interface clock line input
RAB53microcontroller interface R/
SILD54microcontroller interface
W and load control line input (4-wire bus mode)
R/W and load control line input (4-wire-bus mode)
n.c.55not connected
V
SSD4
56
digital ground 4
(1)
RESET57power-on reset input (active LOW)
STATUS58servo interrupt request line/decoder status register output (open-drain)
V
1. All supply pins must be connected to the same external power supply voltage.
1995 Dec 066
Philips SemiconductorsPreliminary specification
Single-chip digital servo processor and
Compact Disc decoder (CD7)
handbook, full pagewidth
C2FAIL
60
21
CRIN
DDD3(C)
V
STATUS
59
58
22
23
TEST2
CROUT
V
SSA1
V
DDA1
D1
D2
D3
V
RL
D4
R1
R2
I
refT
V
RH
V
SSA2
SELPLL
ISLICE
HFIN
V
SSA3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
LDONV2V1
64
63
62
17
18
19
ref
I
HFREF
V
DDA2
CFLG
61
20
TEST1
RESET
57
SAA7372
24
CL16
SSD4
V
56
25
CL11
n.c.
55
26
RA
SILD
54
27
FO
RAB
53
28
SL
SCL
52
29
TEST3
SDA
51
30
DDD1(P)
V
CL4
50
31
DOBM
SSD3
V
49
32
SSD1
V
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
MGC974
SAA7372
SCLK
V
DDD2(P)
WCLK
DATA
EF
KILL
V3
V4
V5
V
SSD2
SUB
RCK
SFSY
SBSY
MOTO2
MOTO1
1995 Dec 067
Fig.2 Pin configuration.
Philips SemiconductorsPreliminary specification
Single-chip digital servo processor and
Compact Disc decoder (CD7)
7FUNCTIONAL DESCRIPTION
7.1Decoder part
7.1.1P
The decoding part can operate at different disc speeds,
single-speed (n = 1) and double-speed (n = 2). The factor
‘n’ is called the overspeed factor.
A simplified data flow through the decoder part is
illustrated in Fig.6.
7.1.2D
The SAA7372 is a multi-speed decoding device, with an
internal phase-locked loop (PLL) clock multiplier.
Depending on the crystal frequency used and the internal
clock settings (selectable via register B), two playback
speeds shown in Table 1 are possible, where ‘n’ is the
overspeed factor.
An internal clock multiplier is present, controlled by
SELPLL, and should only be used if an 8.4672 MHz
crystal, ceramic resonator or external clock is present.
7.1.3L
For high speed CD-ROM applications, the SAA7372 has a
special mode, the lock-to-disc mode. This allows Constant
Angular Velocity (CAV) disc playback with varying input
data rates from the inside-to-outside of the disc. In the
lock-to-disc mode, the FIFO is blocked and the decoder
will adjust its output data rate to the disc speed. Hence, the
frequency of the I2S-bus clocks (WCLK and SCLK) are
dependent on the disc speed. In the lock-to-disc mode
RINCIPLE OPERATIONAL MODES OF THE DECODER
ECODING SPEED AND CRYSTAL FREQUENCY
OCK-TO-DISC MODE
SAA7372
there is a limit on the maximum variation in disc speed that
the SAA7372 will follow. Disc speeds must always be
within 25 to 100% range of their nominal value. The
lock-to-disc mode is enabled/disabled by register E.
7.1.4S
The SAA7372 may be placed in two standby modes
selected by register B (it should be noted that the device
core is still active)
Standby 1: “CD-STOP” mode. Most I/O functions are
switched off.
Standby 2: “CD-PAUSE” mode. Audio output features
are switched off, but the motor loop, the motor output
and the subcode interfaces remain active. This is also
called a “Hot Pause”.
In the standby modes the various pins will have the
following values;
MOTO1 and MOTO2: put in high-impedance, PWM
mode (standby 1 and reset, operating in standby 2). Put
in high-impedance, PDM mode (standby 1 and reset,
operating in standby 2).
SCL, SDA, SILD and RAB: no interaction. Normal
operation continues.
SCLK, WCLK, DATA, EF, CL11 and DOBM: 3-state in
both standby modes. Normal operation continues after
reset.
CRIN, CROUT, CL16 and CL4: no interaction. Normal
operation continues.
V1, V2, V3, V4, V5, CFLG and C2FAIL: no interaction.
Normal operation continues.
1. The CL11 output is always a 5.6448 MHz clock if a 16.9344 MHz external clock is used and SELPLL = 0.
2. Data capture performance is not optimized for these options.
1995 Dec 068
CRYSTAL FREQUENCY (MHz)
33.868816.93448.4672
(2)
−5.6448
CL11 FREQUENCY
(MHz)
(1)
Philips SemiconductorsPreliminary specification
Single-chip digital servo processor and
Compact Disc decoder (CD7)
7.2Crystal oscillator
The crystal oscillator is a conventional 2 pin design
operating between 8 and 35 MHz. This oscillator is
capable of operating with ceramic resonators also with
both fundamental and third overtone crystals. External
components should be used to suppress the fundamental
output of the third overtone crystals as shown in Figs 3
and 4. Typical oscillation frequencies required are 8.4672,
16.9344 or 33.8688 MHz depending on the internal clock
settings used and whether or not the clock multiplier is
enabled.
SAA7372
OSCILLATOR
8.4672 MHz
CRINCROUT
SAA7372
7.3Data slicer and clock regenerator
The SAA7372 has an integrated slice level comparator
which can be clocked by the crystal frequency clock, or
8 times the crystal frequency clock (if SELPLL is set HIGH
while using an 8.4672 MHz crystal, and register 4 is set
to 0xxx). The slice level is controlled by an internal current
source applied to an external capacitor under the control
of the Digital Phase-Locked Loop (DPLL).
Regeneration of the bit clock is achieved with an internal
fully digital PLL. No external components are required and
the bit clock is not output. The PLL has two registers
(8 and 9) for selecting bandwidth and equalization.
For certain applications an off-track input is necessary.
This is internally connected from the servo part (its polarity
can be changed by the foc_parm1 parameter), but may be
input via the V1 pin if selected by register C. If this flag is
HIGH, the SAA7372 will assume that its servo part is
following on the wrong track and will flag all incoming HF
data as incorrect.
330 Ω
100 kΩ
22 pF22 pF
MGC975
Fig.3 8.4672 MHz fundamental configuration.
SAA7372
OSCILLATOR
CROUT
MGC983
33.8688 MHz
330 Ω
100 kΩ
CRIN
3.3 µH
1 nF10 pF10 pF
Fig.4 33.8688 MHz overtone configuration.
1995 Dec 069
Philips SemiconductorsPreliminary specification
Single-chip digital servo processor and
Compact Disc decoder (CD7)
HF
input
2.2 nF
2.2 kΩ
22 kΩ
100 nF
V
47 pF
22 nF
SSA
V
SSA
HFIN
HFREF
I
ref
ISLICE
1/2V
DD
100 µA
100 µA
crystal
clock
DQ
V
SS
V
DD
SAA7372
DPLL
MGA368 - 1
Fig.5 Data slicer showing typical application components (for n = 1).
7.4Demodulator
7.4.1F
RAME SYNC PROTECTION
A double timing system is used to protect the demodulator
from erroneous sync patterns in the serial data. The
master counter is only reset if:
• A sync coincidence detected; sync pattern occurs
588 ±1 EFM clocks after the previous sync pattern
• A new sync pattern is detected within ±6 EFM clocks of
its expected position.
The sync coincidence signal is also used to generate the
PLL lock signal, which is active HIGH after 1 sync
coincidence found, and reset LOW if during 61
consecutive frames no sync coincidence is found.
The PLL lock signal can be accessed via the SDA or
STATUS pins selected by register 2 and 7.
Also incorporated in the demodulator is a Run Length 2
(RL2) correction circuit. Every symbol detected as RL2 will
be pushed back to RL3. To do this, the phase error of both
edges of the RL2 symbol are compared and the correction
is executed at the side with the highest error probability.
7.4.2EFM
DEMODULATION
The 14-bit EFM data and subcode words are decoded into
8-bit symbols.
1995 Dec 0610
Philips SemiconductorsPreliminary specification
Single-chip digital servo processor and
Compact Disc decoder (CD7)
DOBM
SDA
EBU
reg A
INTERFACE
SCLK
WCLK
S-BUS
2
I
1
1
0
1 : no pre-emphasis detected
OR reg D = 01xx (de-emphasis signal at V5)
0 : pre-emphasis detected
AND reg D ≠ 01xx
1
0
DATA
EF
INTERFACE
0
reg 3
(CD-ROM modes)
1 : reg 3 ≠ 101x
0 : reg 3 = 101x
SAA7372
MBG418
handbook, full pagewidth
V4
1
SBSY
CD GRAPHICS
0
MICROCONTROLLER
SFSY
SUB
INTERFACE
0 : reg D = xx01
V4 SUBCODE
INTERFACE
reg F
INTERFACE
SUBCODE
PROCESSOR
1
0 : reg A = xx1x
1 : reg A = xx0x
DEMODULATOR
DIGITAL PLL AND
mode)
s
(1f
0 : reg 3 ≠ xx10
1 : reg 3 = xx10
0
FIFO
PHASE
COMPENSATION
1
0
FILTER
DIGITAL
FADE/MUTE/
INTERPOLATE
ERROR
CORRECTOR
DE-EMPHASIS
KILL
reg 3
KILL
FILTER
V3
reg C
Fig.6 Simplified data flow of decoder functions.
1995 Dec 0611
data slicer
output from
Philips SemiconductorsPreliminary specification
Single-chip digital servo processor and
Compact Disc decoder (CD7)
7.5Subcode data processing
7.5.1Q-
The 96-bit Q-channel word is accumulated in an internal
buffer. The last 16 bits are used internally to perform a
Cyclic Redundancy Check (CRC). If the data is good, the
SUBQREADY-I signal will go LOW. SUBQREADY-I can
be read via the SDA or STATUS pins, selected via
register 2. Good Q-channel data may be read from SDA.
7.5.2EIAJ 3
Data from all the subcode channels (P-to-W) may be read
via the subcode interface, which conforms to
EIAJ CP-2401. The interface is enabled and configured as
either a 3-wire or 4-wire interface via register F. The
subcode interface output formats are illustrated in Fig.7,
where the RCK signal is supplied by another device such
as a CD graphics decoder.
CHANNEL PROCESSING
AND 4-WIRE SUBCODE (CD GRAPHICS)
INTERFACES
SAA7372
7.5.3V4
Data of subcode channels, Q-to-W, may be read via pin V4
if selected via register D. The format is similar to RS232
and is illustrated in Fig.8. The subcode sync word is
formed by a pause of (200/n) µs minimum. Each subcode
byte starts with a logic 1 followed by 7 bits (Q-to-W). The
gap between bytes is variable between (11.3/n) µs and
(90/n) µs.
The subcode data is also available in the EBU output
(DOBM) in a similar format.
Single-chip digital servo processor and
Compact Disc decoder (CD7)
200/n µs
min
W961QRSTUVW1Q
n =disc speed
7.6FIFO and error corrector
The SAA7372 has a ±8 frame FIFO. The error corrector is
a t = 2, e = 4 type, with error corrections on both C1
(32 symbol) and C2 (28 symbol) frames. Four symbols are
used from each frame as parity symbols. This error
corrector can correct up to two errors on the C1 level and
up to four errors on the C2 level.
The error corrector also contains a flag processor. Flags
are assigned to symbols when the error corrector cannot
ascertain if the symbols are definitely good. C1 generates
output flags which are read after (de-interleaving) by C2,
to help in the generation of C2 output flags.
The C2 output flags are used by the interpolator for
concealment of uncorrectable errors. They are also output
via the EBU signal (DOBM) and the EF output with I
for CD ROM applications.
11.3/n
µs
Fig.8 Subcode format and timing on pin V4.
2
S-bus
SAA7372
11.3/n µs min
90/n µs max
MBG401
7.6.1F
The flags output pin CFLG (open-drain) shows the status
of the error corrector and interpolator and is updated every
frame (7.35 × n kHz). In the SAA7372 chip a 1-bit flag is
present on the CFLG pin as illustrated in Fig.9. This signal
shows the status of the error corrector and interpolator.
The first flag bit, F1, is the absolute time sync signal, the
FIFO-passed subcode sync and relates the position of the
subcode sync to the audio data (DAC output). This flag
may also be used in a super FIFO or in the synchronization
of different players. The output flags can be made
available at bit 4 of the EBU data format (LSB of the 24-bit
data word), if selected by register A.
LAGS OUTPUT (CFLG)
handbook, full pagewidth
n = disc speed.
1995 Dec 0613
33.9/n µs
11.3/n
µs
F1F2F3F4F5F6F7F8F1F8
Fig.9 Flag output timing diagram.
33.9/n µs
MBG425
Philips SemiconductorsPreliminary specification
Single-chip digital servo processor and
Compact Disc decoder (CD7)
Table 2 Output flags
F1F2F3F4F5F6F7F8DESCRIPTION
0xxxxxxxno absolute time sync
1xxxxxxxabsolute time sync
x00xxxxxC1 frame contained no errors
x01xxxxxC1 frame contained 1 error
x10xxxxxC1 frame contained 2 errors
x11xxxxxC1 frame uncorrectable
xxx00xx0C2 frame contained no errors
xxx00xx1C2 frame contained 1 error
xxx01xx0C2 frame contained 2 errors
xxx01xx1C2 frame contained 3 errors
xxx10xx0C2 frame contained 4 errors
xxx11xx1C2 frame uncorrectable
xxxxx00xno interpolations
xxxxx01xat least one 1 sample interpolation
xxxxx10xat least one hold and no interpolations
xxxxx11xat least one hold and one 1 sample interpolation
SAA7372
7.6.2C2FAIL
The C2FAIL pin indicates that invalid data has occurred on
the I2S-bus interface. However, due to the structure of the
corrector it is impossible to determine which byte has
failed. C2FAIL will go LOW for (140/n) µs when invalid
data is detected, this data may then occur (15/n) ms before
or after the pin is activated.
7.7Audio functions
7.7.1D
When pre-emphasis is detected in the Q-channel
subcode, the digital filter automatically includes a
de-emphasis filter section. When de-emphasis is not
required, a phase compensation filter section controls the
phase of the digital oversampling filter to ≤±1° within the
band 0 to 16 kHz. With de-emphasis the filter is not phase
linear.
If the de-emphasis signal is set to be available at V5,
selected via register D, then the de-emphasis filter is
bypassed.
7.7.2D
E-EMPHASIS AND PHASE LINEARITY
IGITAL OVERSAMPLING FILTER
These attenuations do not include the sample-and-hold at
the external DAC output or the DAC post filter. When using
the oversampling filter, the output level is scaled −0.5 dB
down, to avoid overflow on full-scale sine wave inputs
(0 to 20 kHz).
Table 3 Filter specification
PASS BANDSTOP BANDATTENUATION
0to9kHz−≤0.001 dB
19 to 20 kHz−≤0.03 dB
−24 kHz≥25 dB
−24 to 27 kHz≥38 dB
−27 to 35 kHz≥40 dB
−35 to 64 kHz≥50 dB
−64 to 68 kHz≥31 dB
−68 kHz≥35 dB
−69 to 88 kHz≥40 dB
The SAA7372 contains a 2 to 4 times oversampling IIR
filter. The filter specification of the 4 times oversampling
filter is given in Table 3.
1995 Dec 0614
Philips SemiconductorsPreliminary specification
Single-chip digital servo processor and
Compact Disc decoder (CD7)
7.7.3CONCEALMENT
A 1 sample linear interpolator becomes active if a single
sample is flagged as erroneous but cannot be corrected.
The erroneous sample is replaced by a level midway
between the preceding and following samples. Left and
right channels have independent interpolators. If more
than one consecutive non-correctable sample is found, the
last good sample is held. A 1 sample linear interpolation is
then performed before the next good sample (see Fig.10).
In CD ROM modes (i.e. the DAC interface is selected to be
in a CD ROM format) concealment is not executed.
7.7.4M
A digital level controller is present on the SAA7372 which
performs the functions of soft mute, full scale, attenuation
and fade; these are selected via register 0:
Mute: signal reduced to 0 in a maximum of 128 steps;
(3/n) ms.
Attenuate: signal scaled by −12 dB.
Full scale: ramp signal back to 0 dB level. From mute
takes (3/n) ms.
UTE, FULL SCALE, ATTENUATION AND FADE
SAA7372
Fade: activates a 128 stage counter which allows the
signal to be scaled up/down by 0.07 dB steps
128 = full scale.
120 = −0.5 dB (i.e. full scale if oversampling filter
used).
32 = −12 dB.
0 = mute.
7.7.5P
The peak detector measures the highest audio level
(absolute value) on positive peaks for left and right
channels. The 8 most significant bits are output in the
Q-channel data in place of the CRC bits. Bits 81 to 88
contain the left peak value (bit 88 = MSB) and
bits 89 to 96 contain the right peak value (bit 96 = MSB).
The values are reset after reading Q-channel data via
SDA.
EAK DETECTOR
InterpolationHoldInterpolation
OKErrorOKErrorErrorErrorOKOK
Fig.10 Concealment mechanism.
1995 Dec 0615
MGA372
Loading...
+ 34 hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.