Philips SAA7370A Datasheet

INTEGRATED CIRCUITS

DATA SH EET

SAA7370A

Digital servo processor and Compact Disc decoder (CD7)

Preliminary speciﬁcation File under Integrated Circuits, IC01

1995 Nov 29

Philips Semiconductors Preliminary speciﬁcation

Digital servo processor and Compact Disc decoder (CD7)

CONTENTS

1 FEATURES 2 GENERAL DESCRIPTION 3 QUICK REFERENCE DATA 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING 7 FUNCTIONAL DESCRIPTION

7.1 Decoder part

7.1.1 Principle operational modes of the decoder

7.1.2 Decoding speed and crystal frequency

7.1.3 Lock-to-disc mode

7.1.4 Standby modes

7.2 Crystal oscillator

7.3 Data slicer and clock regenerator

7.4 Demodulator

7.4.1 Frame sync protection

7.4.2 EFM demodulation

7.5 Subcode data processing

7.5.1 Q-channel processing

7.5.2 EIAJ 3 and 4-wire subcode (CD graphics) interface

7.5.3 V4 subcode interface

7.6 FIFO error corrector

7.6.1 Flags output (CFLG)

7.6.2 C2FAIL

7.7 Audio functions

7.7.1 De-emphasis and phase linearity

7.7.2 Digital oversampling filter

7.7.3 Concealment

7.7.4 Mute, full-speed, attenuation and fade

7.7.5 Peak detector

7.8 DAC interface

7.9 EBU interface

7.9.1 Format

7.10 KILL circuit

7.11 Audio features off

7.12 The VIA interface

7.13 Spindle motor control

7.13.1 Motor output modes

7.13.3 Loop characteristics

7.13.4 FIFO overflow

SAA7370A

7.14 Servo part

7.14.1 Diode signal processing

7.14.2 Signal conditioning

7.14.3 Focus servo system

7.14.4 Radial servo system

7.14.5 Off-track counting

7.14.6 Defect detection

7.14.7 Off-track detection

7.14.8 High level features

7.14.9 Driver interface

7.15 Microcontroller interface

7.15.1 Microprocessor interface (4-wire bus mode)

7.15.2 Microcontroller interface (I2C-bus mode)

7.15.3 Summary of functions controlled by registers 0 to F

7.15.4 Summary of servo commands

7.15.5 Summary of servo command parameters

8 LIMITING VALUES 9 CHARACTERISTICS 10 OPERATING CHARACTERISTICS

(SUBCODE INTERFACE TIMING)

11 OPERATING CHARACTERISTICS

(I2S-BUS TIMING)

12 OPERATING CHARACTERISTICS

(MICROCONTROLLER INTERFACE TIMING)

13 APPLICATION INFORMATION 14 PACKAGE OUTLINE 15 SOLDERING

15.1 Introduction

15.2 Reflow soldering

15.3 Wave soldering

15.4 Repairing soldered joints

16 DEFINITIONS 17 LIFE SUPPORT APPLICATIONS 18 PURCHASE OF PHILIPS I2C COMPONENTS

1995 Nov 29 2

Philips Semiconductors Preliminary speciﬁcation

Digital servo processor and Compact Disc decoder (CD7)

1 FEATURES

• CD-ROM mode

• Up to 8 times-speed mode

• Lock-to-disc mode

• Full error correction strategy, t = 2 and e = 4

• Full CD graphics interface

• All standard decoder functions implemented digitally on

chip

• FIFO overflow concealment for rotational shock resistance

• Digital audio interface (EBU), audio and data

• 2 and 4 times oversampling integrated digital filter,

including fs mode

• Audio data peak level detection

• Kill interface for DAC deactivation during digital silence

• All TDA1301 (DSIC2) digital servo functions, plus extra

high level functions

• Low focus noise

• Improved playability on ABEX TCD-721R, TCD-725 and

TCD-714 discs

• Automatic closed-loop gain control available for focus and radial loops

• Pulsed sledge support

SAA7370A

• Up to 80 kHz (8.4672 MHz crystal) or 16 MHz (16.9344 MHz crystal) jump performance

• Electronic damping of fast radial actuator during long jump

• Microcontroller loading LOW

• High level servo control option

• High level mechanism monitor

• Communication may be via TDA1301/SAA7345

compatible bus or I

• On-chip clock multiplier allows the use of 8.4672 MHz crystal for up to 4 times speed mode or 16.9344 MHz crystal for up to 8 times-speed mode.

2 GENERAL DESCRIPTION

The SAA7370A (CD7) is a single chip combining the functions of a CD decoder IC and digital servo IC. The decoder part is based on the SAA7345 (CD6) with an improved error correction strategy. The servo part is based on the TDA1301T (DSIC2) with improvements incorporated, extra features have also been added.

Supply of this Compact Disc IC does not convey an implied license under any patent right to use this IC in any Compact Disc application.

C-bus

3 QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V I f T T

DD DD xtal

amb

stg

supply voltage 4.75 5.0 5.25 V supply current n = 1 mode − 49 − mA crystal frequency 8 8.4672 35 MHz operating ambient temperature 0 − +70 °C storage temperature −55 − +125 °C

4 ORDERING INFORMATION

PACKAGE

TYPE NUMBER

NAME DESCRIPTION VERSION

SAA7370A QFP64 plastic quad ﬂat package; 64 leads (lead length 1.6 mm);

SOT393-1

body 14 × 14 × 2.7 mm

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Philips Semiconductors Preliminary speciﬁcation

Digital servo processor and Compact Disc decoder (CD7)

5 BLOCK DIAGRAM

handbook, full pagewidth

SELPLL

CROUT

SCL SDA RAB SILD

HFIN

HFREF

ISLICE

TEST1 TEST2 TEST3

CRIN

CL16 CL11

CL4

SBSY SFSY

SUB RCK

D1 D2 D3 D4

3 4 5 7 10 1 12 16 2 19 32 39 49 56 30 47 59

GENERATOR

52 51 53 54

15 17

FRONT END

14 18

ref

20 23

TEST

13 21 22

TIMING

24 25 50

35 36 38 37

ADC

ref

MICRO CONTROLLER

INTERFACE

DEMODULATOR

ADDRESSER

SUBCODE

PROCESSOR

SSA2VDDA1VSSD1VSSD3VDDD1(P)VDDD3(C)

SSA1VSSA3VDDA2VSSD2VSSD4VDDD2(P)

refT

PROCESSING

DIGITAL

PLL

EFM

SRAM

RAM

PRE-

CONTROL

FUNCTION

CONTROL

PART

SAA7370A

PEAK

DETECT

AUDIO

PROCESSOR

OUTPUT STAGES

MOTOR

CONTROL

ERROR

CORRECTOR

FLAGS

EBU

INTERFACE

SAA7370A

LDON

MOTO1

MOTO2

CFLG

C2 FAIL

DOBM

DECODER

STATUS

RESET

MICRO-

CONTROLLER

INTERFACE

VERSATILE PINS

INTERFACE

62 63 42 41 40 43

V1 V2 V3 V4 V5 KILL

Fig.1 Block diagram.

1995 Nov 29 4

KILL

SERIAL DATA

INTERFACE

MBG766

SCLK

WCLK

DATA

Philips Semiconductors Preliminary speciﬁcation

Digital servo processor and Compact Disc decoder (CD7)

6 PINNING

SYMBOL PIN DESCRIPTION

(1)

V V

SSA1 DDA1

(1)

2 D1 3 unipolar current input (central diode signal input) D2 4 unipolar current input (central diode signal input) D3 5 unipolar current input (central diode signal input) V

6 reference voltage input for ADC D4 7 unipolar current input (central diode signal input) R1 8 unipolar current input (satellite diode signal input) R2 9 unipolar current input (satellite diode signal input) I V V

refT

RH SSA2

10 current reference output for ADC calibration 11 reference voltage output from ADC

(1)

12 SELPLL 13 selects whether internal clock multiplier PLL is used ISLICE 14 current feedback output from data slicer HFIN 15 comparator signal input

(1)

SSA3

16 HFREF 17 comparator common mode input I

ref

DDA2

18 reference current output pin (nominally 0.5VDD)

(1)

19 TEST1 20 test control input 1; this pin should be tied LOW CRIN 21 crystal/resonator input CROUT 22 crystal/resonator output TEST2 23 test control input 2; this pin should be tied LOW CL16 24 16.9344 MHz (or 33.8688 MHz) system clock output CL11 25 11.2896 or 5.6448 MHz (or 22.5792 MHz) clock output (3-state) RA 26 radial actuator output FO 27 focus actuator output SL 28 sledge control output TEST3 29 test control input 3; this pin should be tied LOW V

DDD1(P)

(1)

DOBM 31 bi-phase mark output (externally buffered; 3-state) V

SSD1

(1)

MOTO1 33 motor output 1; versatile (3-state) MOTO2 34 motor output 2; versatile (3-state) SBSY 35 subcode block sync output (3-state) SFSY 36 subcode frame sync output (3-state) RCK 37 subcode clock input SUB 38 P-to-W subcode bits output (3-state) V

SSD2

(1)

V5 40 versatile output pin 5

analog ground 1 analog supply voltage 1

analog ground 2

analog ground 3

analog supply voltage 2

digital supply voltage 1 for periphery

digital ground 1

digital ground 2

SAA7370A

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Philips Semiconductors Preliminary speciﬁcation

Digital servo processor and Compact Disc

SAA7370A

decoder (CD7)

SYMBOL PIN DESCRIPTION

V4 41 versatile output pin 4 V3 42 versatile output pin 3 (open-drain) KILL 43 kill output (programmable; open-drain) EF 44 C2 error ﬂag; output only deﬁned in CD ROM modes (3-state) DATA 45 serial data output (3-state) WCLK 46 word clock output (3-state) V

DDD2(P)

SCLK 48 serial bit clock output (3-state) V

SSD3

CL4 50 4.2336 MHz (or 8.4672 MHz) microcontroller clock output SDA 51 microcontroller interface data I/O line (open-drain output) SCL 52 microcontroller interface clock line input RAB 53 microcontroller interface R/ SILD 54 microcontroller interface n.c. 55 not connected V

SSD4

RESET 57 power-on reset input (active LOW) STATUS 58 servo interrupt request line/decoder status register output (open-drain) V

DDD3(C)

C2FAIL 60 indication of correction failure output (open-drain) CFLG 61 correction ﬂag output (open-drain) V1 62 versatile input pin 1 V2 63 versatile input pin 2 LDON 64 laser drive on output (open-drain)

(1)

digital supply voltage 2 for periphery

digital ground 3

W and load control line input (4-wire bus mode)

R/W and load control line input (4-wire-bus mode)

digital ground 4

digital supply voltage 3 for core

Note

1. All supply pins must be connected to the same external power supply voltage.

1995 Nov 29 6

Philips Semiconductors Preliminary speciﬁcation

Digital servo processor and Compact Disc decoder (CD7)

handbook, full pagewidth

C2FAIL 60

CRIN

DDD3(C)

STATUS

TEST2

CROUT

RESET 57

SAA7370A

CL16

SSA1

DDA1

D1 D2 D3

RL D4

R1 R2

refT

SSA2

SELPLL

ISLICE

HFIN

SSA3

10 11 12 13 14 15 16

LDONV2V1 64

ref

HFREF

DDA2

CFLG 61

TEST1

SSD4

V 56

CL11

n.c. 55

26 RA

SILD 54

27 FO

RAB 53

28 SL

SCL 52

TEST3

SDA 51

DDD1(P)

CL4 50

DOBM

SSD3

V 49

SSD1

SAA7370A

SCLK

DDD2(P)

WCLK

DATA

KILL

SSD2

SUB

RCK

SFSY

SBSY

MOTO2

MOTO1

MBG765

Fig.2 Pin configuration.

1995 Nov 29 7

Philips Semiconductors Preliminary speciﬁcation

Digital servo processor and Compact Disc decoder (CD7)

7 FUNCTIONAL DESCRIPTION

7.1 Decoder part

7.1.1 P The decoding part can operate at different disc speeds,

from single-speed (n = 1) up to 8 times speed (n = 8). The factor ‘n’ is called the overspeed factor. A simplified data flow through the decoder part is illustrated in Fig.6.

7.1.2 D The SAA7370A is a multi-speed decoding device, with an

internal phase-locked loop (PLL) clock multiplier. Depending on the crystal frequency used and the internal clock settings (selectable via registers B and E), the playback speeds shown in Table 1 are possible, where ‘n’ is the overspeed factor.

An internal clock multiplier is present, controlled by SELPLL, and should only be used if an 8.4672 MHz or

16.9344 MHz crystal, ceramic resonator or external clock is present.

7.1.3 L For high speed CD-ROM applications, the SAA7370A has

a special mode, the lock-to-disc mode. This allows Constant Angular Velocity (CAV) disc playback with varying input data rates from the inside-to-outside of the disc. In the lock-to-disc mode, the FIFO is blocked and the decoder will adjust its output data rate to the disc speed. Hence, the frequency of the I2S-bus (WCLK and SCLK) clocks are dependent on the disc speed.

RINCIPLE OPERATIONAL MODES OF THE DECODER

ECODING SPEED AND CRYSTAL FREQUENCY

OCK-TO-DISC MODE

SAA7370A

7.1.4 S The SAA7370A may be placed in two standby modes

selected by register B (it should be noted that the device core is still active):

Standby 1: ‘CD-STOP’ mode. Most I/O functions are switched off.

Standby 2: ‘CD-PAUSE’ mode. Audio output features are switched off, but the motor loop, the motor output and the subcode interfaces remain active. This is also called a ‘Hot Pause’.

In the standby modes the various pins will have the following values:

MOTO1 and MOTO2: put in high-impedance, PWM mode (standby 1 and reset: operating in standby 2). Put in high-impedance, PDM mode (standby 1 and reset: operating in standby 2).

SCL, SDA, SILD and RAB: no interaction. Normal operation continues.

SCLK, WCLK, DATA, EF, CL11 and DOBM: 3-state in both standby modes. Normal operation continues after reset.

CRIN, CROUT, CL16 and CL4: no interaction. Normal operation continues.

V1, V2, V3, V4, V5, CFLG and C2FAIL: no interaction. Normal operation continues.

TANDBY MODES

In the lock-to-disc mode there is a limit on the maximum variation in disc speed that the SAA7370A will follow. Disc speeds must always be within 25% to 100% range of their nominal value. The lock-to-disc mode is enabled/disabled by register E.

1995 Nov 29 8

Philips Semiconductors Preliminary speciﬁcation

Digital servo processor and Compact Disc

SAA7370A

decoder (CD7)

Table 1 Playback speeds

CRYSTAL FREQUENCY (MHz)

33.8688 16.9344 8.4672

00xx 0xxx 0 n = 1 −− 11.2896 00xx 0xxx 1 − n=2

(1)

n = 1 11.2896 01xx 0xxx 0 − n=1 − 5.6448 10xx 0xxx 0 n = 2 −− 11.2896 10xx 0xxx 1 − n=4 11xx 0xxx 0 − n=2 00xx 1xxx 0 n = 4

(3)

00xx 1xxx 1 − n=8 01xx 1xxx 0 − n= 4 10xx 1xxx 1 −−n=8

(1) (3)

n = 2 11.2896

− 5.6448

−− 11.2896

(1) (3)

n = 4 11.2896

− 5.6448

(3)

Notes

1. Only if SELPLL = 1, then the CL11 output will be 22.5792 MHz, CL16 will be 33.8688 MHz and CL4 will be

8.4672 MHz.

2. The CL11 output is always a 5.6448 MHz clock if a 16.9344 MHz external clock is used and SELPLL = 0.

3. Data capture performance is not optimized for these options.

CL11 FREQUENCY

(2)

(MHz)

11.2896

7.2 Crystal oscillator

The crystal oscillator is a conventional 2 pin design operating between 8 MHz and 35 MHz. This oscillator is capable of operating with ceramic resonators and with both fundamental and third overtone crystals. External components should be used to suppress the fundamental output of the third overtone crystals as shown in Figs 3 and 4. Typical oscillation frequencies required are

8.4672, 16.9344 or 33.8688 MHz depending on the internal clock settings used and whether or not the clock multiplier is enabled.

SAA7370A

OSCILLATOR

8.4672 MHz

330 Ω

100 kΩ

MBG779

CRINCROUT

22 pF22 pF

SAA7370A

CROUT

MBG778

330 Ω

OSCILLATOR

33.8688 MHz

100 kΩ

CRIN

3.3 µH

1 nF10 pF10 pF

Fig.3 8.4672 MHz fundamental configuration.

1995 Nov 29 9

Fig.4 33.8688 MHz overtone configuration.

Philips Semiconductors Preliminary speciﬁcation

Digital servo processor and Compact Disc decoder (CD7)

7.3 Data slicer and clock regenerator

The SAA7370A has an integrated slice level comparator which can be clocked by the crystal frequency clock, or 8 times the crystal frequency clock (if SELPLL is set HIGH while using an 8.4672 MHz crystal, and register 4 is set to 0xxx). The slice level is controlled by an internal current source applied to an external capacitor under the control of the Digital Phase-Locked Loop (DPLL).

Regeneration of the bit clock is achieved with an internal fully digital PLL. No external components are required and the bit clock is not output. The PLL has two registers (8 and 9) for selecting bandwidth and equalization.

For certain applications an offtrack input is necessary. This is internally connected from the servo part (its polarity can be changed by the foc_parm1 parameter), but may be input via the V1 pin if selected by register C. If this flag is HIGH, the SAA7370A will assume that its servo part is following on the wrong track, and will flag all incoming HF data as incorrect.

SAA7370A

7.4 Demodulator

7.4.1 F A double timing system is used to protect the demodulator

from erroneous sync patterns in the serial data. The master counter is only reset if:

• A sync coincidence detected; sync pattern occurs 588 ±1 EFM clocks after the previous sync pattern

• A new sync pattern is detected within ±6 EFM clocks of its expected position.

The sync coincidence signal is also used to generate the PLL lock signal, which is active HIGH after 1 sync coincidence found, and reset LOW if during 61 consecutive frames no sync coincidence is found. The PLL lock signal can be accessed via the SDA or STATUS pins selected by register 2 and 7.

Also incorporated in the demodulator is a Run Length 2 (RL2) correction circuit. Every symbol detected as RL2 will be pushed back to RL3. To do this, the phase error of both edges of the RL2 symbol are compared and the correction is executed at the side with the highest error probability.

RAME SYNC PROTECTION

inputs

1 nF

22 kΩ

100 nF

SSA

22 pF

22 kΩ

100

SSA

HFIN

HFREF

ref

ISLICE

7.4.2 EFM

DEMODULATION

The 14-bit EFM data and subcode words are decoded into 8-bit symbols.

crystal

clock

DPLL

1/2V

100 µA

MBG397

Fig.5 Data slicer showing typical application components (for n = 4).

1995 Nov 29 10

Philips Semiconductors Preliminary speciﬁcation

Digital servo processor and Compact Disc decoder (CD7)

DOBM

SDA

EBU

reg A

INTERFACE

SCLK

WCLK

S-BUS

1 : no pre-emphasis detected

OR reg D = 01xx (de-emphasis signal at V5)

0 : pre-emphasis detected

AND reg D ≠ 01xx

DATA

INTERFACE

reg 3

(CD-ROM modes)

1 : reg 3 ≠ 101x

0 : reg 3 = 101x

SAA7370A

MBG418

handbook, full pagewidth

SBSY

CD GRAPHICS

MICROCONTROLLER

SFSY

SUB

INTERFACE

0 : reg D = xx01

V4 SUBCODE

INTERFACE

reg F

INTERFACE

SUBCODE

PROCESSOR

0 : reg A = xx1x

1 : reg A = xx0x

DEMODULATOR

DIGITAL PLL AND

mode)

(1f

0 : reg 3 ≠ xx10

1 : reg 3 = xx10

FIFO

PHASE

COMPENSATION

FILTER

DIGITAL

FADE/MUTE/

INTERPOLATE

ERROR

CORRECTOR

DE-EMPHASIS

KILL

reg 3

FILTER

KILL

reg C

Fig.6 Simplified data flow of decoder functions.

data slicer

output from

1995 Nov 29 11

Philips Semiconductors Preliminary speciﬁcation

Digital servo processor and Compact Disc decoder (CD7)

7.5 Subcode data processing

7.5.1 QThe 96-bit Q-channel word is accumulated in an internal

buffer. The last 16 bits are used internally to perform a Cyclic Redundancy Check (CRC). If the data is good, the SUBQREADY-I signal will go LOW. SUBQREADY-I can be read via the SDA or STATUS pins, selected via register 2. Good Q-channel data may be read from SDA.

7.5.2 EIAJ 3 AND 4-WIRE SUBCODE (CD GRAPHICS)

Data from all the subcode channels (P-to- W) may be read via the subcode interface, which conforms to EIAJ CP-2401. The interface is enabled and configured as either a 3-wire or 4-wire interface via register F. The subcode interface output formats are illustrated in Fig.7, where the RCK signal is supplied by another device such as a CD graphics decoder.

CHANNEL PROCESSING

INTERFACES

SAA7370A

7.5.3 V4

Data of subcode channels, Q-to-W, may be read via pin V4 if selected via register D. The format is similar to RS232 and is illustrated in Fig.8. The subcode sync word is formed by a pause of (200/n) µs minimum. Each subcode byte starts with a logic 1 followed by 7 bits (Q-to-W). The gap between bytes is variable between (11.3/n) µs and (90/n) µs.

The subcode data is also available in the EBU output (DOBM) in a similar format.

SUBCODE INTERFACE

handbook, full pagewidth

SBSY

SFSY

RCK

SUB

SFSY

RCK

SUB

SF0 SF1

SF0 SF1 SF2 SF3 SF97 SF0 SF1

SFSY

RCK

SUB

SF2 SF3 SF97 SF0 SF1

P-W P-W P-W

EIAJ 4-wire subcode interface

P-W P-W P-W

EIAJ 3-wire subcode interface

PQRSTUVW

MBG410

Fig.7 EIAJ subcode (CD graphics) interface format.

1995 Nov 29 12

Philips Semiconductors Preliminary speciﬁcation

Digital servo processor and Compact Disc decoder (CD7)

200/n µs

min

W96 1QRSTUVW 1Q

n =disc speed.

7.6 FIFO and error corrector

The SAA7370A has a ±8 frame FIFO. The error corrector is a t = 2, e = 4 type, with error corrections on both C1 (32 symbol) and C2 (28 symbol) frames. Four symbols are used from each frame as parity symbols. This error corrector can correct up to two errors on the C1 level and up to four errors on the C2 level.

The error corrector also contains a flag processor. Flags are assigned to symbols when the error corrector cannot ascertain if the symbols are definitely good. C1 generates output flags which are read after (de-interleaving) by C2, to help in the generation of C2 output flags.

The C2 output flags are used by the interpolator for concealment of uncorrectable errors. They are also output via the EBU signal (DOBM) and the EF output with I2S-bus for CD-ROM applications.

11.3/n µs

Fig.8 Subcode format and timing on pin V4.

SAA7370A

11.3/n µs min 90/n µs max

MBG401

7.6.1 FLAGS OUTPUT (CFLG) The flags output pin CFLG (open-drain) shows the status

of the error corrector and interpolator and is updated every frame (7.35 × n kHz). In the SAA7370A chip a 1-bit flag is present on the CFLG pin as illustrated in Fig.9. This signal shows the status of the error corrector and interpolator.

The first flag bit, F1, is the absolute time sync signal, the FIFO-passed subcode sync and relates the position of the subcode sync to the audio data (DAC output). This flag may also be used in a super FIFO or in the synchronization of different players. The output flags can be made available at bit 4 of the EBU data format (LSB of the 24-bit data word), if selected by register A.

handbook, full pagewidth

n = disc speed.

33.9/n µs

11.3/n µs

F1 F2 F3 F4 F5 F6 F7 F8 F1F8

Fig.9 Flag output timing diagram.

1995 Nov 29 13

33.9/n µs

MBG425

Philips Semiconductors Preliminary speciﬁcation

Digital servo processor and Compact Disc decoder (CD7)

Table 2 Output ﬂags

F1 F2 F3 F4 F5 F6 F7 F8 DESCRIPTION

0xxxxxxxno absolute time sync 1xxxxxxxabsolute time sync x00xxxxxC1 frame contained no errors x01xxxxxC1 frame contained 1 error x10xxxxxC1 frame contained 2 errors x11xxxxxC1 frame uncorrectable x x x 0 0 x x 0 C2 frame contained no errors x x x 0 0 x x 1 C2 frame contained 1 error x x x 0 1 x x 0 C2 frame contained 2 errors x x x 0 1 x x 1 C2 frame contained 3 errors x x x 1 0 x x 0 C2 frame contained 4 errors x x x 1 1 x x 1 C2 frame uncorrectable xxxxx00xno interpolations xxxxx01xat least one 1-sample interpolation xxxxx10xat least one hold and no interpolations xxxxx11xat least one hold and one 1-sample interpolation

SAA7370A

7.6.2 C2FAIL The C2FAIL pin indicates that invalid data has occurred on

the I2S-bus interface. However, due to the structure of the corrector it is impossible to determine which byte has failed. C2FAIL will go LOW for (140/n) µs when invalid data is detected, this data may then occur (15/n) µs before or after the pin is activated.

7.7 Audio functions

7.7.1 DE-EMPHASIS AND PHASE LINEARITY When pre-emphasis is detected in the Q-channel

subcode, the digital filter automatically includes a de-emphasis filter section. When de-emphasis is not required, a phase compensation filter section controls the phase of the digital oversampling filter to ≤±1° within the band 0 to 16 kHz. With de-emphasis the filter is not phase linear.

If the de-emphasis signal is set to be available at V5, selected via register D, then the de-emphasis filter is bypassed.

7.7.2 D

IGITAL OVERSAMPLING FILTER

These attenuations do not include the sample-and-hold at the external DAC output or the DAC post filter. When using the oversampling filter, the output level is scaled −0.5 dB down, to avoid overflow on full scale sine wave inputs (0 to 20 kHz).

Table 3 Filter speciﬁcation

PASS BAND STOP BAND ATTENUATION

0 to 9 kHz −≤0.001 dB

19 to 20 kHz −≤0.03 dB

− 24 kHz ≥25 dB

− 24 to 27 kHz ≥38 dB

− 27 to 35 kHz ≥40 dB

− 35 to 64 kHz ≥50 dB

− 64 to 68 kHz ≥31 dB

− 68 kHz ≥35 dB

− 69 to 88 kHz ≥40 dB

The SAA7370A contains a 2 to 4 times oversampling IIR filter. The filter specification of the 4 times oversampling filter is given in Table 3.

1995 Nov 29 14

Philips Semiconductors Preliminary speciﬁcation

Digital servo processor and Compact Disc decoder (CD7)

7.7.3 CONCEALMENT A 1 sample linear interpolator becomes active if a single

sample is flagged as erroneous but cannot be corrected. The erroneous sample is replaced by a level midway between the preceding and following samples. Left and right channels have independent interpolators. If more than one consecutive non-correctable sample is found, the last good sample is held. A 1-sample linear interpolation is then performed before the next good sample (see Fig.10).

In CD ROM modes (i.e. the DAC interface is selected to be in a CD ROM format) concealment is not executed.

7.7.4 M A digital level controller is present on the SAA7370A which

performs the functions of soft mute, full scale, attenuation and fade; these are selected via register 0:

Mute: signal reduced to 0 in a maximum of 128 steps; (3/n) µs.

Attenuate: signal scaled by −12 dB. Full scale: ramp signal back to 0 dB level. From mute

takes (3/n) µs.

UTE, FULL-SPEED, ATTENUATION AND FADE

SAA7370A

Fade: activates a 128 stage counter which allows the signal to be scaled up/down by 0.07 dB steps

128 = full scale. 120 = −0.5 dB (i.e. full scale if oversampling filter

used). 32 = −12 dB. 0 = mute.

7.7.5 P The peak detector measures the highest audio level

(absolute value) on positive peaks for left and right channels. The 8 most significant bits are output in the Q-channel data in place of the CRC bits. Bits 81 to 88 contain the left peak value (bit 88 = MSB) and bits 89 to 96 contain the right peak value (bit 96 = MSB). The values are reset after reading Q-channel data via SDA.

EAK DETECTOR

Interpolation Hold Interpolation

OK Error OK Error Error Error OK OK

Fig.10 Concealment mechanism.

1995 Nov 29 15

MGA372

Philips Semiconductors Preliminary speciﬁcation

Digital servo processor and Compact Disc

SAA7370A

decoder (CD7)

7.8 DAC interface

The SAA7370A is compatible with a wide range of digital-to-analog converters (DACs). Eleven formats are supported and are given in Table 4. Figures 11 and 12 show the Philips I2S-bus and the EIAJ data formats respectively. When the decoder is operated in lock-to-disc mode, the SCLK frequency is dependent on the disc speed factor ‘d’. All formats are MSB first and fs is (44.1 × n) kHz. The polarity of the WCLK and the data can be inverted; selectable by register 7. It should be noted that EF is only a defined output in CD ROM modes.

Table 4 DAC interface formats

1010 f 1011 f

1110 f 0010 f 0110 f 0000 4f 0100 4f 1100 4f 0011 2f

0111 2f

1111 2f

SAMPLE

FREQUENCY

s s s s s

(2)

s s s

NUMBER OF

BITS

SCLK (MHz) FORMAT INTERPOLATION

16 2.1168 × n CD ROM (I2S-bus) no 16 2.1168 × n CD ROM (EIAJ) no

16/18

(1)

2.1168 × n Philips I2S-bus 16/18 bits

(1)

16 2.1168 × n EIAJ 16 bits yes 18 2.1168 × n EIAJ 18 bits yes 16 8.4672 × n EIAJ 16 bits yes 18 8.4672 × n EIAJ 18 bits yes 18 8.4672 × n Philips I2S-bus 18 bits yes 16 4.2336 × n EIAJ 16 bits yes 18 4.2336 × n EIAJ 18 bits yes 18 4.2336 × n Philips I2S-bus 18 bits yes

yes

Notes

1. in this mode the first 16 bits contain data, but if any of the fade, attenuate or de-emphasis filter functions are activated then the first 18 bits contain data.

2. Cannot be used in the n = 8 mode.

1995 Nov 29 16

Philips Semiconductors Preliminary speciﬁcation

Digital servo processor and Compact Disc decoder (CD7)

MBG424

15 1410DATA

SAA7370A

MBG423

170DATA

S-bus data format (16-bit word length shown).

LEFT CHANNEL DATA (WCLK NORMAL POLARITY)

Fig.11 Philips I

SCLK

15 14

LSB error flag MSB error flag LSB error flag MSB error flag

MODES ONLY)

(CD-ROM

WCLK

AND If

1995 Nov 29 17

SCLK

LEFT CHANNEL DATA

WCLK

MSB error flag LSB error flag MSB error flag

MODES ONLY)

(CD-ROM

AND If

Fig.12 EIAJ data format (18-bit word length shown).

Philips Semiconductors Preliminary speciﬁcation

Digital servo processor and Compact Disc

SAA7370A

decoder (CD7)

7.9 EBU interface

The bi-phase mark digital output signal at pin DOBM is in accordance with the format defined by the IEC958 specification. Three different modes can be selected via register A;

• DOBM pin held LOW.

• Data taken before concealment, mute and fade (must

always be used for CD ROM modes).

• Data taken after concealment, mute and fade.

Table 5 Format

FUNCTION BITS DESCRIPTION

Sync 0 to 3 − Auxiliary 4 to 7 not used; normally zero Error ﬂags 4 CFLG error and interpolation ﬂags when selected by register A Audio sample 8 to 27 ﬁrst 4 bits not used (always zero). 2’s compliment. LSB = bit 12, MSB = bit 27 Validity ﬂag 28 valid = logic 0 User data 29 used for subcode data (Q-to-W) Channel status 30 control bits and category code Parity bit 31 even parity for bits 4 to 30

7.9.1 FORMAT The digital audio output consists of 32-bit words

(‘subframes’) transmitted in bi-phase mark code (two transitions for a logic 1 and one transition for a logic 0). Words are transmitted in blocks of 384. Table 5 gives the formats.

Table 6 Description of Table 5

FUNCTION DESCRIPTION

Sync The sync word is formed by violation of the bi-phase rule and therefore does not contain any data.

Its length is equivalent to 4 data bits. The 3 different sync patterns indicate the following situations: sync B: start of a block (384 words), word contains left sample; sync M: word contains left sample

(no block start) and sync W: word contains right sample. Audio sample Left and right samples are transmitted alternately. Validity ﬂag Audio samples are ﬂagged (bit 28 = 1) if an error has been detected but was uncorrectable.

This ﬂag remains the same even if data is taken after concealment. User data Subcode bits Q-to-W from the subcode section are transmitted via the user data bit.

This data is asynchronous with the block rate. Channel status The channel status bit is the same for left and right words. Therefore a block of 384 words contains

192 channel status bits. The category code is always CD. The bit assignment is given in Table 7.

1995 Nov 29 18

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