The SAA7348 All Compact Disc Engine (ACE) combines
the functionality of a CD decoder (LO9585), a digital servo
(OQ8868) and a microcontroller core (80C51 based) on a
single chip. It was developed for high speed CD-ROM
applications but, due to the large scale integration, can
also be used in other CD applications. The internal
microcontroller makes it possible to develop other
applications quickly. The microcontroller can operate with
internal or external ROM.
1. The analog and digital core supply pins (V
The core and pads can operate at different voltages and should never be connected together directly.
digital supply voltage for pad cells4.55.05.5V
digital supply voltage for the corenote 13.03.33.6V
analog supply voltagenote 13.03.33.6V
supply currentn = 8 mode−90−mA
crystal frequency88.467235MHz
operating ambient temperature0−70°C
storage temperature−55−+125°C
DDA
and V
DDD(core)
) must be connected to the same external supply.
1997 Jul 114
Philips SemiconductorsPreliminary specification
All Compact Disc Engine (ACE)SAA7348GP
5BLOCK DIAGRAM
handbook, full pagewidth
MIDLAD
REFLCA
HFIN
REFHCA
I
ref
V
RH
D1
D2
D3
D4
S1
S2
I
refT
FTC
H
FTC
L
V
DDD(core)
HF
V
V
SSA
V
DDA
22293
(1) (2)(3)(4)
7
8
9
FRONT-END
10
11
SAA7348GP
14
15
16
17
20
21
22
23
24
25
LF
FRONT-END
SSD
V
DDD(pads)
(5)
SBSYRCKVALID
SFSYSUBDACWCLKDACCLK
92
93
94 9565 66 67 68 6962 97 96
DECODER
DIGITAL SERVO
DATASCLKKILL
DEEM
100
89
71
73
72
91
86
85
84
83
82
74
75
78
79
80
90
98
99
DOBM
SUBQW
MOTOV
MOTOS
FB
C2FAIL
CFLG
FOK
TL
RP
DSDEN
CLO
RA
FO
SL
OTD
DEFI
DEFO
LDON
XTALI
XTALO
SELPLL
(1) Pins 13 and 19.
(2) Pins 12 and 18.
(3) Pins 39 and 88.
(4) Pins 29, 38, 51, 61,
63, 70, 76, 81 and
87.
(5) Pins 52, 64 and 77.
28
27
26
CLOCK
PLL
TEST
12330 31 32 33 34 35 36 3748
TS1TS3
TS2
R
XD0
T
XD0
INT0
INT1
R
XD1
T
Fig.1 Block diagram.
1997 Jul 115
XD1
80C51
8
40 to4753 to
A8 to
A15
AD0 to
AD7
5
TPWM
6
TEN
8
60
49 50
ALE
PSENWREARD
MGK498
Philips SemiconductorsPreliminary specification
All Compact Disc Engine (ACE)SAA7348GP
6PINNING
SYMBOLPINTYPE
(1)
DESCRIPTION
TS11Itest control input; this pin should be tied LOW
TS22Itest control input; this pin should be tied LOW
TS33Itest control input; this pin should be tied LOW
RST4Ipower-on reset input
TPWM5Otray PWM output
TEN6Otray enable output
MIDLAD7Aladder middle decoupling of High Frequency (HF) ADC
REFLCA8Aladder low decoupling of HF ADC
HFIN9AHF input
REFHCA10Aladder high decoupling of HF ADC
I
ref
V
V
V
SSA1
DDA1
RH
11Areference current input
12Sanalog ground 1 for HF front-end
13Sanalog supply voltage 1 for HF front-end (3.3 V)
14Acalibrated reference voltage output from ADC
D115Aunipolar current input (central diode signal input)
D216Aunipolar current input (central diode signal input)
D317Aunipolar current input (central diode signal input)
V
V
SSA2
DDA2
18Sanalog ground 2 for LF front-end
19Sanalog supply voltage 2 for LF front-end (3.3 V)
D420Aunipolar current input (central diode signal input)
S121Aunipolar current input (satellite diode signal input)
S222Aunipolar current input (satellite diode signal input)
I
refT
FTC
FTC
H
L
23Acurrent reference, for input range of LF front-end ADCs
24Afast track counter comparator (+) input
25Afast track counter comparator (−) input
SELPLL26Ienables internal clock multiplier PLL
XTALO27Acrystal output
XTALI28Acrystal input
V
R
T
SSD1
XD0
XD0
29Sdigital ground 1
30BP3.0
31BP3.1
INT032BP3.2 (interrupt 0)
INT133BP3.3 (interrupt 1)
R
XD1
T
XD1
34BP3.4
35BP3.5
WR36BP3.6; active LOW
RD37BP3.7; active LOW
V
SSD2
V
DDD1(core)
38Sdigital ground 2
39Sdigital supply voltage 1 for the core (3.3 V)
A840BP2.0 (address or I/O)
1997 Jul 116
Philips SemiconductorsPreliminary specification
All Compact Disc Engine (ACE)SAA7348GP
SYMBOLPINTYPE
(1)
DESCRIPTION
A941BP2.1 (address or I/O)
A1042BP2.2 (address or I/O)
A1143BP2.3 (address or I/O)
A1244BP2.4 (address or I/O)
A1345BP2.5 (address or I/O)
A1446BP2.6 (address or I/O)
A1547BP2.7 (address or I/O)
PSEN48Bprogram store enable (pull-up; active LOW)
ALE49Baddress latch enable (pull-up)
EA50Bexternal ROM select (active LOW); enhanced hooks
V
SSD3
V
DDD1(pads)
51Sdigital ground 3
52Sdigital supply voltage 1 for the pads (5 V); pins 26 to 60
AD053BP0.0 (data, address or I/O)
AD154BP0.1 (data, address or I/O)
AD255BP0.2 (data, address or I/O)
AD356BP0.3 (data, address or I/O)
AD457BP0.4 (data, address or I/O)
AD558BP0.5 (data, address or I/O)
AD659BP0.6 (data, address or I/O)
AD760BP0.7 (data, address or I/O)
V
SSD4
61Sdigital ground 4
DACCLK62TBCC-DAC clock output
V
SSD5
V
DDD2(pads)
63Sdigital ground 5
64Sdigital supply voltage 2 (level shifter) for the pads (5 V)
VALID65Tdata validity flag; C2 error flag; (3-state)
DAC66Tserial audio data output to DAC (3-state)
DATA67Tserial data output to block decoder (3-state)
WCLK68Tword clock output (3-state)
SCLK69Tserial bit clock output (3-state)
V
SSD6
70Sdigital ground 6
SUBQW71Osubcode output; Q to W subcode bits
MOTOS72Tmotor output, sign
MOTOV73Tmotor output, value
DSDEN74ODSD enable output (active LOW)
CLO75Oclock output
V
SSD7
V
DDD3(pads)
76Sdigital ground 7
77Sdigital supply voltage 3 for the pads (5 V); pins 1 to 6 and 65 to 100
RA78Tradial actuator output
FO79Tfocus actuator output
SL80Tsledge control output
V
SSD8
81Sdigital ground 8
1997 Jul 117
Philips SemiconductorsPreliminary specification
All Compact Disc Engine (ACE)SAA7348GP
SYMBOLPINTYPE
(1)
DESCRIPTION
RP82ODradial polarity signal (open drain)
TL83ODtrack loss signal (open drain)
FOK84ODfocus OK signal or decoder measurement signal (open drain)
CFLG85ODcorrection flag output (open drain)
C2FAIL86ODindication of correction failure (open drain)
V
SSD9
V
DDD2(core)
87Sdigital ground 9
88Sdigital supply voltage 2 for the core (3.3 V)
DOBM89TEBU bi-phase mark output (externally buffered) (3-state)
OTD90Ooff-track detect
FB91ODFIFO boundary, motor overflow (open drain)
SBSY92Tsubcode block sync (3-state)
SFSY93Tsubcode frame sync (3-state)
RCK94Isubcode clock input
SUB95TP to W subcode bits (3-state)
DEEM96Odeemphasis active output
KILL97ODkill output (open drain)
DEFI98Idefect detector input
DEFO99Odefect detector output
LDON100ODlaser drive on output (open drain)
Note
1. Pin type abbreviations: O = Output, I = Input, S = power Supply, A = Analog function, OD = Open Drain,
B = Bidirectional, T = 3-state output. All supply pins must be connected directly to their respective external power
supply voltages.
1997 Jul 118
Philips SemiconductorsPreliminary specification
All Compact Disc Engine (ACE)SAA7348GP
handbook, full pagewidth
DDD3(pads)
SSD7
V
V
75
CLO
74
DSDEN
MOTOV
73
MOTOS
72
71
SUBQW
V
70
SSD6
SCLK
69
68
WCLK
67
DATA
DAC
66
VALID
65
V
64
DDD2(pads)
V
63
SSD5
DACCLK
62
V
61
SSD4
AD7
60
59
AD6
AD5
58
AD4
57
AD3
56
AD2
55
AD1
54
AD0
53
V
52
DDD1(pads)
V
51
SSD3
TS1
TS2
TS3
RST
TPWM
TEN
MIDLAD
REFLCA
HFIN
REFHCA
I
ref
V
SSA1
V
DDA1
V
RH
D1
D2
D3
V
SSA2
V
DDA2
D4
S1
S2
I
refT
FTC
FTC
DDD2(core)
LDON
DEFO
DEFI
KILL
DEEM
SUB
RCK
SFSY
SBSYFBOTD
99989796959493929190898887868584838281
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
H
25
L
SAA7348GP
DOBM
V
SSD9
V
C2FAIL
CFLG
FOKTLRP
SSD8
SLFORA
V
8079787776
26
XTALO
SELPLL
XTALI
31323334353637383940414243444546474849
RD
SSD1
V
XD0
R
XD0
T
INT0
INT1
XD1TXD1
R
WR
30
29
28
27
Fig.2 Pin configuration.
1997 Jul 119
SSD2
V
DDD1(core)
V
A8
A9
A10
A11
A12
A13
A14
A15
PSEN
ALE
50
EA
MGK497
Philips SemiconductorsPreliminary specification
All Compact Disc Engine (ACE)SAA7348GP
7FUNCTIONAL DESCRIPTION
The ACE combines the functionality of a DSICS
(OQ8868), a CD65 (LO9585) and an 80C51-based
microcontroller (83C654). In addition, a large part of the
glue logic has been integrated to help minimize the
number of external components required in CD-ROM
applications.
7.1Analog front-end
The front-end circuit can be split into two parts:
1. The decoder input (HF front-end)
2. The servo input (LF front-end).
Each is powered by a separate power supply pin pair.
7.1.1D
ECODER FRONT-END
The EFM signal is fed to the decoder through an ADC,
which is preceded by an AGC stage. In order to make full
use of the digital front-end resolution, the gain control
amplifier should deliver a constant 1.4 V p-p output signal.
The gain range of the AGC is 16 dB and is controlled in
steps of 1.0 dB. The gain of the variable gain amplifier is
controlled by an on-chip digital gain control block. This
block allows for both automatic and microcontroller gain
control.
The internal HF detector is sensitive to any disturbance on
the HF signal; a clean (good signal-to-noise ratio) EFM
signal is necessary since high frequency components can
disturb the HF detector. The input range of the HF
front-end varies from 2.3 V p-p down to 0.35 V p-p. If in the
lower range the signal level is between 25% and 75% of
the ADC range, the HF detector will signal NO HF (In this
range an ADC LSB translates into 5.5 mV, so half the
range equals 175 mV. If the total offset was equal to
6 LSBs, the signal range would be reduced by 2 × 33 mV.
In this case a signal of less than 109 mV would signal NO
HF). To ensure the AGC offset is minimized when the AGC
gain is high, it is necessary to connect a resistor divider to
MIDLAD, as shown in Fig.3.
The SAA7348 contains an on-chip digital equalizer and
data slicer. The equalizer is adaptive; actual equalization
depends on the disc speed. The data slicer has a
microcontroller programmable bandwidth. A fully digital
internal PLL is used to regenerate the bit clock.
The bandwidth and equalization of the PLL can be
programmed by the microcontroller. An off-track input is
necessary for certain applications. If the off-track input flag
is HIGH, the SAA7348 will assume that the servo is
following on the wrong track, and will flag all incoming HF
data as incorrect. The off-track input is connected
internally to the servo section.
handbook, halfpage
+3.3 V
820 Ω820 Ω
10 nF
820 Ω
V
DDA1
MIDLAD
V
SSA1
MGK500
13
7
12
Fig.3 Front-end offset compensation.
7.1.2SERVO FRONT END
The servo front end contains six current-input ADCs (four
for focus and two for the radial signals). The ADCs do not
require external capacitors, unlike the OQ8868 or CD7
(SAA7370). For high performance radial access, a
comparator input is available for the FTC (Fast Track
Count) signal.
The dynamic range of the ADC input currents can be
adjusted over a range dependent on the value of an
external resistor connected to I
. The maximum input
refT
current for the central and satellite diodes, respectively, is
given below:
I
i(central) max()
I
i satellite()max()
V
is generated internally. The value of VRH is dependent
RH
2.4 106×
----------------------- R
1.2 106×
----------------------- R
µ A()=
IrefT
µ A()=
IrefT
upon the spread of internal capacitors and on the value of
the reference current generated by the external resistor on
I
. Typical input currents for a range of resistance values
refT
are given in Table 1.
1997 Jul 1110
Philips SemiconductorsPreliminary specification
All Compact Disc Engine (ACE)SAA7348GP
Table 1 Typical input currents for a range of values of R
The preset latch command can be used to select this
method of V
automatic adjustment.
RH
Alternatively, the dynamic range of the input currents can
be made dependent on the ADC reference voltage, V
RH
In this case, the maximum input current for the central and
satellite diodes, respectively, is:
I
i(central) max()
I
i(satellite) max()
where f
sys
f
×1.10×106–×µA()=
sysVRH
f
×0.55×106–×µA()=
sysVRH
= 4.2336 MHz.
VRH can be set to any one of 32 pre-defined levels,
selectable under software control. VRH is initially set to
2.5 V using the preset latch command, then incremented
or decremented one level at a time by repeatedly
resending the same commend.
7.2Decoder functions
The SAA7348 is a multi-speed decoding device with an
internal phase locked loop clock multiplier. Several
playback speeds can be selected, depending on the
crystal frequency and the internal clock settings;
see Table 2.
The following functions are performed in the decoder
.
block:
• Demodulation (includes sync protection circuit);
converts the 14-bit EFM data and subcode words into
8-bit symbols.
• Subcode data processing.
• Error correction; a t = 2, e = 4 type is used on both C1
(32 symbol) and C2 (28 symbol) frames. The error
corrector can correct up to 2 errors on the C1 level and
up to 4 errors on the C2 level. The error corrector also
contains a flag processor. Flags are assigned to
symbols when the error corrector cannot ascertain if the
symbols are definitely good. C1 generates output flags
that are used by C2. The C2 output flags are used by the
interpolator to conceal uncorrectable errors for audio
output; they are also output via the EBU signal (DOBM)
and the VALID output with I
2
S for CD-ROM applications.
1997 Jul 1111
Philips SemiconductorsPreliminary specification
All Compact Disc Engine (ACE)SAA7348GP
• Motor control; the spindle motor is controlled by a fully
integrated digital servo. Address information from the
internal 8 frame FIFO and disc speed information are
used to calculate the motor control output signals.
Several output modes are supported:
– Pulse density, 2-line (true complement output),
1 × n MHz sample frequency
– PWM-output, 2-line, 22.05 × n kHz modulation
frequency
– CDV motor mode
– Brushless motor control mode.
A simplified illustration of the data flow through the
decoder is shown in Fig.4.
Fig.4 SAA7348 decoder function: simplified data flow.
Philips SemiconductorsPreliminary specification
All Compact Disc Engine (ACE)SAA7348GP
7.3Servo functions
7.3.1S
IGNAL CONDITIONING
The digital codes retrieved from the ADCs are applied to
logic circuitry to obtain various control signals. The signals
from the central aperture diodes are processed to obtain a
normalised focus error signal:
FE
n
D1 D2–
---------------------D1 D2+
D3 D4–
–=
---------------------D3 D4+
where the detector set-up illustrated in Fig.5 is assumed.
For single Foucault focusing, signal conditioning can be
switched under software control such that:
D1 D2–
FE
The error signal, FE
×=
2
n
---------------------D1 D2+
, is further processed by a
n
Proportional Integral and Differential (PID) filter section.
A Focus OK (FOK) flag is generated by means of the
central aperture signal and an adjustable reference level.
This signal is used to provide extra protection for
Track-Loss (TL) generation, drop out detection and the
focus start-up procedure.
The radial or tracking error signal is generated by the
satellite detector signals R1 and R2. The radial error signal
can be formulated as follows:
RE
= (R1 − R2) × re_gain + (R1 − R2) × re_offset
s
where the index ‘s’ indicates the automatic scaling
operation performed on the radial error signal. This scaling
is necessary to avoid non-optimal dynamic range usage in
the digital representation and to reduce the radial
bandwidth spread. Furthermore, the radial error signal will
be free of offset during disc start-up.
The four signals from the central aperture detectors,
together with the satellite detector signals, generate a
track position signal (TPI), which can be formulated as
follows:
TPI = sign [(D1 + D2 + D3 + D4) − (R1 + R2) × sum_gain]
where the weighting factor sum_gain is generated
internally by the SAA7348 during initialization.
handbook, full pagewidth
SATELLITE
DIODE R1
D1
D3
D2
SATELLITE
DIODE R2
single Foucaultastigmatic focusdouble Foucault
SATELLITE
DIODE R1
D1
D2
D3
D4
SATELLITE
DIODE R2
SATELLITE
DIODE R1
D1
D2
D3
D4
SATELLITE
DIODE R2
Fig.5 Detector arrangement.
MBG422
1997 Jul 1114
Philips SemiconductorsPreliminary specification
All Compact Disc Engine (ACE)SAA7348GP
7.3.2Focus control
The SAA7348 performs the following focus servo function:
• Focus start-up
• Focus position control loop
• Drop-out detection
• Focus loss detection and fast restart
• Focus loop gain switching
• Focus automatic gain control loop.
7.3.3R
ADIAL CONTROL
The SAA7348 performs the following radial servo
functions:
• Level initialization
• Radial position control loop
• Sledge control
• Tracking control
• Access with or without track loss information
• Radial automatic gain control loop.
7.3.4O
FF-TRACK COUNTING
The track position signal (TPI) is a flag used to indicate
whether the radial spot is positioned on the track with a
margin of ±0.25 of the track pitch. One of the following
three counting states is selected:
• Protected state
• Slow counting state
• Fast counting state.
7.3.5O
FF-TRACK DETECTION
The Off-Track Detection (OTD) signal flags off-track
conditions; the polarity of this signal is programmable.
7.3.6S
HOCK DETECTION
A shock detector can be switched on during normal track
following. Within an adjustable frequency range, it detects
whether disturbances in the radial spot relative to the track
exceed a programmable level. Every time the Radial
tracking Error (RE) exceeds this level, the radial control
bandwidth is switched to twice its original bandwidth and
the loop gain is increased by a factor of 4.
switched off, applied only to focus control, or applied to
both focus and radial controls under software control.
The actions of the circuit can be monitored on the DEFO
pin (active HIGH).
An external defect detector can be added by removing the
connection between DEFO and DEFI (normal operation)
and inserting the necessary circuitry.
7.3.8D
RIVER INTERFACE
The control signals (pins RA, FO and SL) for the
mechanism actuators are pulse density modulated.
The modulating frequency can be set to either
servo clock
----------------------------- 8
servo clock
orMHz. An analog representation
----------------------------- 4
of the output signals can be generated by connecting a first
order low-pass filter to the outputs.
During reset (i.e. RST pin held HIGH) the RA, FO and SL
pins are high impedance.
7.3.9L
ASER INTERFACE
The LDON pin (open-drain output) is used to turn the laser
on and off. When the laser is on, the output is high
impedance. The action of the LDON pin is controlled by the
xtra_preset parameter; the pin is automatically driven if the
focus control loop is active.
7.4Subcode interface
There are two subcode interfaces:
• One which conforms to
“EIAJ CP-2401”
(using SBSY,
SFSY, RCK and SUB) and can be configured as either
a 3- or 4-wire interface. The interface formats are
illustrated in Fig.6.
• An RS232 like format on SUBQW as illustrated in Fig.7.
The subcode sync word is formed by a pause ofµs
200
--------- n
minimum. Each subcode byte starts with a 1 followed by
7 bits (Q to W). The gap between bytes can vary
betweenandµs. Note that SUBQW is not
11.3
----------n
90
-----n
valid in lock-to-disc mode (includes QLLV).
The subcode data is also available at the EBU output
(DOBM).
7.3.7D
EFECT DETECTION
A defect detection circuit is incorporated into the
SAA7348. If a defect is detected, the circuit can hold all
radial and focus controls. The defect detector can be
The AES/EBU signal on pin DOBM is in accordance with
the format defined in
“IEC 958”
. This signal is only
available in the decoder’s CLV modes if audio features are
enabled (not in QCLV modes). Three different modes can
be selected:
• DOBM pin held LOW
• Data taken before concealment, mute and fade (must
• Data taken after concealment, mute and fade (can only
be used for audio modes).
7.5.1F
ORMAT
The digital audio output consists of 32-bit words
(‘subframes’) transmitted in bi-phasemark code (two
transitions for a logic 1 and one transition for a logic 0).
Words are transmitted in blocks of 384.
always be used for CD-ROM modes)
Table 3 32-bit digital audio output format
FUNCTIONBITSDESCRIPTION
Sync0 to 3note 1
Auxiliary4 to 7not used; normally zero
Error flags4CFLG error and interpolation flags when selected by register A
Audio sample
Validity flag
User data
(3)
(4)
Channel status
(2)
(5)
8 to 27first 4 bits not used (always zero); two’s complement; LSB = bit 12, MSB = bit 27
28valid = logic 0
29used for subcode data (Q to W)
30control bits and category code
Parity bit31even parity for bits 4 to 30
Notes
1. The sync word is formed in violation of the bi-phase rule and, therefore, does not contain any data. Its length is
equivalent to 4 data bits. The 3 different sync patterns indicate the following situations:
a) Sync B: word contains left sample (start of a block, 384 words).
b) Sync M: word contains left sample (no block start).
c) Sync W: word contains right sample.
2. Left and right samples are transmitted alternately.
3. Audio samples are flagged (bit 28 = 1) if an error was detected but could not be corrected. This flag remains the same
even if data is taken after concealment.
4. Subcode bits Q to W from the subcode section are transmitted via the user data bit. This data is asynchronous with
the block rate.
5. The channel status bit is the same for both left and right words. Therefore, a block of 384 words contains 192 channel
status bits. The category code is always CD. The bit assignment is shown in Table 4.
1997 Jul 1117
Philips SemiconductorsPreliminary specification
All Compact Disc Engine (ACE)SAA7348GP
Table 4 Channel status bit assignment
FUNCTIONBITDESCRIPTION
Control0 to 3copy of CRC checked Q-channel control bits 0 to 3; bit 2 is logic 1 when
copy permitted; bit 3 is logic 1 when recording has pre-emphasis
Reserved mode4 to 7always zero
Category code8 to 15CD: bit 8 = logic 1, all other bits = logic 0
Clock accuracy28 and 29set by register A:
10 = class 1 crystal (<50 ppm)
00 = class 2 crystal (<1000 ppm)
01 = class 3 crystal (>1000 ppm)
Remaining16 to 27 and 30 to 191 always zero
7.6S2B interface
This interface is in accordance with the
Description”
. It's a serial interface with a high level
“S2B Interface
command set for controlling a CD-ROM engine.
7.7Audio support
Audio support consists of several parts:
• Serial data interface.
• Deemphasis control (DEEM). This signal is HIGH if the
subcode info of a track defines it to be recorded with
deemphasis.
• Kill control (KILL). This signal tests for digital silence in
the right and left channel before the digital filter.
The output is switched active LOW if silence has been
detected for at least 250 ms, if mute is active, or in
CD-ROM modes.
• Output clock for BCC-DAC applications (DACCLK).
• Oversampled output. The SAA7348 contains a
2 to 4 times oversampling IIR (Infinite
Impulse-Response) filter, and a selectable deemphasis
filter (if the de-emphasis signal is selected to come out
of DEEM then the filter is bypassed; see Table 31).
• Concealment, mute, attenuation and fade. In audio
modes a 1-sample linear interpolator becomes active if
a single sample is flagged as erroneous; left and right
channels have independent interpolators. A digital level
converter performs the following functions:
– soft mute (signal reduced to 0 in a maximum of
128 steps)
– full-scale (signal ramped back to 0 dB level)
– attenuation (signal scaled by −12 dB)
– fade (activates a 128 stage counter which allows the
signal to be scaled up or down in 0.07 dB steps)
– peak detector (measures highest audio level;
absolute level for left and right channels; the 8 MSBs
of each are output in the Q-channel data).
• Mono output selection. Either channel can be selected
to be output over both left and right channels.
7.7.1S
ERIAL AUDIO DATA INTERFACE
The serial data interface can be switched between two
modes: Philips I2S and the EIAJ format.
In each case, the serial data is transferred through a 3-wire
interface. The I2S signal contains three components:
WCLK (word select), SCLK (serial clock) and DAC (serial
data). The polarity of WCLK and of the data can be
inverted.
The oversampling frequency and format are selected as
shown in Table 5. The serial data output is separate from
the CD-ROM output. In CD-ROM mode the DAC serial
data output pin will be muted.
Table 5 Oversampling frequency select
MODE
I2S184f
EIAJ184f
NUMBER
OF BITS
SAMPLE FREQUENCY
182f
16f
182f
18f
164f
162f
16f
s
s
s
s
s
s
s
s
s
1997 Jul 1118
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