Philips SAA7108AE, SAA7109AE User Guide

INTEGRATED CIRCUITS

DATA SH EET

SAA7108AE; SAA7109AE

HD-CODEC

Product speciﬁcation Supersedes data of 2003 Mar 26

2004 Jun 29

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

CONTENTS

1 FEATURES

1.1 Video decoder

1.2 Video scaler

1.3 Video encoder

1.4 Common features 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 ORDERING INFORMATION 5 QUICK REFERENCE DATA 6 BLOCK DIAGRAMS 7 PINNING 8 FUNCTIONAL DESCRIPTION OF DIGITAL

VIDEO ENCODER PART

8.1 Reset conditions

8.2 Input formatter

8.3 RGB LUT

8.4 Cursor insertion

8.5 RGB Y-CB-CR matrix

8.6 Horizontal scaler

8.7 Vertical scaler and anti-flicker filter

8.8 FIFO

8.9 Border generator

8.10 Oscillator and Discrete Time Oscillator (DTO)

8.11 Low-pass Clock Generation Circuit (CGC)

8.12 Encoder

8.13 RGB processor

8.14 Triple DAC

8.15 HD data path

8.16 Timing generator

8.17 Pattern generator for HD sync pulses

8.18 I2C-bus interface

8.19 Power-down modes

8.20 Programmingthegraphicsacquisitionscalerof the video encoder

8.21 Input levels and formats

9 FUNCTIONAL DESCRIPTION OF DIGITAL

VIDEO DECODER PART

9.1 Decoder

9.2 Decoder output formatter

9.3 Scaler

9.4 VBI data decoder and capture (subaddresses 40H to 7FH)

9.5 Image port output formatter (subaddresses 84H to 87H)

9.6 Audio clock generation (subaddresses 30H to 3FH)

10 INPUT/OUTPUT INTERFACES AND PORTS

OF DIGITAL VIDEO DECODER PART

10.1 Analog terminals

10.2 Audio clock signals

10.3 Clock and real-time synchronization signals

10.4 Video expansion port (X port)

10.5 Image port (I port)

10.6 Host port for 16-bit extension of video data I/O (H port)

10.7 Basic input and output timing diagrams for the I and X ports

11 BOUNDARY SCAN TEST

11.1 Initialization of boundary scan circuit

11.2 Device identification codes

12 LIMITING VALUES 13 THERMAL CHARACTERISTICS 14 CHARACTERISTICS OF THE DIGITAL

VIDEO ENCODER PART

15 CHARACTERISTICS OF THE DIGITAL

VIDEO DECODER PART

16 TIMING

16.1 Digital video encoder part

16.2 Digital video decoder part

17 APPLICATION INFORMATION

17.1 Reconstruction filter

17.2 Analog output voltages

17.3 Suggestions for a board layout

18 I2C-BUS DESCRIPTION

18.1 Digital video encoder part

18.2 Digital video decoder part

19 PROGRAMMING START SET-UP OF

DIGITAL VIDEO DECODER PART

19.1 Decoder part

19.2 Audio clock generation part

19.3 Data slicer and data type control part

19.4 Scaler and interfaces

20 PACKAGE OUTLINE 21 SOLDERING 22 DATA SHEET STATUS 23 DEFINITIONS 24 DISCLAIMERS 25 PURCHASE OF PHILIPS I2C COMPONENTS

2004 Jun 29 2

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

1 FEATURES

1.1 Video decoder

• Six analog inputs, internal analog source selectors, e.g. 6 × CVBS or (2 × Y/C and 2 × CVBS) or (1 × Y/C and 4 × CVBS)

• Two analog preprocessing channels in differential CMOS style for best S/N performance

• Fully programmable static gain or Automatic Gain Control (AGC) for the selected CVBS or Y/C channel

• Switchable white peak control

• Two built-in analog anti-aliasing filters

• Two 9-bit video CMOS Analog-to-Digital Converters

(ADCs), digitized CVBS or Y/C signals are available on the Image Port Data (IPD) port under I2C-bus control

• On-chip clock generator

• Line-locked system clock frequencies

• Digital PLL for horizontal sync processing and clock

generation, horizontal and vertical sync detection

• Requires only one crystal (either 24.576 MHz or

32.11 MHz) for all standards

• Automatic detection of 50 and 60 Hz field frequency, and automatic switching between PAL and NTSC standards

• Luminance and chrominance signal processing for PAL BGHI, PAL N, combination PAL N, PAL M, NTSC M, NTSC-Japan, NTSC N, NTSC 4.43 and SECAM

• User programmable luminance peaking or aperture correction

• Cross-colour reduction for NTSC by chrominance comb filtering

• PAL delay line for correcting PAL phase errors

• Brightness Contrast Saturation (BCS) and hue control

on-chip

• Two multi functional real-time output pins controlled by the I2C-bus

• Multi-standard VBI data slicer decoding World Standard Teletext (WST), North-American Broadcast Text System (NABTS), Closed Caption (CC), Wide Screen Signalling (WSS), Video Programming System (VPS), Vertical Interval Time Code (VITC) variants (EBU/SMPTE) etc.

• StandardITU 656 Y-CB-CR4:2:2format(8-bit)onIPD output bus

• Enhanced ITU 656 output format on IPD output bus containing:

– active video – raw CVBS data for INTERCAST applications

(27 MHz data rate)

– decoded VBI data

• Detection of copy protected input signals according to the Macrovision unauthorized recording of pay-TV or video tape signals.

1.2 Video scaler

• Both up and downscaling

• Conversion to square pixel format

• NTSC to 288 lines (video phone)

• Phaseaccuracybetterthan1/64pixelorline,horizontally

or vertically

• Independent scaling definitions for odd and even fields

• Anti-alias filter for horizontal scaling

• Provides output as:

– scaled active video – raw CVBS data for INTERCAST, WAVE-PHORE,

POPCON applications or general VBI data decoding (27 MHz or sample rate converted)

• Local video output for Y-CB-CR4 : 2 : 2 format (VMI, VIP, ZV).

(1) Macrovision is a trademark of the Macrovision Corporation.

(1)

standard. Can be used to prevent

2004 Jun 29 3

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

1.3 Video encoder

• Digital PAL/NTSC encoder with integrated high quality scaler and anti-flicker filter for TV output from a PC

• Supports Intel Digital Video Out (DVO) low voltage interfacing to graphics controller

• 27 MHz crystal-stable subcarrier generation

• Maximum graphics pixel clock 85 MHz at double edged

clocking, synthesized on-chip or from external source

• Programmable assignment of clock edge to bytes (in double edged mode)

• Synthesizable pixel clock (PIXCLK) with minimized outputjitter,canbeusedasreferenceclock for the VGC, as well

• PIXCLK output and bi-phase PIXCLK input (VGC clock loop-through possible)

• Hot-plug detection through dedicated interrupt pin

• Supported VGA resolutions for PAL or NTSC legacy

video output up to 1280 × 1024 graphics data at 60 or 50 Hz frame rate

• Supported VGA resolutions for HDTV output up to 1920 × 1080 interlaced graphics data at 60 or 50 Hz frame rate

• Three Digital-to-Analog Converters (DACs) for CVBS (BLUE, CB), VBS (GREEN, CVBS) and C (RED, CR)at 27 MHz sample rate (signals in parenthesis are optionally selected), all at 10-bit resolution

• Non-interlaced CB-Y-CR or RGB input at maximum 4:4:4 sampling

• Downscaling and upscaling from 50 to 400 %

• Optional interlaced CB-Y-CR input of Digital Versatile

Disk (DVD) signals

• Optional non-interlaced RGB output to drive second VGA monitor (bypass mode, maximum 85 MHz)

• 3 × 256 bytes RGB Look-Up Table (LUT)

• Support for hardware cursor

• HDTV up to 1920 × 1080 interlaced and 1280 × 720

progressive, including 3-level sync pulses

• Programmable border colour of underscan area

• Programmable 5 line anti-flicker filter

• On-chip 27 MHz crystal oscillator (3rd-harmonic or

fundamental 27 MHz crystal)

• Fast I2C-bus control port (400 kHz)

• Encoder can be master or slave

• Adjustable output levels for the DACs

• Programmable horizontal and vertical input

synchronization phase

• Programmable horizontal sync output phase

• Internal Colour Bar Generator (CBG)

• Optional support of various Vertical Blanking Interval

(VBI) data insertion

• Macrovision Pay-per-View copy protection system rev. 7.01, rev. 6.1 and rev. 1.03 (525p) as option; thisappliesto SAA7108AE only. The device is protected by USA patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. Use of the Macrovision anti-copy process in the device is licensed for non-commercial home use only. Reverse engineering or disassembly is prohibited. Please contact your nearest Philips Semiconductors sales office for more information.

1.4 Common features

• 5 V tolerant digital I/O ports

• I2C-bus controlled (full read-back ability by an external

controller, bit rate up to 400 kbits/s)

• Versatile power-save modes

• Boundary scan test circuit complies with the

1149.b1-1994”

encoder)

• Monolithic CMOS 3.3 V device

• BGA156 package

• Moisture Sensitive Level (MSL): e3.

2 APPLICATIONS

• Notebook (low-power consumption)

• PCMCIA card application

• AGP based graphics cards

• PC editing

• Image processing

• Video phone applications

• INTERCAST and PC teletext applications

• Security applications

• Hybrid satellite set-top boxes.

(separate ID codes for decoder and

“IEEE Std.

2004 Jun 29 4

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

3 GENERAL DESCRIPTION

The SAA7108AE; SAA7109AE is a new multi-standard video decoder and encoder chip, offering high quality video input and TV output processing as required by PC-99 specifications. It enables hardware manufacturers to implement versatile video functions on a significantly reduced printed-circuit board area at very competitive costs.

Separate pins for supply voltages as well as for I2C-bus control and boundary scan test have been provided for the video encoder and decoder sections to ensure both flexible handling and optimized noise behaviour.

Thevideo encoder is used to encode PC graphics data at maximum1280 × 1024resolution(optionally 1920 × 1080 interlaced) to PAL (50 Hz) or NTSC (60 Hz) video signals. A programmable scaler and anti-flicker filter (maximum 5 lines) ensures properly sized and flicker-free TV display as CVBS or S-video output.

Alternatively, the three Digital-to-Analog Converters (DACs) can output RGB signals together with a TTL composite sync to feed SCART connectors.

When the scaler/interlacer is bypassed, a second VGA monitor can be connected to the RGB outputs and separate H and V-syncs as well, thereby serving as an auxiliary monitor at maximum 1280 × 1024 resolution/60 Hz (PIXCLK < 85 MHz). Alternatively this port can provide Y, PB and PR signals for HDTV monitors.

The encoder section includes a sync/clock generator and on-chip DACs.

All inputs intended to interface to the host graphics controller are designed for low-voltage signals down to

1.1 V and up to 3.45 V.

The video decoder, a 9-bit video input processor, is a combination of a 2-channel analog pre-processing circuit including source selection, anti-aliasing filter and Analog-to-Digital Converter (ADC), automatic clamp and gain control, a Clock Generation Circuit (CGC), and a digital multi-standard decoder (PAL BGHI, PAL M, PAL N, combination PAL N, NTSC M, NTSC-Japan, NTSC N, NTSC 4.43 and SECAM).

The decoder includes a brightness, contrast and saturation control circuit, a multi-standard VBI data slicer and a 27 MHz VBI data bypass. The pure 3.3 V (5 V compatible) CMOS circuit SAA7108AE; SAA7109AE, consisting of an analog front-end and digital video decoder,a digital video encoder and analog back-end, is a highly integrated circuit especially designed for desktop video applications.

The decoder is based on the principle of line-locked clock decoding and is able to decode the colour of PAL, SECAM and NTSC signals into ITU-R BT.601 compatible colour component values.

The encoder can operate fully independently at its own variable pixel clock, transporting graphics input data, and at the line-locked, single crystal-stable video encoding clock.

As an option, it is possible to slave the video PAL/NTSC encodingto the video decoderclockwith the encoder FIFO acting as a buffer to decouple the line-locked decoder clock from the crystal-stable encoder clock.

4 ORDERING INFORMATION

TYPE

NUMBER

SAA7108AE BGA156 plastic ball grid array package; 156 balls; body 15 × 15 × 1.15 mm SOT472-1 SAA7109AE

2004 Jun 29 5

NAME DESCRIPTION VERSION

PACKAGE

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

5 QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

DDD

DDA

amb

A+D

Note

1. Power dissipation is extremely dependent on programming and selected application.

6 BLOCK DIAGRAMS

digital supply voltage 3.15 3.3 3.45 V analog supply voltage 3.15 3.3 3.45 V ambient temperature 0 − 70 °C analog and digital power dissipation note 1 −−1.7 W

handbook, full pagewidth

graphics input

analog

video input

digital video

CVBS, Y/C

Y-CB-CR/RGB

digital video

input and output

X port

ANALOG VIDEO

ACQUISITION AND

DEMODULATOR

VIDEO DECODER PART

VIDEO ENCODER PART

SCALER

AND

INTERLACER

SCALER

VIDEO

ENCODER

Fig.1 Simplified block diagram.

I port (IPD)

CVBS, Y/C RGB

MHB903

digital video output

analog video output

2004 Jun 29 6

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2004 Jun 29 7

C1, C2, B1, B2, A2, B4,

PD11 to

PD0

B3, A3, F3, H1, H2, H3

INPUT

FORMATTER

FIFO AND

UPSAMPLING

LUT

AND

CURSOR

RGB TO Y-CB-C

MATRIX

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

PIXCLKI

PIXCLKO

DECIMATOR

4 : 4 : 4 to 4 : 2 : 2

FIFO

PIXEL CLOCK

SYNTHESIZER

XTALIe

HORIZONTAL

SCALER

BORDER

GENERATOR

SAA7108AE SAA7109AE

CRYSTAL

OSCILLATOR

XTALOe

27 MHz

TTX_SRES

VERTICAL

SCALER

ENCODER

GENERATOR

G1A6A5 C3

VSVGC

FSVGC

VIDEO

OUTPUT

TIMING

F1 G3

HSVGC

CBO TTXRQ_XCLKO2

Fig.2 Block diagram (video encoder part).

ndbook, full pagewidth

SDAe

VERTICAL

FILTER

TRIPLE

DAC

I2C-BUS

CONTROL

SCLe

BLUE_CB_CVBS

GREEN_VBS_CVBS

RED_CR_C_CVBS

VSM

HSM_CSYNC

F12

TVD

E2 D2E3 C4

RESe

MBL785

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2004 Jun 29 8

]

XPD[7:0

XRH

K2, K3, L1 to L3 M1, M2, N1

X PORT I/O FORMATTING

K14

ASCLK

AMXCLK

J12

DDXd

J13

XRV

SSXd

XTRI

XRDY

FIR-PREFILTER

PRESCALER

SCALER BCS

GENERAL PURPOSE

D11, F11, J4, J11, L4, L11

DDId

RESd

XTOUTd

XTALId

XTALOd

AI11 AI12 AI21 AI22 AI23 AI24

AOUT

AI1D AI2D

AGND

M12 N14 P4 P2 P3

P13 P11 P10 P9 P7 P6 M10

P12 P8

N10

LLC2

LLC

M14

CLOCK GENERATION

POWER-ON CONTROL

ANALOG

DUAL

ADC

TRSTd

RTCO

(1)

L14

L13

AND

BOUNDARY

SCAN

TEST

TCLKd

TMSd

RTS0

TDId

XCLK

RTS1

K13

L10

DIGITAL

DECODER

WITH

ADAPTIVE

COMB

FILTER

AMCLK

TDOd

XDQ

EXPANSION PORT PIN MAPPING I/O CONTROL I2C-BUSREAL-TIME OUTPUT

AUDIO

CLOCK

GENERATION

K12

ALRCLK

(1)

, full pagewidth

HPD[7:0

PROGRAMMING

AND

VBI DATA SLICER

D10, G11, L7, L9

DDEd

A13, D12, C12, B12, A12, C11, B11, A11

chrominance of 16-bit input

ARRAY

EVENT CONTROLLER

BUFFER

DDAd

]

LINE FIFO

M8, M9, N11

VERTICAL

SCALING

E11, K4, K11

SSId

SDAd

A/B

MUX

SSEd

L12

H4, H11, L6, M13

SCLd

M11

HORIZONTAL

FINE

(PHASE)

SCALING

M7, N7 to N9, N12, N13

SSAd

TEST5

TEST4

TEST3

SAA7108AE SAA7109AE

VIDEO

FIFO

TEXT

FIFO

VIDEO/TEXT

ARBITER

TEST2

to 8(16) MUX

TEST1

TEST0

C10

H13

B10

E14, D14, C14, B14, E13, D13, C13, B13

IMAGE PORT PIN MAPPING

MBL791

H14 G12

F13 F14

G13

H12

J14

G14

IPD[7:0 IDQ IGPH IGPV IGP0 IGP1

ICLK

ITRDY ITRI

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

]

(1) The pins RTCO and ALRCLK are used for configuration of the I2C-bus interface

and the definition of the crystal oscillator frequency at RESET (pin strapping).

Fig.3 Block diagram (video decoder part).

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

7 PINNING

SYMBOL PIN TYPE

(1)

DESCRIPTION

PD7 A2 I MSB of encoder input bus with CB-Y-CR 4 : 2 : 2; see Tables 9 to 15 for pin

assignment

PD4 A3 I MSB − 3 of encoder input bus with CB-Y-CR 4 : 2 : 2; see Tables 9 to 15 for

pin assignment

TRSTe A4 I/pu test reset input for Boundary Scan Test (BST) (encoder); active LOW; with

internal pull-up; notes 2 and 3 XTALIe A5 I 27 MHz crystal input (encoder) XTALOe A6 O 27 MHz crystal output (encoder) DUMP A7 O DAC reference pin (encoder), 12 Ω resistor connected to V V

SSXe

A8 S ground for oscillator (encoder) RSET A9 O DAC reference pin (encoder), 1 kΩ resistor connected to V V

DDAe

A10 S 3.3 V analog supply voltage (encoder)

SSAe

HPD0 A11 I/O MSB − 7 of Host Port Data (HPD) output bus HPD3 A12 I/O MSB − 4 of HPD output bus HPD7 A13 I/O MSB of HPD output bus PD9 B1 I see Tables 9, 14 and 15 for pin assignment with different encoder input

formats

PD8 B2 I see Tables 9, 14 and 15 for pin assignment with different encoder input

formats

PD5 B3 I MSB − 2 of encoder input bus with CB-Y-CR 4 : 2 : 2; see Tables 9 to 15 for

pin assignment

PD6 B4 I MSB − 1 of encoder input bus with CB-Y-CR 4 : 2 : 2; see Tables 9 to 15 for

pin assignment TDIe B5 I/pu test data input for BST (encoder); note 4 V

DDAe

B6 S 3.3 V analog supply voltage (encoder) DUMP B7 O DAC reference pin (encoder); connected to A7 V V

SSAe DDAe

B8 S analog ground (encoder)

B9 S 3.3 V analog supply voltage (encoder) TEST1 B10 I scan test input 1, do not connect HPD1 B11 I/O MSB − 6 of HPD output bus HPD4 B12 I/O MSB − 3 of HPD output bus IPD0 B13 O MSB − 7 of IPD output bus IPD4 B14 O MSB − 3 of Image Port Data (IPD) output bus PD11 C1 I see Tables 9, 14 and 15 for pin assignment with different encoder input

formats

PD10 C2 I see Tables 9, 14 and 15 for pin assignment with different encoder input

formats TTX_SRES C3 I teletext input or sync reset input (encoder) TTXRQ_XCLKO2 C4 O teletext request output or 13.5 MHz clock output of the crystal oscillator

(encoder) V

SSIe

C5 S digital ground core (encoder)

BLUE_CB_CVBS C6 O BLUE or CB or CVBS output

2004 Jun 29 9

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

SYMBOL PIN TYPE

(1)

DESCRIPTION

GREEN_VBS_CVBS C7 O GREEN or VBS or CVBS output RED_CR_C_CVBS C8 O RED or CR or C or CVBS output V

DDAe

C9 S 3.3 V analog supply voltage (encoder) TEST2 C10 I scan test input 2, do not connect HPD2 C11 I/O MSB − 5 of HPD output bus HPD5 C12 I/O MSB − 2 of HPD output bus IPD1 C13 O MSB − 6 of IPD output bus IPD5 C14 O MSB − 2 of IPD output bus TDOe D1 O test data output for BST (encoder); note4 RESe D2 I reset input (encoder); active LOW TMSe D3 I/pu test mode select input for BST (encoder); note 4 V

DDIEe

SSIe

DDXe

D4 S 3.3 V digital supply voltage for core and peripheral cells (encoder)

D5 S digital ground core (encoder)

D6 S 3.3 V supply voltage for oscillator (encoder) VSM D7 O vertical synchronization output to VGA monitor (non-interlaced) HSM_CSYNC D8 O horizontal synchronization output to VGA monitor (non-interlaced) or

composite sync for RGB-SCART V V V

DDAe DDEd DDId

D9 S 3.3 V analog supply voltage (encoder) D10 S 3.3 V digital supply voltage for peripheral cells (decoder) D11 S 3.3 V digital supply voltage for core (decoder)

HPD6 D12 I/O MSB − 1 of HPD output bus IPD2 D13 O MSB − 5 of IPD output bus IPD6 D14 O MSB − 1 of IPD output bus TCKe E1 I/pu test clock input for BST (encoder); note 4 SCLe E2 I I2C-bus serial clock input (encoder) HSVGC E3 I/O horizontal synchronization output to Video Graphics Controller (VGC)

(optional input) V V

SSEe SSId

E4 S digital ground peripheral cells (encoder)

E11 S digital ground core (decoder) n.c. E12 − not connected IPD3 E13 O MSB − 4 of IPD output bus IPD7 E14 O MSB of IPD output bus VSVGC F1 I/O vertical synchronization output to VGC (optional input) PIXCLKI F2 I pixel clock input (looped through) PD3 F3 I MSB − 4 of encoder input bus with CB-Y-CR 4 : 2 : 2; see Tables 9 to 15 for

pin assignment

DD(DVO)

DDId

F4 S digital supply voltage for DVO cells

F11 S 3.3 V digital supply voltage for core (decoder) TVD F12 O TV Detector; hot-plug interrupt pin, HIGH if TV is connected IGPV F13 O multi-purpose vertical reference output with IPD output bus IGP0 F14 O general purpose output signal 0 with IPD output bus

2004 Jun 29 10

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

SYMBOL PIN TYPE

(1)

DESCRIPTION

FSVGC G1 I/O frame synchronization output to VGC (optional input) SDAe G2 I/O I2C-bus serial data input/output (encoder) CBO G3 O composite blanking output to VGC; active LOW PIXCLKO G4 O pixel clock output to VGC V

DDEd

G11 S 3.3 V digital supply voltage for peripheral cells (decoder) IGPH G12 O multi-purpose horizontal reference output with IPD output bus IGP1 G13 O general purpose output signal 1 with IPD output bus ITRI G14 I/(O) programmable control signals for IPD output bus PD2 H1 I MSB − 5 of encoder input bus with CB-Y-CR 4 : 2 : 2; see Tables 9 to 15 for

pin assignment

PD1 H2 I MSB − 6 of encoder input bus with CB-Y-CR 4 : 2 : 2; see Tables 9 to 15 for

pin assignment

PD0 H3 I MSB − 7 of encoder input bus with CB-Y-CR 4 : 2 : 2; see Tables 9 to 15 for

pin assignment V V

SSEd SSEd

H4 S digital ground for peripheral cells (decoder)

H11 S digital ground for peripheral cells (decoder) ICLK H12 I/O clock for IPD output bus (optional clock input) TEST0 H13 O scan test output, do not connect IDQ H14 O data qualiﬁer for IPD output bus TEST4 J1 O scan test output, do not connect TEST5 J2 I scan test input, do not connect TEST3 J3 I scan test input, do not connect V V

DDId DDId

J4 S 3.3 V digital supply voltage for core (decoder)

J11 S 3.3 V digital supply voltage for core (decoder) AMXCLK J12 I audio master external clock input ALRCLK J13 (I/)O audio left/right clock output; can be strapped to supply via a 3.3 kΩ resistor to

indicate that the default 24.576 MHz crystal (ALRCLK = 0; internal pull-down)

has been replaced by a 32.110 MHz crystal (ALRCLK = 1); notes 5 and 6 ITRDY J14 I target ready input for IPD output bus XTRI K1 I control signal for all X port pins XPD7 K2 I/O MSB of XPD bus XPD6 K3 I/O MSB − 1 of XPD bus V V

SSId SSId

K4 S digital ground core (decoder)

K11 S digital ground core (decoder) AMCLK K12 O audio master clock output, must be less than 50 % of crystal clock RTS0 K13 O real-time status or sync information line 0 ASCLK K14 O audio serial clock output XPD5 L1 I/O MSB − 2 of XPD bus XPD4 L2 I/O MSB − 3 of XPD bus XPD3 L3 I/O MSB − 4 of XPD bus V

DDId

L4 S 3.3 V digital supply voltage for core (decoder)

XRV L5 I/O vertical reference for XPD bus

2004 Jun 29 11

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

SYMBOL PIN TYPE

SSEd

DDEd

DDXd

DDEd

L6 S digital ground for peripheral cells (decoder) L7 S 3.3 V digital supply voltage for peripheral cells (decoder) L8 S 3.3 V supply voltage for oscillator (decoder) L9 S 3.3 V digital supply voltage for peripheral cells (decoder)

(1)

DESCRIPTION

RTS1 L10 O real-time status or sync information line 1 V

DDId

L11 S 3.3 V digital supply voltage for core (decoder) SDAd L12 I/O I2C-bus serial data input/output (decoder) RTCO L13 (I/)O real-time control output; contains information about actual system clock

frequency, ﬁeld rate, odd/even sequence, decoder status, subcarrier frequency and phase and PAL sequence (see external document

Functional Description”

, available on request); the RTCO pin is enabled via

“RTC

I2C-bus bit RTCE; see notes 5 and 7 and Table 150 LLC2 L14 O line-locked1⁄2clock output (13.5 MHz nominal) XPD2 M1 I/O MSB − 5 of XPD bus XPD1 M2 I/O MSB − 6 of XPD bus XCLK M3 I/O clock for XPD bus XDQ M4 I/O data qualiﬁer for XPD bus TMSd M5 I/pu test mode select input for BST (decoder); note 4 TCKd M6 I/pu test clock input for BST (decoder); note 4 V V V

SSAd DDAd DDAd

M7 S analog ground (decoder) M8 S 3.3 V analog supply voltage (decoder)

M9 S 3.3 V analog supply voltage (decoder) AOUT M10 O analog test output (do not connect) SCLd M11 I I2C-bus serial clock input (decoder) RESd M12 O reset output signal; active LOW (decoder) V

SSEd

M13 S digital ground for peripheral cells (decoder) LLC M14 O line-locked clock output (27 MHz nominal) XPD0 N1 I/O MSB − 7 of XPD bus XRH N2 I/O horizontal reference for XPD bus XRDY N3 O data input ready for XPD bus TRSTd N4 I/pu test reset input for BST (decoder); active LOW; with internal pull-up;

notes 2 and 3 TDOd N5 O test data output for BST (decoder); note4 TDId N6 I/pu test data input for BST (decoder); note 4 V V V

SSAd SSAd SSAd

N7 S analog ground (decoder) N8 S analog ground (decoder)

N9 S analog ground (decoder) AGND N10 S analog ground (decoder) connected to substrate V V V

DDAd SSAd SSAd

N11 S 3.3 V analog supply voltage (decoder) N12 S analog ground (decoder) N13 S analog ground (decoder)

CE N14 I chip enable or reset input (with internal pull-up)

2004 Jun 29 12

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

SYMBOL PIN TYPE

(1)

DESCRIPTION

XTALId P2 I 27 MHz crystal input (decoder) XTALOd P3 O 27 MHz crystal output (decoder) XTOUTd P4 O crystal oscillator output signal (decoder); auxiliary signal V

SSXd

P5 S ground for crystal oscillator (decoder) AI24 P6 I analog input 24 AI23 P7 I analog input 23 AI2D P8 I differential analog input for channel 2; connect to ground via a capacitor AI22 P9 I analog input 22 AI21 P10 I analog input 21 AI12 P11 I analog input 12 AI1D P12 I differential analog input for channel 1; connect to ground via a capacitor AI11 P13 I analog input 11

Notes

1. Pin type: I = input, O = output, S = supply, pu = pull-up.

2. For board design without boundary scan implementation connect TRSTe and TRSTd to ground.

3. This pin provides easy initialization of the Boundary Scan Test (BST) circuit. TRSTe and TRSTd can be used to force the Test Access Port (TAP) controller to the TEST_LOGIC_RESET state (normal operation) at once.

4. In accordance with the

“IEEE1149.1”

standard the pads TDIe (TDId), TMSe (TMSd), TCKe (TCKd) and TRSTe

(TRSTd) are input pads with an internal pull-up resistor and TDOe (TDOd) is a 3-state output pad.

5. Pin strapping is done by connecting the pin to supply via a 3.3 kΩ resistor. During the power-up reset sequence the corresponding pins are switched to input mode to read the strapping level. For the default setting no strapping resistor is necessary (internal pull-down).

6. Pin ALRCLK: 0 = 24.576 MHz crystal (default); 1 = 32.110 MHz crystal.

7. Pin RTCO: operates as I2C-bus slave address pin; RTCO = 0 slave address 42H/43H (default); RTCO = 1 slave address 40H/41H.

handbook, halfpage

P N M

L K

J H G

E D C B A

234567891011121314

SAA7108AE SAA7109AE

Fig.4 Pin configuration.

2004 Jun 29 13

MBL788

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2004 Jun 29 14

Table 1 Pin assignment (top view)

123456 7 8 91011121314

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

A PD7 PD4 TRSTe XTALIe XTALOe DUMP V

B PD9 PD8 PD5 PD6 TDIe V

C PD11 PD10 TTX_

SRES

D TDOe RESe TMSe V

E TCKe SCLe HSVGC V

F VSVGC PIXCLKI PD3 V

TTXRQ_ XCLKO2

DDIEe

SSEe

DD(DVO)

SSIe

BLUE_

CB_CVBS

DDAe

DDXe

DUMP V

GREEN_

RED_CR_C_

VBS_CVBS

VSM HSM_CSYNC V

SSXe

SSAe

CVBS

RSET V

DDAe

DDAeVDDEdVDDId

DDAe

TEST1 HPD1 HPD4 IPD0 IPD4

TEST2 HPD2 HPD5 IPD1 IPD5

G FSVGC SDAe CBO PIXCLKO V

H PD2 PD1 PD0 V

J TEST4 TEST5 TEST3 V

K XTRI XPD7 XPD6 V

SSEd

DDId

SSId

HPD0 HPD3 HPD7

HPD6 IPD2 IPD6

SSId

DDId

DDEd

SSEd

DDId

SSId

n.c. IPD3 IPD7

TVD IGPV IGP0

IGPH IGP1 ITRI

ICLK TEST0 IDQ

AMXCLK ALRCLK ITRDY

AMCLK RTS0 ASCLK

L XPD5 XPD4 XPD3 V

DDId

XRV V

SSEd

M XPD2 XPD1 XCLK XDQ TMSd TCKd V

N XPD0 XRH XRDY TRSTd TDOd TDId V

P XTALId XTALOd XTOUTd V

SSXd

AI24 AI23 AI2D AI22 AI21 AI12 AI1D AI11

DDEd

SSAd

DDXd

DDAd

SSAd

RTS1 V

DDEd

AOUT SCLd RESd V

DDAd

AGND V

SSAd

DDId

DDAd

SDAd RTCO LLC2

LLC

SSAd

SSEd

SSAd

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

8 FUNCTIONAL DESCRIPTION OF DIGITAL VIDEO

ENCODER PART

The digital video encoder encodes digital luminance and colour difference signals (CB-Y-CR) or digital RGB signals into analog CVBS, S-video and, optionally, RGB or CR-Y-CB signals. NTSC M, PAL B/G and sub-standards are supported.

The SAA7108AE; SAA7109AE can be directly connected to a PC video graphics controller with a maximum resolution of 1280 × 1024 (progressive) or 1920 × 1080 (interlaced) at a 50 or 60 Hz frame rate. A programmable scalerscalesthecomputergraphics picture so that it will fit into a standard TV screen with an adjustable underscan area.Non-interlaced-to-interlaced conversion is optimized with an adjustable anti-flicker filter for a flicker-free display at a very high sharpness.

Besides the most common 16-bit 4 :2:2 CB-Y-CR input format (using 8 pins with double edge clocking), other CB-Y-CR and RGB formats are also supported; see Tables 9 to 15.

Acomplete3 × 256 bytes Look-Up Table (LUT), which can be used, for example, as a separate gamma corrector, is locatedintheRGBdomain;itcan be loaded either through the video input port PD (Pixel Data) or via the I2C-bus.

The SAA7108AE; SAA7109AE supports a 32 × 32 × 2-bit hardware cursor, the pattern of which can also be loaded through the video input port or via the I2C-bus.

It is also possible to encode interlaced 4 :2:2 video signals such as PC-DVD; for that the anti-flicker filter, and in most cases the scaler, will simply be bypassed.

Besides the applications for video output, the SAA7108AE;SAA7109AE can alsobeused for generating a kind of auxiliary VGA output, when the RGB non-interlacedinputsignalisfed to the DACs. This may be of interest for example, when the graphics controller provides a second graphics window at its video output port.

The basic encoder function consists of subcarrier generation, colour modulation and insertion of synchronization signals at a crystal-stable clock rate of

13.5 MHz (independent of the actual pixel clock used at the input side), corresponding to an internal 4 :2:2 bandwidth in the luminance/colour difference domain. Luminance and chrominance signals are filtered in accordance with the standard requirements of and

“ITU-R BT.470-3”

“RS-170-A”

For ease of analog post filtering the signals are twice oversampled to 27 MHz before digital-to-analog conversion.

The total filter transfer characteristics (scaler and anti-flicker filter are not taken into account) are illustrated in Figs 5 to 10. All three DACs are realized with full 10-bit resolution. The CR-Y-CB to RGB dematrix can be bypassed (optionally) in order to provide the upsampled CR-Y-CB input signals.

The8-bit multiplexed CB-Y-CRformatsare (D1 format) compatible, but the SAV and EAV codes can be decoded optionally, when the device is operated in slave mode. For assignment of the input data to the rising or falling clock edge see Tables 9 to 15.

In order to display interlaced RGB signals through a euro-connector TV set, a separate digital composite sync signal (pin HSM_CSYNC) can be generated; it can be advanced up to 31 periods of the 27 MHz crystal clock in order to be adapted to the RGB processing of a TV set.

The SAA7108AE; SAA7109AE synthesizes all necessary internal signals, colour subcarrier frequency and synchronization signals from that clock.

It is also possible to connect pin RTCO of the decoder section to pin RTCI of the encoder section. Thus, information containing actual subcarrier frequency, PAL-ID etc. is available in case the line-locked clock of the decoder section is used for re-encoding of the encoder section.

Wide screen signalling data can be loaded via the I2C-bus and is inserted into line 23 for standards using a 50 Hz field rate.

VPS data for program dependent automatic start and stop of such featured VCRs is loadable via the I2C-bus.

The IC also contains Closed Caption and extended data servicesencoding(line 21), and supports teletext insertion forthe appropriate bit stream formatata 27 MHz clock rate (see Fig.51). It is also possible to load data for the copy generation management system into line 20 of every field (525/60 line counting).

A number of possibilities are provided for setting different video parameters such as:

• Black and blanking level control

• Colour subcarrier frequency

• Variable burst amplitude etc.

“ITU-R BT.656”

2004 Jun 29 15

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

handbook, full pagewidth

(dB)

−6

−12

−18

−24

−30

−36

−42

−48

−54

024

(1) SCBW = 1. (2) SCBW = 0.

(1) (2)

Fig.5 Chrominance transfer characteristic 1.

MBE737

6 8 10 12 14

f (MHz)

handbook, halfpage

(1) SCBW = 1. (2) SCBW = 0.

(dB)

−2

−4

−6

0 0.4 0.8 1.6

Fig.6 Chrominance transfer characteristic 2.

2004 Jun 29 16

MBE735

(1)

(2)

1.2

f (MHz)

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

handbook, full pagewidth

(dB)

−6

−12

−18

−24

−30

−36

−42

−48

−54

024

(1) CCRS1 = 0; CCRS0 = 1. (2) CCRS1 = 1; CCRS0 = 0. (3) CCRS1 = 1; CCRS0 = 1. (4) CCRS1 = 0; CCRS0 = 0.

MGD672

(4)

(3)

(2)

(1)

8101214

f (MHz)

(1) CCRS1 = 0; CCRS0 = 0.

Fig.7 Luminance transfer characteristic 1 (excluding scaler).

f (MHz)

MBE736

handbook, halfpage

(dB)

−1

−2

−3

−4

−5

(1)

Fig.8 Luminance transfer characteristic 2 (excluding scaler).

2004 Jun 29 17

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

handbook, full pagewidth

(dB)

−6

−12

−18

−24

−30

−36

−42

−48

−54

024

6 8 10 12 14

Fig.9 Luminance transfer characteristic in RGB (excluding scaler).

MGB708

f (MHz)

handbook, full pagewidth

(dB)

−6

−12

−18

−24

−30

−36

−42

−48

−54

024

6 8 10 12 14

Fig.10 Colour difference transfer characteristic in RGB (excluding scaler).

2004 Jun 29 18

MGB706

f (MHz)

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

8.1 Reset conditions

To activate the reset a pulse at least of 2 crystal clocks duration is required.

During reset (RESET = LOW) plus an extra 32 crystal clock periods, FSVGC, VSVGC, CBO, HSVGC and TTX_SRES are set to input mode and HSM_CSYNC and VSM are set to 3-state. A reset also forces the I2C-bus interface to abort any running bus transfer and sets it into receive condition.

After reset, the state of the I/Os and other functions is defined by the strapping pins until an I2C-bus access redefines the corresponding registers; see Table 2.

Table 2 Strapping pins

PIN TIED PRESET

FSVGC (pin G1) LOW NTSC M encoding, PIXCLK

ﬁts to 640 × 480 graphics input

HIGH PAL B/G encoding, PIXCLK

ﬁts to 640 × 480 graphics input

VSVGC (pin F1) LOW 4:2:2 Y-CB-CR graphics

input (format 0)

HIGH 4:4:4 RGB graphics input

(format 3)

CBO (pin G3) LOW input demultiplex phase:

LSB=LOW

HIGH input demultiplex phase:

LSB = HIGH

HSVGC (pin E3) LOW input demultiplex phase:

MSB = LOW

HIGH input demultiplex phase:

MSB = HIGH

TTXRQ_XCLKO2 (pin C4)

8.2 Input formatter

The input formatter converts all accepted PD input data formats, either RGB or Y-CB-CR, to a common internal RGB or Y-CB-CR data stream.

When double-edge clocking is used, the data is internally split into portions PPD1 and PPD2. The clock edge assignment must be set according to the I2C-bus control bits SLOT and EDGE for correct operation.

LOW slave (FSVGC, VSVGC and

HSVGC are inputs, internal colour bar is active)

HIGH master (FSVGC, VSVGC

and HSVGC are outputs)

If Y-CB-CR is being applied as a 27 Mbyte/s data stream, the output of the input formatter can be used directly to feed the video encoder block.

The horizontal upscaling is supported via the input formatter. According to the programming of the pixel clock dividers (see Section 8.10), it will upsample the data stream to 1 ×, 2 × or 4 × the input data rate. An optional interpolation filter is available. The clock domain transition is handled by a 4 entries wide FIFO which gets initialized every field or explicitly at request. A bypass for the FIFO is available, especially for high input data rates.

8.3 RGB LUT

The three 256-byte RAMs of this block can be addressed by three 8-bit wide signals, thus it can be used to build any transformation, e.g. a gamma correction for RGB signals. In the event that the indexed colour data is applied, the RAMs are addressed in parallel.

The LUTs can either be loaded by an I2C-bus write access or can be part of the pixel data input through the PD port. Inthelatter case, 256 × 3 bytes for the R, G and B LUT are expected at the beginning of the input video line, two lines before the line that has been defined as first active line, until the middle of the line immediately preceding the first active line. The first 3 bytes represent the first RGB LUT data, and so on.

8.4 Cursor insertion

A32× 32 dots cursor can be overlaid as an option; the bit map of the cursor can be uploaded by an I2C-bus write accesstospecific registers or in the pixel data input via the PDport.In the latter case the 256 bytes definingthecursor bit map (2 bits per pixel) are expected immediately following the last RGB LUT data in the line preceding the first active line.

The cursor bit map is set up as follows: each pixel occupies 2 bits. The meaning of these bits depends on the CMODE I2C-bus register as described in Table 5. Transparent means that the input pixels are passed through, the ‘cursor colours’ can be programmed in separate registers.

The bit map is stored with 4 pixels per byte, aligned to the least significant bit. So the first pixel is in bits 0 and 1, the next pixel in bits 3 and 4 and so on. The first index is the column, followed by the row; index 0,0 is the upper left corner.

2004 Jun 29 19

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

Table 3 Layout of a byte in the cursor bit map

D7 D6 D5 D4 D3 D2 D1 D0

pixel n + 3 pixel n + 2 pixel n + 1 pixel n D1 D0 D1 D0 D1 D0 D1 D0

For each direction, there are 2 registers controlling the position of the cursor, one controls the position of the ‘hot spot’, the other register controls the insertion position. Thehotspotisthe‘tip’ofthepointerarrow.It can have any position in the bit map. The actual position registers describe the co-ordinates of the hot spot. Again 0,0 is the upper left corner. While it is not possible to move the hot spot beyond the left respectively upper screen border thisisperfectly legal for the right respectively lower border. It should be noted that the cursor position is described relative to the input resolution.

Table 4 Cursor bit map

BYTE D7 D6 D5 D4 D3 D2 D1 D0

0row0

column 3

1row0

column 7

2row0

column 11

... ... ... ... ...

6row0

column 27 7row0

column 31

... ... ... ... ...

254 row 31

column 27 255 row 31

column 31

row 0 column 2

row 0 column 6

row 0 column 10

row 0 column 26

row 0 column 30

row 31 column 26

row 31 column 30

row 0 column 1

row 0 column 5

row 0 column 9

row 0 column 25

row 0 column 29

row 31 column 25

row 31 column 29

row 0 column 0

row 0 column 4

row 0 column 8

row 0 column 24

row 0 column 28

row 31 column 24

row 31 column 28

Table 5 Cursor modes

CURSOR PATTERN

00 second cursor colour second cursor colour 01 ﬁrst cursor colour ﬁrst cursor colour 10 transparent transparent 11 inverted input auxiliary cursor

8.5 RGB Y-CB-CR matrix

RGB input signals to be encoded to PAL or NTSC are converted to the Y-C colour difference signals are fed through low-pass filters and formatted to a ITU-R BT.601 like 4 : 2 : 2 data stream for further processing.

A gain adjust option corrects the level swing of the graphics world (black-to-white as 0 to 255) to the required range of 16 to 235.

The matrix and formatting blocks can be bypassed for Y-CB-CR graphics input.

Whenthe auxiliary VGA mode isselected,the output of the cursor insertion block is immediately directed to the triple DAC.

8.6 Horizontal scaler

The high quality horizontal scaler operates on the 4 : 2 : 2 data stream. Its control engines compensate the colour phase offset automatically.

The scaler starts processing after a programmable horizontal offset and continues with a number of input pixels. Each input pixel is a programmable fraction of the current output pixel (XINC/4096). A special case is XINC = 0, this sets the scaling factor to 1.

If the SAA7108AE; SAA7109AE input data is in accordance with another mode. In this event, XINC needs to be set to 2048 for a scaling factor of 1. With higher values, upscaling will occur.

CMODE = 0 CMODE = 1

“ITU-R BT.656”

CURSOR MODE

colour

colour space in this block. The

B-CR

, the scaler enters

2004 Jun 29 20

The phase resolution of the circuit is 12 bits, giving a maximum offset of 0.2 after 800 input pixels. Small FIFOs rearrange a 4 : 2 : 2 data stream at the scaler output.

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

8.7 Vertical scaler and anti-ﬂicker ﬁlter

The functions scaling, Anti-Flicker Filter (AFF) and re-interlacing are implemented in the vertical scaler.

Besides the entire input frame, it receives the first and last lines of the border to allow anti-flicker filtering.

Thecircuit generates the interlaced outputfieldsby scaling down the input frames with different offsets for odd and even fields. Increasing the YSKIP setting reduces the anti-flicker function. A YSKIP value of 4095switches it off; see Table 120.

An additional, programmable vertical filter supports the anti-flicker function. This filter is not available at upscaling factors of more than 2.

Theprogramming is similar tothehorizontal scaler. For the re-interlacing,the resolutions of the offset registers are not sufficient, so the weighting factors for the first lines can also be adjusted. YINC = 0 sets the scaling factor to 1; YIWGTO and YIWGTE must not be 0.

Due to the re-interlacing, the circuit can perform upscaling by a maximum factor of 2. The maximum factor depends onthe setting of the anti-flickerfunctionand can be derived from the formulae given in Section 8.20.

Anadditionalupscaling mode enables the upscaling factor to be increased to a maximum of 4 as it is required for the old VGA modes like 320 × 240.

8.10 Oscillator and Discrete Time Oscillator (DTO)

The master clock generation is realized as a 27 MHz crystal oscillator, which can operate with either a fundamental wave crystal or a 3rd-harmonic crystal.

The crystal clock supplies the DTO of the pixel clock synthesizer, the video encoder and the I2C-bus control block. It also usually supplies the triple DAC, with the exceptionoftheauxiliaryVGAmode,wherethetripleDAC is clocked by the pixel clock (PIXCLK).

The DTO can be programmed to synthesize all relevant pixel clock frequencies between circa 40 and 85 MHz. Two programmable dividers provide the actual clock to be used externally and internally. The dividers can be programmed to factors of 1, 2, 4 and 8. For the internal pixel clock, a divider ratio of 8 makes no sense and is thus forbidden.

The internal clock can be switched completely to the pixel clock input. In this event, the input FIFO is useless and will be bypassed.

The entire pixel clock generation can be locked to the vertical frequency. Both pixel clock dividers get re-initialized every field. Optionally, the DTO can be cleared with each V-sync. At proper programming, this will make the pixel clock frequency a precise multiple of the vertical and horizontal frequencies. This is required for some graphic controllers.

8.8 FIFO

The FIFO acts as a buffer to translate from the PIXCLK clock domain to the XTAL clock domain. The write clock is PIXCLK and the read clock is XTAL. An underflow or overflow condition can be detected via the I2C-bus read access.

In order to avoid underflows and overflows, it is essential that the frequency of the synthesized PIXCLK matches to the input graphics resolution and the desired scaling factor.

8.9 Border generator

When the graphics picture is to be displayed as interlaced PAL, NTSC, S-video or RGB on a TV screen, it is desired in many cases not to lose picture information due to the inherent overscanning of a TV set. The desired amount of underscan area, which is achieved through appropriate scaling in the vertical and horizontal direction, can be filled in the border generator with an arbitrary true colour tint.

2004 Jun 29 21

8.11 Low-pass Clock Generation Circuit (CGC)

This block reduces the phase jitter of the synthesized pixel clock. It works as a tracking filter for all relevant synthesized pixel clock frequencies.

8.12 Encoder

8.12.1 VIDEO PATH The encoder generates luminance and colour subcarrier

output signals from the Y, CBand CR baseband signals, which are suitable for use as CVBS or separate Y and C signals.

Input to the encoder, at 27 MHz clock (e.g. DVD), is either originated from computer graphics at pixel clock, fed throughthe FIFO and border generator,ora ITU-R BT.656 style signal.

Luminance is modified in gain and in offset (the offset is programmable in a certain range to enable different black level set-ups). A blanking level can be set after insertion of a fixed synchronization pulse tip level, in accordance with standard composite synchronization schemes.

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

Other manipulations used for the Macrovision anti-taping process, such as additional insertion of AGC super-white pulses (programmable in height), are supported by the SAA7108AE only.

To enable easy analog post filtering, luminance is interpolated from a 13.5 MHz data rate to a 27 MHz data rate, thereby providing luminance in a 10-bit resolution. The transfer characteristics of the luminance interpolation filter are illustrated in Figs 7 and 8. Appropriate transients at start/end of active video and for synchronization pulses are ensured.

Chrominance is modified in gain (programmable separately for CBand CR), and a standard dependent burst is inserted, before baseband colour signals are interpolated from a 6.75 MHz data rate to a 27 MHz data rate. One of the interpolation stages can be bypassed, thus providing a higher colour bandwidth, which can be usedforthe Y and C output. The transfer characteristics of the chrominance interpolation filter are illustrated in Figs 5 and 6.

The amplitude (beginning and ending) of the inserted burst, is programmable in a certain range that is suitable for standard signals and for special effects. After the succeeding quadrature modulator, colour is provided on the subcarrier in 10-bit resolution.

The numeric ratio between the Y and C outputs is in accordance with the standards.

8.12.3 VIDEO PROGRAMMING SYSTEM (VPS) ENCODING Five bytes of VPS information can be loaded via the

I2C-bus and will be encoded in the appropriate format into line 16.

8.12.4 CLOSED CAPTION ENCODER Using this circuit, data in accordance with the specification

of Closed Caption or extended data service, delivered by the control interface, can be encoded (line 21). Two dedicated pairs of bytes (two bytes per field), each pair preceded by run-in clocks and framing code, are possible.

Theactualline number in which data is to be encoded, can be modified in a certain range.

The data clock frequency is in accordance with the definition for NTSC M standard 32 times horizontal line frequency.

DataLOWat the output of the DACs correspondsto0 IRE, data HIGH at the output of the DACs corresponds to approximately 50 IRE.

Itis also possible to encode Closed Caption data for 50 Hz field frequencies at 32 times the horizontal line frequency.

8.12.5 ANTI-TAPING (SAA7108AE ONLY) For more information contact your nearest Philips

Semiconductors sales office.

8.12.2 TELETEXT INSERTION AND ENCODING (NOT

SIMULTANEOUSLY WITH REAL-TIME CONTROL)

Pin TTX_SRES receives a WST or NABTS teletext bitstream sampled at the crystal clock. At each rising edge of the output signal (TTXRQ) a single teletext bit has to be provided after a programmable delay at input pin TTX_SRES.

Phase variant interpolation is achieved on this bitstream in the internal teletext encoder, providing sufficient small phase jitter on the output text lines.

TTXRQ_XCLKO2 provides a fully programmable request signal to the teletext source, indicating the insertion period of bitstream at lines which can be selected independently for both fields. The internal insertion window for text is set to 360 (PAL WST), 296 (NTSC WST) or 288 (NABTS) teletext bits including clock run-in bits. The protocol and timing are illustrated in Fig.51.

Alternatively, this pin can be provided with a buffered crystal clock (XCLK) of 13.5 MHz.

2004 Jun 29 22

8.13 RGB processor

This block contains a dematrix in order to produce RED, GREEN and BLUE signals to be fed to a SCART plug.

Before Y, CBand CR signals are de-matrixed, individual gain adjustment for Y and colour difference signals and 2 times oversampling for luminance and 4 times oversampling for colour difference signals is performed. The transfer curves of luminance and colour difference components of RGB are illustrated in Figs 9 and 10.

8.14 Triple DAC

Both Y and C signals are converted from digital-to-analog in a 10-bit resolution at the output of the video encoder. Y and C signals are also combined into a 10-bit CVBS signal.

The CVBS output signal occurs with the same processing delay as the Y, C and optional RGB or CR-Y-CB outputs. Absolute amplitude at the input of the DAC for CVBS is reduced by15⁄16with respect to Y and C DACs to make maximum use of the conversion ranges.

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

RED, GREEN and BLUE signals are also converted from digital-to-analog, each providing a 10-bit resolution.

The reference currents of all three DACs can be adjusted individually in order to adapt for different output signals. In addition, all reference currents can be adjusted commonly to compensate for small tolerances of the on-chip band gap reference voltage.

Alternatively, all currents can be switched off to reduce power dissipation.

All three outputs can be used to sense for an external load (usually 75 Ω) during a pre-defined output. A flag in the I2C-bus status byte reflects whether a load is applied or not. An automatic sense mode can also be activated, which will immediately indicate any 75 Ω load at any of the three outputs at the dedicated interrupt pin TVD.

If the SAA7108AE; SAA7109AE is required to drive a second (auxiliary) VGA monitor or an HDTV set, the DACs receive the signal coming from the HD data path. In this event, the DACs are clocked at the incoming PIXCLKI instead of the 27 MHz crystal clock used in the video encoder.

8.15 HD data path

This data path enables the SAA7108AE; SAA7109AE to be used with VGA or HDTV monitors. It receives its data directly from the cursor generator and supports RGB and Y-PB-PR output formats (RGB not with Y-PB-PR input formats). No scaling is done in this mode.

Alternatively, the device can be triggered by auxiliary codes in a ITU-R BT.656 data stream via PD7 to PD0.

Only vertical frequencies of 50 and 60 Hz are allowed with the SAA7108AE; SAA7109AE. In slave mode, it is not possible to lock the encoders colour carrier to the line frequency with the PHRES bits.

In the (more common) master mode, the time base of the circuit is continuously free-running. The IC can output a frame sync at pin FSVGC, a vertical sync at pin VSVGC, a horizontal sync at pin HSVGC and a composite blanking signal at pin CBO. All of these signals are defined in the PIXCLK domain. The duration of HSVGC and VSVGC are fixed,they are 64 clocks forHSVGCand 1 line for VSVGC. The leading slopes are in phase and the polarities can be programmed.

The input line length can be programmed. The field length is always derived from the field length of the encoder and the pixel clock frequency that is being used.

CBO acts as a data request signal. The circuit accepts input data at a programmable number of clocks after CBO goes active. This signal is programmable and it is possible to adjust the following (see Figs 49 and 50):

• The horizontal offset

• The length of the active part of the line

• The distance from active start to first expected data

• The vertical offset separately for odd and even fields

• The number of lines per input field.

A gain adjustment either leads the full level swing to the digital-to-analog converters or reduces the amplitude by a factor of 0.69. This enables sync pulses to be added to the signal as it is required for display units that require signals with sync pulses, either regular or 3-level syncs.

8.16 Timing generator

The synchronization of the SAA7108AE; SAA7109AE is able to operate in two modes; slave mode and master mode.

In slave mode, the circuit accepts sync pulses on the bidirectional FSVGC (frame sync), VSVGC (vertical sync) and HSVGC (horizontal sync) pins: the polarities of the signals can be programmed. The frame sync signal is only necessary when the input signal is interlaced, in other casesit may be omitted. If theframesyncsignal is present, it is possible to derive the vertical and the horizontal phase from it by setting the HFS and VFS bits. HSVGC and VSVGC are not necessary in this case, so it is possible to switch the pins to output mode.

2004 Jun 29 23

In most cases, the vertical offsets for odd and even fields are equal. If they are not, then the even field will start later. The SAA7108AE; SAA7109AE will also request the first input lines in the even field, the total number of requested lines will increase by the difference of the offsets.

As stated above, the circuit can be programmed to accept the look-up and cursor data in the first 2 lines of each field. The timing generator provides normal data request pulses forthese lines; the duration is thesameasfor regular lines. The additional request pulses will be suppressed with LUTL set to logic 0; see Table 143. The other vertical timings do not change in this case, so the first active line can be number 2, counted from 0.

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

8.17 Pattern generator for HD sync pulses

The pattern generator provides an appropriate synchronization pattern for the video data path in auxiliary monitororHDTV mode, respectively. It providesmaximum flexibility in terms of raster generation for all interlaced and non-interlaced computer graphics or ATSC formats. The sync engine is capable of providing a combination of event-value pairs which can be used to insert certain values at specified times in the outgoing data stream. It can also be used to generate digital signals associated with time events. They can be used as digital horizontal andvertical synchronization signalsonpins HSM_CSYNC and VSM.

The picture position is adjustable through the programmable relationship between the sync pulses and the video contents.

The generation of embedded analog sync pulses is bound to a number of events which can be defined for a line. Several of these line timing definitions can exist in parallel. Forthe final sync raster composition a certain sequence of lineswithdifferent sync event properties has to be defined. The sequence specifies a series of line types and the number of occurrences of this specific line type. After the sequence has been completed, it restarts from the beginning. All pulse shapes are filtered internally in order to avoid ringing after analog post filters.

The sequence of the generated pulse stream must fit precisely to the incoming data stream in terms of the total number of pixels per line and lines per frame.

The sync engines flexibility is achieved by using a sequence of linked lists carrying the properties for the image, the lines as well as fractions of lines. Figure 11 illustrates the context between the various tables.

The first table serves as an array to hold the correct sequence of lines composing the synchronization raster. It cancontainupto16 entries. Each entry holds a 4-bit index tothe next table and a 10-bit counter value which specifies how often this particular line is invoked. If the necessary line count for a particular line exceeds the 10 bits, it has to use two table entries.

Each index of this table points to a particular line of the next table in the linked list. This table is called the line pattern array and each of the up to seven entries stores up tofour pairs of a duration in pixel clock cycles and an index to a value table. The table entries are used to define portions of a line representing a certain value for a certain number of clock cycles.

The value specified in this table is actually another 3-bit index into a value array which can hold up to eight 8-bit values. If bit 4 (MSB) of the index is logic 1, the value is inserted into the G or Y signal only; if bit 4 = 0, the associated value is inserted into all three signals.

Two additional bits of the entries in the value array (LSBs of the second byte) determine if the associated events appearasa digital pulse on the HSM_CSYNC and/or VSM outputs.

To ease the trigger set-up for the sync generation module, a set of registers is provided to set up the screen raster defined as width and height. A trigger position can be specified as an x, y co-ordinate within the overall dimensions of the screen raster. If the x, y counter matches the specified co-ordinates, a trigger pulse is generated which pre-loads the tables with their initial values.

Table 6 outlines an example on how to set up the sync tables for a 1080i HD raster.

Important note:

Due to a problem in the programming interface, writing to the line pattern array (address D2) might destroy the data of the line type array (address D1). A work around is to write the line pattern array data before writing the line type array. Reading of the arrays is possible but all address pointers must be initialized before the next write operation.

The4-bitindexinthelinecountarraypointstothelinetype array. It holds up to 15 entries where, index 0 is not used, index 1 points to the first entry, index 2 to the second entry of the line type array etc.

Each entry of the line type array can hold up to 8 index pointerstoanother table. These indices point to portions of alinepulsepattern:A line could be split up e.g. into a sync, a blank, and an active portion followed by another blank portion, occupying four entries in one table line.

2004 Jun 29 24

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

handbook, full pagewidth

4-bit line type index

line type pointer

8 + 2-bit value

VALUE ARRAY

8 entries

10-bit line count

LINE COUNT ARRAY

16 entries

3 3 3 3 3 3 3 3

LINE TYPE ARRAY

15 entries

3 3 3 3 3 3 3 3

event type pointer

10-bit duration

4-bit value index

10-bit duration

4-bit value index

line

count

pointer

LINE PATTERN ARRAY

7 entries

line pattern pointer

pattern pointer

10-bit duration

4-bit value index

10-bit duration

4-bit value index

MBL797

Fig.11 Context between the pattern generator tables for DH sync pulses.

2004 Jun 29 25

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

Table 6 Example for set-up of the sync tables

SEQUENCE COMMENT

Write to subaddress D0H

00 points to ﬁrst entry of line count array (index 0) 05 20 generate 5 lines of line type index 2 (remember, it is the second entry of the line type

array); will be the ﬁrst vertical raster pulse

01 40 generate 1 line of line type index 4; will be sync-black-sync-black sequence after the ﬁrst

vertical pulse 0E 60 generate 14 lines of line type index 6; will be the following lines with sync-black sequence 1C 12 generate 540 lines of line type index 1; will be lines with sync and active video 02 60 generate 2 lines of line type index 6; will be the following lines with sync-black sequence 01 50 generate 1 line of line type index 5; will be the following line (line 563) with

sync-black-sync-black-null sequence (null is equivalent to sync tip) 04 20 generate 4 lines of line type index 2; will be the second vertical raster pulse 01 30 generate 1 line of line type index 3; will be the following line with sync-null-sync-black

sequence 0F 60 generate 15 lines of line type index 6; will be the following lines with sync-black sequence 1C 12 generate 540 lines of line type index 1; will be lines with sync and active video 02 60 generate 2 lines of line type index 6; will be the following lines with sync-black sequence;

now, 1125 lines are deﬁned

Write to subaddress D2H (insertion is done into all three analog output signals)

00 points to ﬁrst entry of line pattern array (index 1) 6F 33 2B 30 00 00 00 00 880 × value(3) + 44 × value(3); (subtract 1 from real duration) 6F 43 2B 30 00 00 00 00 880 × value(4) + 44 × value(3) 3B 30 BF 03 BF 03 2B 30 60 × value(3) + 960 × value(0) + 960 × value(0) + 44 × value(3) 2B 10 2B 20 57 30 00 00 44 × value(1) + 44 × value(2) + 88 × value(3) 3B 30 BF 33 BF 33 2B 30 60 × value(3) + 960 × value(3) + 960 × value(3) + 44 × value(3)

Write to subaddress D1H

00 points to ﬁrst entry of line type array (index 1) 34 00 00 00 use pattern entries 4 and 3 in this sequence (for sync and active video) 24 24 00 00 use pattern entries 4, 2, 4 and 2 in this sequence (for 2 × sync-black-null-black) 24 14 00 00 use pattern entries 4, 2, 4 and 1 in this sequence (for sync-black-null-black-null) 14 14 00 00 use pattern entries 4, 1, 4 and 1 in this sequence (for sync-black-sync-black) 14 24 00 00 use pattern entries 4, 1, 4 and 2 in this sequence (for sync-black-sync-black-null) 54 00 00 00 use pattern entries 4 and 5 in this sequence (for sync-black)

2004 Jun 29 26

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

SEQUENCE COMMENT

Write to subaddress D3H (no signals are directed to pins HSM_CSYNC and VSM)

00 points to ﬁrst entry of value array (index 0) CC 00 black level, to be added during active video 80 00 sync level LOW (minimum output voltage) 0A 00 sync level HIGH (3-level sync) CC 00 black level (needed elsewhere) 80 00 null (identical with sync level LOW)

Write to subaddress DCH

0B insertion is active, gain for signal is adapted accordingly

8.18 I2C-bus interface

The I2C-bus interface is a standard slave transceiver, supporting 7-bit slave addresses and 400 kbits/s guaranteed transfer rate. It uses 8-bit subaddressing with an auto-increment function. All registers are read and write, except two read only status bytes.

The register bit map consists of an RGB Look-Up Table (LUT), a cursor bit map and control registers. The LUT containsthree banks of 256 bytes, where each RGB triplet isassigned to one address. Thus a write access needs the LUT address and three data bytes following subaddress FFH. For further write access auto-incrementing of the LUT address is performed. The cursor bit map access is similar to the LUT access but contains only a single byte per address.

The I2C-bus slave address is defined as 88H.

8.19 Power-down modes

In order to reduce the power consumption, the SAA7108AE; SAA7109AE supports 2 Power-down modes, accessible via the I2C-bus. The analog Power-down mode (DOWNA = 1) turns off the digital-to-analog converters and the pixel clock synthesizer. The digital down mode turns off all internal clocks and sets the digital outputs to LOW except the I2C-bus interface. The IC retains its programming and can still be accessed in this mode, but not all registers can be read from or written to. Reading or writing to the look-up tables, the cursor and the HD sync generator require a valid pixel clock. The typical supply current in full power-down is approximately 5 mA.

So in most cases, DOWNA and DOWND should be set to logic 1 simultaneously. If the EIDIV bit is logic 1, it should be set to logic 0 before power-down.

8.20 Programming the graphics acquisition scaler of the video encoder

The encoder section needs to provide a continuous data stream at its analog outputs as well as receive a continuous stream from its data source. Due to the fact that there is no frame memory isolating the data streams, restrictions apply to the input frame timings.

Input and output processing of the encoder section are only coupled through the vertical frequencies. In master mode, the encoder provides a vertical sync and an odd/even pulse to the input processing, in slave mode, the encoder receives them.

The parameters of the input field are mainly given by the memory capacity of the encoder section. The rule is that the scaler and thus the input processing needs to provide the video data in the same time frames as the encoder reads them. So the vertical active video times (and the vertical frequencies) need to be the same.

The second rule is that there has to be data in the buffer FIFO when the encoder enters the active video area. So the vertical offset in the input path needs to be a bit shorter than the offset of the encoder.

The following gives the set of equations required to program the IC for the most common application: A post processor in master mode with non-interlaced video input data.

Due to the fact that the analog Power-down mode turns off the pixel clock synthesizer, there are limitations in some applications. If there is no pixel clock, the IC is not able to set its outputs to LOW.

2004 Jun 29 27

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

Some variables are defined below:

• InPix: the number of active pixels per input line

• InPpl: the length of the entire input line in pixel clocks

• InLin: the number of active lines per input field/frame

• TPclk: the pixel clock period

• RiePclk: the ratio of internal to external pixel clock

• OutPix: the number of active pixels per output line

• OutLin: the number of active lines per output field

• TXclk: the encoder clock period (37.037 ns).

8.20.1 TV DISPLAY WINDOW At 60 Hz, the first visible pixel has the index 256,

710 pixels can be encoded; at 50 Hz, the index is 284, 702 pixels can be visible.

Theoutputlinesshouldbecentred on the screen. It should be noted that the encoder has 2 clocks per pixel; see Table 93.

ADWHS = 256 + 710 − OutPix (60 Hz); ADWHS = 284 + 702 − OutPix (50 Hz); ADWHE = ADWHS + OutPix × 2 (all frequencies)

For vertical, the procedure is the same. At 60 Hz, the first line with video information is number 19, 240 lines can be active. For 50 Hz, the numbers are 23 and 287; see Table 99.

240 OutLin–

FAL 19

FAL 23

LAL = FAL + OutLin (all frequencies) Most TV sets use overscan, and not all pixels respectively

lines are visible. There is no standard for the factor, it is highly recommended to make the number of output pixels and lines adjustable. A reasonable underscan factor is 10 %, giving approximately 640 output pixels per line.

8.20.2 INPUT FRAME AND PIXEL CLOCK The total number of pixel clocks per line and the input

horizontal offset need to be chosen next. The only constraint is that the horizontal blanking has at least 10 clock pulses.

The required pixel clock frequency can be determined in thefollowingway:Due to the limited internal FIFO size, the input path has to provide all pixels in the same time frame as the encoders vertical active time. The scaler also has to process the first and last border lines for the anti-flicker function.

--------------------------------2

287 OutLin–

--------------------------------2

(60 Hz);

(50 Hz);

TPclk

Thus: (60 Hz)

TPclk

---------------------------------------------------------------------------------------InPpl integer

and for the pixel clock generator

PCL

see Tables 102, 104 and 105. The divider PCLE should be set according to Table 104. PCLI may be set to a lower or the same value. Setting a lower value means that the internal pixel clock is higher and the data get sampled up. Thedifferencemaybe 1 at 640 × 480 pixels resolution and 2 at resolutions with 320 pixels per line as a rule of thumb. This allows horizontal upscaling by a maximum factor of 2 respectively 4 (this is the parameter RiePclk).

PCLI PCLE

The equations ensure that the last line of the field has the full number of clock cycles. Many graphic controllers require this. Note that the bit PCLSY needs to be set to ensure that there is not even a fraction of a clock left at the end of the field.

8.20.3 H XOFS can be chosen arbitrarily, the condition being that

XOFS + XPIX ≤ HLEN is fulfilled. Values given by the VESA display timings are preferred.

HLEN = InPpl × RiePclk − 1

XPIX

XINC

XINC needs to be rounded up, it needs to be set to 0 for a scaling factor of 1.

8.20.4 VERTICAL SCALER The input vertical offset can be taken from the assumption

thatthescalershould have just finished writing the first line when the encoder starts reading it:

YOFS

TXclk

-------------- TPclk

ORIZONTAL SCALER

InPix

------------ 2

OutPix

----------------- InPix

FAL 1716× TXclk×

----------------------------------------------------

InPpl TPclk×

FAL 1728× TXclk×

----------------------------------------------------

InPpl TPclk×

262.5 1716× TXclk×

----------------------------------------------------------------------------------------

InPpl integer

312.5 1728× TXclk×

20 PCLE+

×=

RiePclklog

–=

---------------------------2log

RiePclk×=

4096

×=

------------------- RiePclk

InLin 2+



----------------------



OutLin

InLin 2+



----------------------



OutLin

(all frequencies);

(all frequencies)

2.5–=

262.5×

(50 Hz)

312.5×

(60 Hz)

(50 Hz)

2004 Jun 29 28

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

In most cases the vertical offsets will be the same for odd and even fields. The results should be rounded down.

YPIX = InLin YSKIPdefinestheanti-flickerfunction.0 meansmaximum

flicker reduction but minimum vertical bandwidth, 4095 gives no flicker reduction and maximum bandwidth. Note that the maximum value for YINC is 4095. It might be necessary to reduce the value of YSKIP to fulfil this requirement.

YINC

YIWGTO

YIWGTE

OutLin

---------------------InLin 2+

YINC

------------- 2

YINC YSKIP–

------------------------------------- -

YSKIP



× 4096×=

-----------------



4095

2048+=

When YINC = 0 it sets the scaler to scaling factor 1. The initial weighting factors must not be set to 0 in this case. YIWGTE may go negative. In this event, YINC should be added and YOFSE incremented. This can be repeated as often as necessary to make YIWGTE positive.

Note that these equations assume that the input is non-interlaced while the output is interlaced. If the input is interlaced, the initial weighting factors need to be adapted to get the proper phase offsets in the output frame.

If vertical upscaling beyond the upper capabilities is required, the parameter YUPSC may be set to 1. This extends the maximum vertical scaling factor by a factor 2. Only the parameter YINC gets affected, it needs to be divided by 2 to get the same effect.

There are restrictions in this mode:

• The vertical filter YFILT is not available in this mode; the circuit will ignore this value

• The horizontal blanking needs to be long enough to transfer an output line between 2 memory locations. This is 710 internal pixel clocks

Ortheupscaling factor needs to be limited to 1.5andthe horizontal upscaling factor is also limited to less than ∼1.5. In this case a normal blanking length is sufficient.

For C and CVBS outputs, deviating amplitudes of the colour difference signals can be compensated for by independent gain control setting, while gain for luminance is set to predefined values, distinguishable for 7.5 IRE set-up or without set-up.

The RGB, respectively C

-Y-CB path features an

individual gain setting for luminance (GY) and colour difference signals (GCD). Reference levels are measured with a colour bar, 100 % white, 100 % amplitude and 100 % saturation.

The encoder section of the SAA7108AE; SAA7109AE has special input cells for the VGC port. They operate at a wider supply voltage range and have a strict input threshold at1/2V

DD(DVO)

. To achieve full speed of these cells, the EIDIV bit needs to be set to logic 1. In this case the impedance of these cells is approximately 6 kΩ. This may cause trouble with the bootstrapping pins of some graphic chips. So the power-on reset forces the bit to logic 0, the input impedance is regular in this mode.

Table 7

“ITU-R BT.601”

signal component levels

SIGNALS

(1)

COLOUR

YCBC

RGB

White 235 128 128 235 235 235 Yellow 210 16 146 235 235 16 Cyan 170 166 16 16 235 235 Green 145 54 34 16 235 16 Magenta 106 202 222 235 16 235 Red 81 90 240 235 16 16 Blue 41 240 110 16 16 235 Black 16 128 128 16 16 16

Note

1. Transformation:

a) R = Y + 1.3707 × (CR− 128) b) G=Y− 0.3365 × (CB− 128) − 0.6982 × (CR− 128) c) B = Y + 1.7324 × (CB− 128).

8.21 Input levels and formats

The SAA7108AE; SAA7109AE accepts digital Y, C

B,CR

or RGB data with levels (digital codes) in accordance with

“ITU-R BT.601”

. An optional gain adjustment also allows

data to be accepted with the full level swing of 0 to 255.

2004 Jun 29 29

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

Table 8 Usage of bits SLOTand EDGE

DATA SLOT CONTROL

(EXAMPLE FOR FORMAT 0)

SLOT EDGE 1st DATA 2nd DATA

0 0 at rising edge

G3/Y3

0 1 at falling edge

G3/Y3

1 0 at rising edge

R7/CR7

1 1 at falling edge

R7/CR7

Table 9 Pin assignment for input format 0

8 + 8 + 8-BIT 4 : 4 : 4 NON-INTERLACED

RGB/CB-Y-C

PD11 G3/Y3 R7/CR7 PD10 G2/Y2 R6/CR6 PD9 G1/Y1 R5/CR5 PD8 G0/Y0 R4/CR4 PD7 B7/CB7 R3/CR3 PD6 B6/CB6 R2/CR2 PD5 B5/CB5 R1/CR1 PD4 B4/CB4 R0/CR0 PD3 B3/CB3 G7/Y7 PD2 B2/CB2 G6/Y6 PD1 B1/CB1 G5/Y5 PD0 B0/CB0 G4/Y4

FALLING

CLOCK EDGE

at falling edge R7/CR7

at rising edge R7/CR7

at falling edge G3/Y3

at rising edge G3/Y3

RISING

CLOCK EDGE

Table 10 Pin assignment for input format 1

5 + 5 + 5-BIT 4 : 4 : 4 NON-INTERLACED RGB

PD7 G2 X PD6 G1 R4 PD5 G0 R3 PD4 B4 R2 PD3 B3 R1 PD2 B2 R0 PD1 B1 G4 PD0 B0 G3

Table 11 Pin assignment for input format 2

5 + 6 + 5-BIT 4 : 4 : 4 NON-INTERLACED RGB

PD7 G2 R4 PD6 G1 R3 PD5 G0 R2 PD4 B4 R1 PD3 B3 R0 PD2 B2 G5 PD1 B1 G4 PD0 B0 G3

Table 12 Pin assignment for input format 3

8 + 8 + 8-BIT 4:2:2 NON-INTERLACED CB-Y-C

FALLING

PD7 CB7(0) Y7(0) CR7(0) Y7(1) PD6 CB6(0) Y6(0) CR6(0) Y6(1) PD5 CB5(0) Y5(0) CR5(0) Y5(1) PD4 CB4(0) Y4(0) CR4(0) Y4(1) PD3 CB3(0) Y3(0) CR3(0) Y3(1) PD2 CB2(0) Y2(0) CR2(0) Y2(1) PD1 CB1(0) Y1(0) CR1(0) Y1(1) PD0 CB0(0) Y0(0) CR0(0) Y0(1)

CLOCK

EDGE

FALLING

CLOCK EDGE

FALLING

CLOCK EDGE

RISING

CLOCK

EDGE

FALLING

CLOCK

RISING

CLOCK EDGE

RISING

CLOCK EDGE

EDGE

n+1

RISING CLOCK

EDGE

n+1

2004 Jun 29 30

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