Philips SAA7108AE, SAA7109AE User Guide

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INTEGRATED CIRCUITS

DATA SH EET

SAA7108AE; SAA7109AE

HD-CODEC

Product speciﬁcation Supersedes data of 2003 Mar 26

2004 Jun 29

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

CONTENTS

1 FEATURES

1.1 Video decoder

1.2 Video scaler

1.3 Video encoder

1.4 Common features 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 ORDERING INFORMATION 5 QUICK REFERENCE DATA 6 BLOCK DIAGRAMS 7 PINNING 8 FUNCTIONAL DESCRIPTION OF DIGITAL

VIDEO ENCODER PART

8.1 Reset conditions

8.2 Input formatter

8.3 RGB LUT

8.4 Cursor insertion

8.5 RGB Y-CB-CR matrix

8.6 Horizontal scaler

8.7 Vertical scaler and anti-flicker filter

8.8 FIFO

8.9 Border generator

8.10 Oscillator and Discrete Time Oscillator (DTO)

8.11 Low-pass Clock Generation Circuit (CGC)

8.12 Encoder

8.13 RGB processor

8.14 Triple DAC

8.15 HD data path

8.16 Timing generator

8.17 Pattern generator for HD sync pulses

8.18 I2C-bus interface

8.19 Power-down modes

8.20 Programmingthegraphicsacquisitionscalerof the video encoder

8.21 Input levels and formats

9 FUNCTIONAL DESCRIPTION OF DIGITAL

VIDEO DECODER PART

9.1 Decoder

9.2 Decoder output formatter

9.3 Scaler

9.4 VBI data decoder and capture (subaddresses 40H to 7FH)

9.5 Image port output formatter (subaddresses 84H to 87H)

9.6 Audio clock generation (subaddresses 30H to 3FH)

10 INPUT/OUTPUT INTERFACES AND PORTS

OF DIGITAL VIDEO DECODER PART

10.1 Analog terminals

10.2 Audio clock signals

10.3 Clock and real-time synchronization signals

10.4 Video expansion port (X port)

10.5 Image port (I port)

10.6 Host port for 16-bit extension of video data I/O (H port)

10.7 Basic input and output timing diagrams for the I and X ports

11 BOUNDARY SCAN TEST

11.1 Initialization of boundary scan circuit

11.2 Device identification codes

12 LIMITING VALUES 13 THERMAL CHARACTERISTICS 14 CHARACTERISTICS OF THE DIGITAL

VIDEO ENCODER PART

15 CHARACTERISTICS OF THE DIGITAL

VIDEO DECODER PART

16 TIMING

16.1 Digital video encoder part

16.2 Digital video decoder part

17 APPLICATION INFORMATION

17.1 Reconstruction filter

17.2 Analog output voltages

17.3 Suggestions for a board layout

18 I2C-BUS DESCRIPTION

18.1 Digital video encoder part

18.2 Digital video decoder part

19 PROGRAMMING START SET-UP OF

DIGITAL VIDEO DECODER PART

19.1 Decoder part

19.2 Audio clock generation part

19.3 Data slicer and data type control part

19.4 Scaler and interfaces

20 PACKAGE OUTLINE 21 SOLDERING 22 DATA SHEET STATUS 23 DEFINITIONS 24 DISCLAIMERS 25 PURCHASE OF PHILIPS I2C COMPONENTS

2004 Jun 29 2

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

1 FEATURES

1.1 Video decoder

• Six analog inputs, internal analog source selectors, e.g. 6 × CVBS or (2 × Y/C and 2 × CVBS) or (1 × Y/C and 4 × CVBS)

• Two analog preprocessing channels in differential CMOS style for best S/N performance

• Fully programmable static gain or Automatic Gain Control (AGC) for the selected CVBS or Y/C channel

• Switchable white peak control

• Two built-in analog anti-aliasing filters

• Two 9-bit video CMOS Analog-to-Digital Converters

(ADCs), digitized CVBS or Y/C signals are available on the Image Port Data (IPD) port under I2C-bus control

• On-chip clock generator

• Line-locked system clock frequencies

• Digital PLL for horizontal sync processing and clock

generation, horizontal and vertical sync detection

• Requires only one crystal (either 24.576 MHz or

32.11 MHz) for all standards

• Automatic detection of 50 and 60 Hz field frequency, and automatic switching between PAL and NTSC standards

• Luminance and chrominance signal processing for PAL BGHI, PAL N, combination PAL N, PAL M, NTSC M, NTSC-Japan, NTSC N, NTSC 4.43 and SECAM

• User programmable luminance peaking or aperture correction

• Cross-colour reduction for NTSC by chrominance comb filtering

• PAL delay line for correcting PAL phase errors

• Brightness Contrast Saturation (BCS) and hue control

on-chip

• Two multi functional real-time output pins controlled by the I2C-bus

• Multi-standard VBI data slicer decoding World Standard Teletext (WST), North-American Broadcast Text System (NABTS), Closed Caption (CC), Wide Screen Signalling (WSS), Video Programming System (VPS), Vertical Interval Time Code (VITC) variants (EBU/SMPTE) etc.

• StandardITU 656 Y-CB-CR4:2:2format(8-bit)onIPD output bus

• Enhanced ITU 656 output format on IPD output bus containing:

– active video – raw CVBS data for INTERCAST applications

(27 MHz data rate)

– decoded VBI data

• Detection of copy protected input signals according to the Macrovision unauthorized recording of pay-TV or video tape signals.

1.2 Video scaler

• Both up and downscaling

• Conversion to square pixel format

• NTSC to 288 lines (video phone)

• Phaseaccuracybetterthan1/64pixelorline,horizontally

or vertically

• Independent scaling definitions for odd and even fields

• Anti-alias filter for horizontal scaling

• Provides output as:

– scaled active video – raw CVBS data for INTERCAST, WAVE-PHORE,

POPCON applications or general VBI data decoding (27 MHz or sample rate converted)

• Local video output for Y-CB-CR4 : 2 : 2 format (VMI, VIP, ZV).

(1) Macrovision is a trademark of the Macrovision Corporation.

(1)

standard. Can be used to prevent

2004 Jun 29 3

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

1.3 Video encoder

• Digital PAL/NTSC encoder with integrated high quality scaler and anti-flicker filter for TV output from a PC

• Supports Intel Digital Video Out (DVO) low voltage interfacing to graphics controller

• 27 MHz crystal-stable subcarrier generation

• Maximum graphics pixel clock 85 MHz at double edged

clocking, synthesized on-chip or from external source

• Programmable assignment of clock edge to bytes (in double edged mode)

• Synthesizable pixel clock (PIXCLK) with minimized outputjitter,canbeusedasreferenceclock for the VGC, as well

• PIXCLK output and bi-phase PIXCLK input (VGC clock loop-through possible)

• Hot-plug detection through dedicated interrupt pin

• Supported VGA resolutions for PAL or NTSC legacy

video output up to 1280 × 1024 graphics data at 60 or 50 Hz frame rate

• Supported VGA resolutions for HDTV output up to 1920 × 1080 interlaced graphics data at 60 or 50 Hz frame rate

• Three Digital-to-Analog Converters (DACs) for CVBS (BLUE, CB), VBS (GREEN, CVBS) and C (RED, CR)at 27 MHz sample rate (signals in parenthesis are optionally selected), all at 10-bit resolution

• Non-interlaced CB-Y-CR or RGB input at maximum 4:4:4 sampling

• Downscaling and upscaling from 50 to 400 %

• Optional interlaced CB-Y-CR input of Digital Versatile

Disk (DVD) signals

• Optional non-interlaced RGB output to drive second VGA monitor (bypass mode, maximum 85 MHz)

• 3 × 256 bytes RGB Look-Up Table (LUT)

• Support for hardware cursor

• HDTV up to 1920 × 1080 interlaced and 1280 × 720

progressive, including 3-level sync pulses

• Programmable border colour of underscan area

• Programmable 5 line anti-flicker filter

• On-chip 27 MHz crystal oscillator (3rd-harmonic or

fundamental 27 MHz crystal)

• Fast I2C-bus control port (400 kHz)

• Encoder can be master or slave

• Adjustable output levels for the DACs

• Programmable horizontal and vertical input

synchronization phase

• Programmable horizontal sync output phase

• Internal Colour Bar Generator (CBG)

• Optional support of various Vertical Blanking Interval

(VBI) data insertion

• Macrovision Pay-per-View copy protection system rev. 7.01, rev. 6.1 and rev. 1.03 (525p) as option; thisappliesto SAA7108AE only. The device is protected by USA patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. Use of the Macrovision anti-copy process in the device is licensed for non-commercial home use only. Reverse engineering or disassembly is prohibited. Please contact your nearest Philips Semiconductors sales office for more information.

1.4 Common features

• 5 V tolerant digital I/O ports

• I2C-bus controlled (full read-back ability by an external

controller, bit rate up to 400 kbits/s)

• Versatile power-save modes

• Boundary scan test circuit complies with the

1149.b1-1994”

encoder)

• Monolithic CMOS 3.3 V device

• BGA156 package

• Moisture Sensitive Level (MSL): e3.

2 APPLICATIONS

• Notebook (low-power consumption)

• PCMCIA card application

• AGP based graphics cards

• PC editing

• Image processing

• Video phone applications

• INTERCAST and PC teletext applications

• Security applications

• Hybrid satellite set-top boxes.

(separate ID codes for decoder and

“IEEE Std.

2004 Jun 29 4

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

3 GENERAL DESCRIPTION

The SAA7108AE; SAA7109AE is a new multi-standard video decoder and encoder chip, offering high quality video input and TV output processing as required by PC-99 specifications. It enables hardware manufacturers to implement versatile video functions on a significantly reduced printed-circuit board area at very competitive costs.

Separate pins for supply voltages as well as for I2C-bus control and boundary scan test have been provided for the video encoder and decoder sections to ensure both flexible handling and optimized noise behaviour.

Thevideo encoder is used to encode PC graphics data at maximum1280 × 1024resolution(optionally 1920 × 1080 interlaced) to PAL (50 Hz) or NTSC (60 Hz) video signals. A programmable scaler and anti-flicker filter (maximum 5 lines) ensures properly sized and flicker-free TV display as CVBS or S-video output.

Alternatively, the three Digital-to-Analog Converters (DACs) can output RGB signals together with a TTL composite sync to feed SCART connectors.

When the scaler/interlacer is bypassed, a second VGA monitor can be connected to the RGB outputs and separate H and V-syncs as well, thereby serving as an auxiliary monitor at maximum 1280 × 1024 resolution/60 Hz (PIXCLK < 85 MHz). Alternatively this port can provide Y, PB and PR signals for HDTV monitors.

The encoder section includes a sync/clock generator and on-chip DACs.

All inputs intended to interface to the host graphics controller are designed for low-voltage signals down to

1.1 V and up to 3.45 V.

The video decoder, a 9-bit video input processor, is a combination of a 2-channel analog pre-processing circuit including source selection, anti-aliasing filter and Analog-to-Digital Converter (ADC), automatic clamp and gain control, a Clock Generation Circuit (CGC), and a digital multi-standard decoder (PAL BGHI, PAL M, PAL N, combination PAL N, NTSC M, NTSC-Japan, NTSC N, NTSC 4.43 and SECAM).

The decoder includes a brightness, contrast and saturation control circuit, a multi-standard VBI data slicer and a 27 MHz VBI data bypass. The pure 3.3 V (5 V compatible) CMOS circuit SAA7108AE; SAA7109AE, consisting of an analog front-end and digital video decoder,a digital video encoder and analog back-end, is a highly integrated circuit especially designed for desktop video applications.

The decoder is based on the principle of line-locked clock decoding and is able to decode the colour of PAL, SECAM and NTSC signals into ITU-R BT.601 compatible colour component values.

The encoder can operate fully independently at its own variable pixel clock, transporting graphics input data, and at the line-locked, single crystal-stable video encoding clock.

As an option, it is possible to slave the video PAL/NTSC encodingto the video decoderclockwith the encoder FIFO acting as a buffer to decouple the line-locked decoder clock from the crystal-stable encoder clock.

4 ORDERING INFORMATION

TYPE

NUMBER

SAA7108AE BGA156 plastic ball grid array package; 156 balls; body 15 × 15 × 1.15 mm SOT472-1 SAA7109AE

2004 Jun 29 5

NAME DESCRIPTION VERSION

PACKAGE

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

5 QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

DDD

DDA

amb

A+D

Note

1. Power dissipation is extremely dependent on programming and selected application.

6 BLOCK DIAGRAMS

digital supply voltage 3.15 3.3 3.45 V analog supply voltage 3.15 3.3 3.45 V ambient temperature 0 − 70 °C analog and digital power dissipation note 1 −−1.7 W

handbook, full pagewidth

graphics input

analog

video input

digital video

CVBS, Y/C

Y-CB-CR/RGB

digital video

input and output

X port

ANALOG VIDEO

ACQUISITION AND

DEMODULATOR

VIDEO DECODER PART

VIDEO ENCODER PART

SCALER

AND

INTERLACER

SCALER

VIDEO

ENCODER

Fig.1 Simplified block diagram.

I port (IPD)

CVBS, Y/C RGB

MHB903

digital video output

analog video output

2004 Jun 29 6

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2004 Jun 29 7

C1, C2, B1, B2, A2, B4,

PD11 to

PD0

B3, A3, F3, H1, H2, H3

INPUT

FORMATTER

FIFO AND

UPSAMPLING

LUT

AND

CURSOR

RGB TO Y-CB-C

MATRIX

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

PIXCLKI

PIXCLKO

DECIMATOR

4 : 4 : 4 to 4 : 2 : 2

FIFO

PIXEL CLOCK

SYNTHESIZER

XTALIe

HORIZONTAL

SCALER

BORDER

GENERATOR

SAA7108AE SAA7109AE

CRYSTAL

OSCILLATOR

XTALOe

27 MHz

TTX_SRES

VERTICAL

SCALER

ENCODER

GENERATOR

G1A6A5 C3

VSVGC

FSVGC

VIDEO

OUTPUT

TIMING

F1 G3

HSVGC

CBO TTXRQ_XCLKO2

Fig.2 Block diagram (video encoder part).

ndbook, full pagewidth

SDAe

VERTICAL

FILTER

TRIPLE

DAC

I2C-BUS

CONTROL

SCLe

BLUE_CB_CVBS

GREEN_VBS_CVBS

RED_CR_C_CVBS

VSM

HSM_CSYNC

F12

TVD

E2 D2E3 C4

RESe

MBL785

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2004 Jun 29 8

]

XPD[7:0

XRH

K2, K3, L1 to L3 M1, M2, N1

X PORT I/O FORMATTING

K14

ASCLK

AMXCLK

J12

DDXd

J13

XRV

SSXd

XTRI

XRDY

FIR-PREFILTER

PRESCALER

SCALER BCS

GENERAL PURPOSE

D11, F11, J4, J11, L4, L11

DDId

RESd

XTOUTd

XTALId

XTALOd

AI11 AI12 AI21 AI22 AI23 AI24

AOUT

AI1D AI2D

AGND

M12 N14 P4 P2 P3

P13 P11 P10 P9 P7 P6 M10

P12 P8

N10

LLC2

LLC

M14

CLOCK GENERATION

POWER-ON CONTROL

ANALOG

DUAL

ADC

TRSTd

RTCO

(1)

L14

L13

AND

BOUNDARY

SCAN

TEST

TCLKd

TMSd

RTS0

TDId

XCLK

RTS1

K13

L10

DIGITAL

DECODER

WITH

ADAPTIVE

COMB

FILTER

AMCLK

TDOd

XDQ

EXPANSION PORT PIN MAPPING I/O CONTROL I2C-BUSREAL-TIME OUTPUT

AUDIO

CLOCK

GENERATION

K12

ALRCLK

(1)

, full pagewidth

HPD[7:0

PROGRAMMING

AND

VBI DATA SLICER

D10, G11, L7, L9

DDEd

A13, D12, C12, B12, A12, C11, B11, A11

chrominance of 16-bit input

ARRAY

EVENT CONTROLLER

BUFFER

DDAd

]

LINE FIFO

M8, M9, N11

VERTICAL

SCALING

E11, K4, K11

SSId

SDAd

A/B

MUX

SSEd

L12

H4, H11, L6, M13

SCLd

M11

HORIZONTAL

FINE

(PHASE)

SCALING

M7, N7 to N9, N12, N13

SSAd

TEST5

TEST4

TEST3

SAA7108AE SAA7109AE

VIDEO

FIFO

TEXT

FIFO

VIDEO/TEXT

ARBITER

TEST2

to 8(16) MUX

TEST1

TEST0

C10

H13

B10

E14, D14, C14, B14, E13, D13, C13, B13

IMAGE PORT PIN MAPPING

MBL791

H14 G12

F13 F14

G13

H12

J14

G14

IPD[7:0 IDQ IGPH IGPV IGP0 IGP1

ICLK

ITRDY ITRI

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

]

(1) The pins RTCO and ALRCLK are used for configuration of the I2C-bus interface

and the definition of the crystal oscillator frequency at RESET (pin strapping).

Fig.3 Block diagram (video decoder part).

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

7 PINNING

SYMBOL PIN TYPE

(1)

DESCRIPTION

PD7 A2 I MSB of encoder input bus with CB-Y-CR 4 : 2 : 2; see Tables 9 to 15 for pin

assignment

PD4 A3 I MSB − 3 of encoder input bus with CB-Y-CR 4 : 2 : 2; see Tables 9 to 15 for

pin assignment

TRSTe A4 I/pu test reset input for Boundary Scan Test (BST) (encoder); active LOW; with

internal pull-up; notes 2 and 3 XTALIe A5 I 27 MHz crystal input (encoder) XTALOe A6 O 27 MHz crystal output (encoder) DUMP A7 O DAC reference pin (encoder), 12 Ω resistor connected to V V

SSXe

A8 S ground for oscillator (encoder) RSET A9 O DAC reference pin (encoder), 1 kΩ resistor connected to V V

DDAe

A10 S 3.3 V analog supply voltage (encoder)

SSAe

HPD0 A11 I/O MSB − 7 of Host Port Data (HPD) output bus HPD3 A12 I/O MSB − 4 of HPD output bus HPD7 A13 I/O MSB of HPD output bus PD9 B1 I see Tables 9, 14 and 15 for pin assignment with different encoder input

formats

PD8 B2 I see Tables 9, 14 and 15 for pin assignment with different encoder input

formats

PD5 B3 I MSB − 2 of encoder input bus with CB-Y-CR 4 : 2 : 2; see Tables 9 to 15 for

pin assignment

PD6 B4 I MSB − 1 of encoder input bus with CB-Y-CR 4 : 2 : 2; see Tables 9 to 15 for

pin assignment TDIe B5 I/pu test data input for BST (encoder); note 4 V

DDAe

B6 S 3.3 V analog supply voltage (encoder) DUMP B7 O DAC reference pin (encoder); connected to A7 V V

SSAe DDAe

B8 S analog ground (encoder)

B9 S 3.3 V analog supply voltage (encoder) TEST1 B10 I scan test input 1, do not connect HPD1 B11 I/O MSB − 6 of HPD output bus HPD4 B12 I/O MSB − 3 of HPD output bus IPD0 B13 O MSB − 7 of IPD output bus IPD4 B14 O MSB − 3 of Image Port Data (IPD) output bus PD11 C1 I see Tables 9, 14 and 15 for pin assignment with different encoder input

formats

PD10 C2 I see Tables 9, 14 and 15 for pin assignment with different encoder input

formats TTX_SRES C3 I teletext input or sync reset input (encoder) TTXRQ_XCLKO2 C4 O teletext request output or 13.5 MHz clock output of the crystal oscillator

(encoder) V

SSIe

C5 S digital ground core (encoder)

BLUE_CB_CVBS C6 O BLUE or CB or CVBS output

2004 Jun 29 9

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

SYMBOL PIN TYPE

(1)

DESCRIPTION

GREEN_VBS_CVBS C7 O GREEN or VBS or CVBS output RED_CR_C_CVBS C8 O RED or CR or C or CVBS output V

DDAe

C9 S 3.3 V analog supply voltage (encoder) TEST2 C10 I scan test input 2, do not connect HPD2 C11 I/O MSB − 5 of HPD output bus HPD5 C12 I/O MSB − 2 of HPD output bus IPD1 C13 O MSB − 6 of IPD output bus IPD5 C14 O MSB − 2 of IPD output bus TDOe D1 O test data output for BST (encoder); note4 RESe D2 I reset input (encoder); active LOW TMSe D3 I/pu test mode select input for BST (encoder); note 4 V

DDIEe

SSIe

DDXe

D4 S 3.3 V digital supply voltage for core and peripheral cells (encoder)

D5 S digital ground core (encoder)

D6 S 3.3 V supply voltage for oscillator (encoder) VSM D7 O vertical synchronization output to VGA monitor (non-interlaced) HSM_CSYNC D8 O horizontal synchronization output to VGA monitor (non-interlaced) or

composite sync for RGB-SCART V V V

DDAe DDEd DDId

D9 S 3.3 V analog supply voltage (encoder) D10 S 3.3 V digital supply voltage for peripheral cells (decoder) D11 S 3.3 V digital supply voltage for core (decoder)

HPD6 D12 I/O MSB − 1 of HPD output bus IPD2 D13 O MSB − 5 of IPD output bus IPD6 D14 O MSB − 1 of IPD output bus TCKe E1 I/pu test clock input for BST (encoder); note 4 SCLe E2 I I2C-bus serial clock input (encoder) HSVGC E3 I/O horizontal synchronization output to Video Graphics Controller (VGC)

(optional input) V V

SSEe SSId

E4 S digital ground peripheral cells (encoder)

E11 S digital ground core (decoder) n.c. E12 − not connected IPD3 E13 O MSB − 4 of IPD output bus IPD7 E14 O MSB of IPD output bus VSVGC F1 I/O vertical synchronization output to VGC (optional input) PIXCLKI F2 I pixel clock input (looped through) PD3 F3 I MSB − 4 of encoder input bus with CB-Y-CR 4 : 2 : 2; see Tables 9 to 15 for

pin assignment

DD(DVO)

DDId

F4 S digital supply voltage for DVO cells

F11 S 3.3 V digital supply voltage for core (decoder) TVD F12 O TV Detector; hot-plug interrupt pin, HIGH if TV is connected IGPV F13 O multi-purpose vertical reference output with IPD output bus IGP0 F14 O general purpose output signal 0 with IPD output bus

2004 Jun 29 10

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

SYMBOL PIN TYPE

(1)

DESCRIPTION

FSVGC G1 I/O frame synchronization output to VGC (optional input) SDAe G2 I/O I2C-bus serial data input/output (encoder) CBO G3 O composite blanking output to VGC; active LOW PIXCLKO G4 O pixel clock output to VGC V

DDEd

G11 S 3.3 V digital supply voltage for peripheral cells (decoder) IGPH G12 O multi-purpose horizontal reference output with IPD output bus IGP1 G13 O general purpose output signal 1 with IPD output bus ITRI G14 I/(O) programmable control signals for IPD output bus PD2 H1 I MSB − 5 of encoder input bus with CB-Y-CR 4 : 2 : 2; see Tables 9 to 15 for

pin assignment

PD1 H2 I MSB − 6 of encoder input bus with CB-Y-CR 4 : 2 : 2; see Tables 9 to 15 for

pin assignment

PD0 H3 I MSB − 7 of encoder input bus with CB-Y-CR 4 : 2 : 2; see Tables 9 to 15 for

pin assignment V V

SSEd SSEd

H4 S digital ground for peripheral cells (decoder)

H11 S digital ground for peripheral cells (decoder) ICLK H12 I/O clock for IPD output bus (optional clock input) TEST0 H13 O scan test output, do not connect IDQ H14 O data qualiﬁer for IPD output bus TEST4 J1 O scan test output, do not connect TEST5 J2 I scan test input, do not connect TEST3 J3 I scan test input, do not connect V V

DDId DDId

J4 S 3.3 V digital supply voltage for core (decoder)

J11 S 3.3 V digital supply voltage for core (decoder) AMXCLK J12 I audio master external clock input ALRCLK J13 (I/)O audio left/right clock output; can be strapped to supply via a 3.3 kΩ resistor to

indicate that the default 24.576 MHz crystal (ALRCLK = 0; internal pull-down)

has been replaced by a 32.110 MHz crystal (ALRCLK = 1); notes 5 and 6 ITRDY J14 I target ready input for IPD output bus XTRI K1 I control signal for all X port pins XPD7 K2 I/O MSB of XPD bus XPD6 K3 I/O MSB − 1 of XPD bus V V

SSId SSId

K4 S digital ground core (decoder)

K11 S digital ground core (decoder) AMCLK K12 O audio master clock output, must be less than 50 % of crystal clock RTS0 K13 O real-time status or sync information line 0 ASCLK K14 O audio serial clock output XPD5 L1 I/O MSB − 2 of XPD bus XPD4 L2 I/O MSB − 3 of XPD bus XPD3 L3 I/O MSB − 4 of XPD bus V

DDId

L4 S 3.3 V digital supply voltage for core (decoder)

XRV L5 I/O vertical reference for XPD bus

2004 Jun 29 11

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

SYMBOL PIN TYPE

SSEd

DDEd

DDXd

DDEd

L6 S digital ground for peripheral cells (decoder) L7 S 3.3 V digital supply voltage for peripheral cells (decoder) L8 S 3.3 V supply voltage for oscillator (decoder) L9 S 3.3 V digital supply voltage for peripheral cells (decoder)

(1)

DESCRIPTION

RTS1 L10 O real-time status or sync information line 1 V

DDId

L11 S 3.3 V digital supply voltage for core (decoder) SDAd L12 I/O I2C-bus serial data input/output (decoder) RTCO L13 (I/)O real-time control output; contains information about actual system clock

frequency, ﬁeld rate, odd/even sequence, decoder status, subcarrier frequency and phase and PAL sequence (see external document

Functional Description”

, available on request); the RTCO pin is enabled via

“RTC

I2C-bus bit RTCE; see notes 5 and 7 and Table 150 LLC2 L14 O line-locked1⁄2clock output (13.5 MHz nominal) XPD2 M1 I/O MSB − 5 of XPD bus XPD1 M2 I/O MSB − 6 of XPD bus XCLK M3 I/O clock for XPD bus XDQ M4 I/O data qualiﬁer for XPD bus TMSd M5 I/pu test mode select input for BST (decoder); note 4 TCKd M6 I/pu test clock input for BST (decoder); note 4 V V V

SSAd DDAd DDAd

M7 S analog ground (decoder) M8 S 3.3 V analog supply voltage (decoder)

M9 S 3.3 V analog supply voltage (decoder) AOUT M10 O analog test output (do not connect) SCLd M11 I I2C-bus serial clock input (decoder) RESd M12 O reset output signal; active LOW (decoder) V

SSEd

M13 S digital ground for peripheral cells (decoder) LLC M14 O line-locked clock output (27 MHz nominal) XPD0 N1 I/O MSB − 7 of XPD bus XRH N2 I/O horizontal reference for XPD bus XRDY N3 O data input ready for XPD bus TRSTd N4 I/pu test reset input for BST (decoder); active LOW; with internal pull-up;

notes 2 and 3 TDOd N5 O test data output for BST (decoder); note4 TDId N6 I/pu test data input for BST (decoder); note 4 V V V

SSAd SSAd SSAd

N7 S analog ground (decoder) N8 S analog ground (decoder)

N9 S analog ground (decoder) AGND N10 S analog ground (decoder) connected to substrate V V V

DDAd SSAd SSAd

N11 S 3.3 V analog supply voltage (decoder) N12 S analog ground (decoder) N13 S analog ground (decoder)

CE N14 I chip enable or reset input (with internal pull-up)

2004 Jun 29 12

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

SYMBOL PIN TYPE

(1)

DESCRIPTION

XTALId P2 I 27 MHz crystal input (decoder) XTALOd P3 O 27 MHz crystal output (decoder) XTOUTd P4 O crystal oscillator output signal (decoder); auxiliary signal V

SSXd

P5 S ground for crystal oscillator (decoder) AI24 P6 I analog input 24 AI23 P7 I analog input 23 AI2D P8 I differential analog input for channel 2; connect to ground via a capacitor AI22 P9 I analog input 22 AI21 P10 I analog input 21 AI12 P11 I analog input 12 AI1D P12 I differential analog input for channel 1; connect to ground via a capacitor AI11 P13 I analog input 11

Notes

1. Pin type: I = input, O = output, S = supply, pu = pull-up.

2. For board design without boundary scan implementation connect TRSTe and TRSTd to ground.

3. This pin provides easy initialization of the Boundary Scan Test (BST) circuit. TRSTe and TRSTd can be used to force the Test Access Port (TAP) controller to the TEST_LOGIC_RESET state (normal operation) at once.

4. In accordance with the

“IEEE1149.1”

standard the pads TDIe (TDId), TMSe (TMSd), TCKe (TCKd) and TRSTe

(TRSTd) are input pads with an internal pull-up resistor and TDOe (TDOd) is a 3-state output pad.

5. Pin strapping is done by connecting the pin to supply via a 3.3 kΩ resistor. During the power-up reset sequence the corresponding pins are switched to input mode to read the strapping level. For the default setting no strapping resistor is necessary (internal pull-down).

6. Pin ALRCLK: 0 = 24.576 MHz crystal (default); 1 = 32.110 MHz crystal.

7. Pin RTCO: operates as I2C-bus slave address pin; RTCO = 0 slave address 42H/43H (default); RTCO = 1 slave address 40H/41H.

handbook, halfpage

P N M

L K

J H G

E D C B A

234567891011121314

SAA7108AE SAA7109AE

Fig.4 Pin configuration.

2004 Jun 29 13

MBL788

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2004 Jun 29 14

Table 1 Pin assignment (top view)

123456 7 8 91011121314

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

A PD7 PD4 TRSTe XTALIe XTALOe DUMP V

B PD9 PD8 PD5 PD6 TDIe V

C PD11 PD10 TTX_

SRES

D TDOe RESe TMSe V

E TCKe SCLe HSVGC V

F VSVGC PIXCLKI PD3 V

TTXRQ_ XCLKO2

DDIEe

SSEe

DD(DVO)

SSIe

BLUE_

CB_CVBS

DDAe

DDXe

DUMP V

GREEN_

RED_CR_C_

VBS_CVBS

VSM HSM_CSYNC V

SSXe

SSAe

CVBS

RSET V

DDAe

DDAeVDDEdVDDId

DDAe

TEST1 HPD1 HPD4 IPD0 IPD4

TEST2 HPD2 HPD5 IPD1 IPD5

G FSVGC SDAe CBO PIXCLKO V

H PD2 PD1 PD0 V

J TEST4 TEST5 TEST3 V

K XTRI XPD7 XPD6 V

SSEd

DDId

SSId

HPD0 HPD3 HPD7

HPD6 IPD2 IPD6

SSId

DDId

DDEd

SSEd

DDId

SSId

n.c. IPD3 IPD7

TVD IGPV IGP0

IGPH IGP1 ITRI

ICLK TEST0 IDQ

AMXCLK ALRCLK ITRDY

AMCLK RTS0 ASCLK

L XPD5 XPD4 XPD3 V

DDId

XRV V

SSEd

M XPD2 XPD1 XCLK XDQ TMSd TCKd V

N XPD0 XRH XRDY TRSTd TDOd TDId V

P XTALId XTALOd XTOUTd V

SSXd

AI24 AI23 AI2D AI22 AI21 AI12 AI1D AI11

DDEd

SSAd

DDXd

DDAd

SSAd

RTS1 V

DDEd

AOUT SCLd RESd V

DDAd

AGND V

SSAd

DDId

DDAd

SDAd RTCO LLC2

LLC

SSAd

SSEd

SSAd

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

8 FUNCTIONAL DESCRIPTION OF DIGITAL VIDEO

ENCODER PART

The digital video encoder encodes digital luminance and colour difference signals (CB-Y-CR) or digital RGB signals into analog CVBS, S-video and, optionally, RGB or CR-Y-CB signals. NTSC M, PAL B/G and sub-standards are supported.

The SAA7108AE; SAA7109AE can be directly connected to a PC video graphics controller with a maximum resolution of 1280 × 1024 (progressive) or 1920 × 1080 (interlaced) at a 50 or 60 Hz frame rate. A programmable scalerscalesthecomputergraphics picture so that it will fit into a standard TV screen with an adjustable underscan area.Non-interlaced-to-interlaced conversion is optimized with an adjustable anti-flicker filter for a flicker-free display at a very high sharpness.

Besides the most common 16-bit 4 :2:2 CB-Y-CR input format (using 8 pins with double edge clocking), other CB-Y-CR and RGB formats are also supported; see Tables 9 to 15.

Acomplete3 × 256 bytes Look-Up Table (LUT), which can be used, for example, as a separate gamma corrector, is locatedintheRGBdomain;itcan be loaded either through the video input port PD (Pixel Data) or via the I2C-bus.

The SAA7108AE; SAA7109AE supports a 32 × 32 × 2-bit hardware cursor, the pattern of which can also be loaded through the video input port or via the I2C-bus.

It is also possible to encode interlaced 4 :2:2 video signals such as PC-DVD; for that the anti-flicker filter, and in most cases the scaler, will simply be bypassed.

Besides the applications for video output, the SAA7108AE;SAA7109AE can alsobeused for generating a kind of auxiliary VGA output, when the RGB non-interlacedinputsignalisfed to the DACs. This may be of interest for example, when the graphics controller provides a second graphics window at its video output port.

The basic encoder function consists of subcarrier generation, colour modulation and insertion of synchronization signals at a crystal-stable clock rate of

13.5 MHz (independent of the actual pixel clock used at the input side), corresponding to an internal 4 :2:2 bandwidth in the luminance/colour difference domain. Luminance and chrominance signals are filtered in accordance with the standard requirements of and

“ITU-R BT.470-3”

“RS-170-A”

For ease of analog post filtering the signals are twice oversampled to 27 MHz before digital-to-analog conversion.

The total filter transfer characteristics (scaler and anti-flicker filter are not taken into account) are illustrated in Figs 5 to 10. All three DACs are realized with full 10-bit resolution. The CR-Y-CB to RGB dematrix can be bypassed (optionally) in order to provide the upsampled CR-Y-CB input signals.

The8-bit multiplexed CB-Y-CRformatsare (D1 format) compatible, but the SAV and EAV codes can be decoded optionally, when the device is operated in slave mode. For assignment of the input data to the rising or falling clock edge see Tables 9 to 15.

In order to display interlaced RGB signals through a euro-connector TV set, a separate digital composite sync signal (pin HSM_CSYNC) can be generated; it can be advanced up to 31 periods of the 27 MHz crystal clock in order to be adapted to the RGB processing of a TV set.

The SAA7108AE; SAA7109AE synthesizes all necessary internal signals, colour subcarrier frequency and synchronization signals from that clock.

It is also possible to connect pin RTCO of the decoder section to pin RTCI of the encoder section. Thus, information containing actual subcarrier frequency, PAL-ID etc. is available in case the line-locked clock of the decoder section is used for re-encoding of the encoder section.

Wide screen signalling data can be loaded via the I2C-bus and is inserted into line 23 for standards using a 50 Hz field rate.

VPS data for program dependent automatic start and stop of such featured VCRs is loadable via the I2C-bus.

The IC also contains Closed Caption and extended data servicesencoding(line 21), and supports teletext insertion forthe appropriate bit stream formatata 27 MHz clock rate (see Fig.51). It is also possible to load data for the copy generation management system into line 20 of every field (525/60 line counting).

A number of possibilities are provided for setting different video parameters such as:

• Black and blanking level control

• Colour subcarrier frequency

• Variable burst amplitude etc.

“ITU-R BT.656”

2004 Jun 29 15

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

handbook, full pagewidth

(dB)

−6

−12

−18

−24

−30

−36

−42

−48

−54

024

(1) SCBW = 1. (2) SCBW = 0.

(1) (2)

Fig.5 Chrominance transfer characteristic 1.

MBE737

6 8 10 12 14

f (MHz)

handbook, halfpage

(1) SCBW = 1. (2) SCBW = 0.

(dB)

−2

−4

−6

0 0.4 0.8 1.6

Fig.6 Chrominance transfer characteristic 2.

2004 Jun 29 16

MBE735

(1)

(2)

1.2

f (MHz)

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

handbook, full pagewidth

(dB)

−6

−12

−18

−24

−30

−36

−42

−48

−54

024

(1) CCRS1 = 0; CCRS0 = 1. (2) CCRS1 = 1; CCRS0 = 0. (3) CCRS1 = 1; CCRS0 = 1. (4) CCRS1 = 0; CCRS0 = 0.

MGD672

(4)

(3)

(2)

(1)

8101214

f (MHz)

(1) CCRS1 = 0; CCRS0 = 0.

Fig.7 Luminance transfer characteristic 1 (excluding scaler).

f (MHz)

MBE736

handbook, halfpage

(dB)

−1

−2

−3

−4

−5

(1)

Fig.8 Luminance transfer characteristic 2 (excluding scaler).

2004 Jun 29 17

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

handbook, full pagewidth

(dB)

−6

−12

−18

−24

−30

−36

−42

−48

−54

024

6 8 10 12 14

Fig.9 Luminance transfer characteristic in RGB (excluding scaler).

MGB708

f (MHz)

handbook, full pagewidth

(dB)

−6

−12

−18

−24

−30

−36

−42

−48

−54

024

6 8 10 12 14

Fig.10 Colour difference transfer characteristic in RGB (excluding scaler).

2004 Jun 29 18

MGB706

f (MHz)

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

8.1 Reset conditions

To activate the reset a pulse at least of 2 crystal clocks duration is required.

During reset (RESET = LOW) plus an extra 32 crystal clock periods, FSVGC, VSVGC, CBO, HSVGC and TTX_SRES are set to input mode and HSM_CSYNC and VSM are set to 3-state. A reset also forces the I2C-bus interface to abort any running bus transfer and sets it into receive condition.

After reset, the state of the I/Os and other functions is defined by the strapping pins until an I2C-bus access redefines the corresponding registers; see Table 2.

Table 2 Strapping pins

PIN TIED PRESET

FSVGC (pin G1) LOW NTSC M encoding, PIXCLK

ﬁts to 640 × 480 graphics input

HIGH PAL B/G encoding, PIXCLK

ﬁts to 640 × 480 graphics input

VSVGC (pin F1) LOW 4:2:2 Y-CB-CR graphics

input (format 0)

HIGH 4:4:4 RGB graphics input

(format 3)

CBO (pin G3) LOW input demultiplex phase:

LSB=LOW

HIGH input demultiplex phase:

LSB = HIGH

HSVGC (pin E3) LOW input demultiplex phase:

MSB = LOW

HIGH input demultiplex phase:

MSB = HIGH

TTXRQ_XCLKO2 (pin C4)

8.2 Input formatter

The input formatter converts all accepted PD input data formats, either RGB or Y-CB-CR, to a common internal RGB or Y-CB-CR data stream.

When double-edge clocking is used, the data is internally split into portions PPD1 and PPD2. The clock edge assignment must be set according to the I2C-bus control bits SLOT and EDGE for correct operation.

LOW slave (FSVGC, VSVGC and

HSVGC are inputs, internal colour bar is active)

HIGH master (FSVGC, VSVGC

and HSVGC are outputs)

If Y-CB-CR is being applied as a 27 Mbyte/s data stream, the output of the input formatter can be used directly to feed the video encoder block.

The horizontal upscaling is supported via the input formatter. According to the programming of the pixel clock dividers (see Section 8.10), it will upsample the data stream to 1 ×, 2 × or 4 × the input data rate. An optional interpolation filter is available. The clock domain transition is handled by a 4 entries wide FIFO which gets initialized every field or explicitly at request. A bypass for the FIFO is available, especially for high input data rates.

8.3 RGB LUT

The three 256-byte RAMs of this block can be addressed by three 8-bit wide signals, thus it can be used to build any transformation, e.g. a gamma correction for RGB signals. In the event that the indexed colour data is applied, the RAMs are addressed in parallel.

The LUTs can either be loaded by an I2C-bus write access or can be part of the pixel data input through the PD port. Inthelatter case, 256 × 3 bytes for the R, G and B LUT are expected at the beginning of the input video line, two lines before the line that has been defined as first active line, until the middle of the line immediately preceding the first active line. The first 3 bytes represent the first RGB LUT data, and so on.

8.4 Cursor insertion

A32× 32 dots cursor can be overlaid as an option; the bit map of the cursor can be uploaded by an I2C-bus write accesstospecific registers or in the pixel data input via the PDport.In the latter case the 256 bytes definingthecursor bit map (2 bits per pixel) are expected immediately following the last RGB LUT data in the line preceding the first active line.

The cursor bit map is set up as follows: each pixel occupies 2 bits. The meaning of these bits depends on the CMODE I2C-bus register as described in Table 5. Transparent means that the input pixels are passed through, the ‘cursor colours’ can be programmed in separate registers.

The bit map is stored with 4 pixels per byte, aligned to the least significant bit. So the first pixel is in bits 0 and 1, the next pixel in bits 3 and 4 and so on. The first index is the column, followed by the row; index 0,0 is the upper left corner.

2004 Jun 29 19

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

Table 3 Layout of a byte in the cursor bit map

D7 D6 D5 D4 D3 D2 D1 D0

pixel n + 3 pixel n + 2 pixel n + 1 pixel n D1 D0 D1 D0 D1 D0 D1 D0

For each direction, there are 2 registers controlling the position of the cursor, one controls the position of the ‘hot spot’, the other register controls the insertion position. Thehotspotisthe‘tip’ofthepointerarrow.It can have any position in the bit map. The actual position registers describe the co-ordinates of the hot spot. Again 0,0 is the upper left corner. While it is not possible to move the hot spot beyond the left respectively upper screen border thisisperfectly legal for the right respectively lower border. It should be noted that the cursor position is described relative to the input resolution.

Table 4 Cursor bit map

BYTE D7 D6 D5 D4 D3 D2 D1 D0

0row0

column 3

1row0

column 7

2row0

column 11

... ... ... ... ...

6row0

column 27 7row0

column 31

... ... ... ... ...

254 row 31

column 27 255 row 31

column 31

row 0 column 2

row 0 column 6

row 0 column 10

row 0 column 26

row 0 column 30

row 31 column 26

row 31 column 30

row 0 column 1

row 0 column 5

row 0 column 9

row 0 column 25

row 0 column 29

row 31 column 25

row 31 column 29

row 0 column 0

row 0 column 4

row 0 column 8

row 0 column 24

row 0 column 28

row 31 column 24

row 31 column 28

Table 5 Cursor modes

CURSOR PATTERN

00 second cursor colour second cursor colour 01 ﬁrst cursor colour ﬁrst cursor colour 10 transparent transparent 11 inverted input auxiliary cursor

8.5 RGB Y-CB-CR matrix

RGB input signals to be encoded to PAL or NTSC are converted to the Y-C colour difference signals are fed through low-pass filters and formatted to a ITU-R BT.601 like 4 : 2 : 2 data stream for further processing.

A gain adjust option corrects the level swing of the graphics world (black-to-white as 0 to 255) to the required range of 16 to 235.

The matrix and formatting blocks can be bypassed for Y-CB-CR graphics input.

Whenthe auxiliary VGA mode isselected,the output of the cursor insertion block is immediately directed to the triple DAC.

8.6 Horizontal scaler

The high quality horizontal scaler operates on the 4 : 2 : 2 data stream. Its control engines compensate the colour phase offset automatically.

The scaler starts processing after a programmable horizontal offset and continues with a number of input pixels. Each input pixel is a programmable fraction of the current output pixel (XINC/4096). A special case is XINC = 0, this sets the scaling factor to 1.

If the SAA7108AE; SAA7109AE input data is in accordance with another mode. In this event, XINC needs to be set to 2048 for a scaling factor of 1. With higher values, upscaling will occur.

CMODE = 0 CMODE = 1

“ITU-R BT.656”

CURSOR MODE

colour

colour space in this block. The

B-CR

, the scaler enters

2004 Jun 29 20

The phase resolution of the circuit is 12 bits, giving a maximum offset of 0.2 after 800 input pixels. Small FIFOs rearrange a 4 : 2 : 2 data stream at the scaler output.

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

8.7 Vertical scaler and anti-ﬂicker ﬁlter

The functions scaling, Anti-Flicker Filter (AFF) and re-interlacing are implemented in the vertical scaler.

Besides the entire input frame, it receives the first and last lines of the border to allow anti-flicker filtering.

Thecircuit generates the interlaced outputfieldsby scaling down the input frames with different offsets for odd and even fields. Increasing the YSKIP setting reduces the anti-flicker function. A YSKIP value of 4095switches it off; see Table 120.

An additional, programmable vertical filter supports the anti-flicker function. This filter is not available at upscaling factors of more than 2.

Theprogramming is similar tothehorizontal scaler. For the re-interlacing,the resolutions of the offset registers are not sufficient, so the weighting factors for the first lines can also be adjusted. YINC = 0 sets the scaling factor to 1; YIWGTO and YIWGTE must not be 0.

Due to the re-interlacing, the circuit can perform upscaling by a maximum factor of 2. The maximum factor depends onthe setting of the anti-flickerfunctionand can be derived from the formulae given in Section 8.20.

Anadditionalupscaling mode enables the upscaling factor to be increased to a maximum of 4 as it is required for the old VGA modes like 320 × 240.

8.10 Oscillator and Discrete Time Oscillator (DTO)

The master clock generation is realized as a 27 MHz crystal oscillator, which can operate with either a fundamental wave crystal or a 3rd-harmonic crystal.

The crystal clock supplies the DTO of the pixel clock synthesizer, the video encoder and the I2C-bus control block. It also usually supplies the triple DAC, with the exceptionoftheauxiliaryVGAmode,wherethetripleDAC is clocked by the pixel clock (PIXCLK).

The DTO can be programmed to synthesize all relevant pixel clock frequencies between circa 40 and 85 MHz. Two programmable dividers provide the actual clock to be used externally and internally. The dividers can be programmed to factors of 1, 2, 4 and 8. For the internal pixel clock, a divider ratio of 8 makes no sense and is thus forbidden.

The internal clock can be switched completely to the pixel clock input. In this event, the input FIFO is useless and will be bypassed.

The entire pixel clock generation can be locked to the vertical frequency. Both pixel clock dividers get re-initialized every field. Optionally, the DTO can be cleared with each V-sync. At proper programming, this will make the pixel clock frequency a precise multiple of the vertical and horizontal frequencies. This is required for some graphic controllers.

8.8 FIFO

The FIFO acts as a buffer to translate from the PIXCLK clock domain to the XTAL clock domain. The write clock is PIXCLK and the read clock is XTAL. An underflow or overflow condition can be detected via the I2C-bus read access.

In order to avoid underflows and overflows, it is essential that the frequency of the synthesized PIXCLK matches to the input graphics resolution and the desired scaling factor.

8.9 Border generator

When the graphics picture is to be displayed as interlaced PAL, NTSC, S-video or RGB on a TV screen, it is desired in many cases not to lose picture information due to the inherent overscanning of a TV set. The desired amount of underscan area, which is achieved through appropriate scaling in the vertical and horizontal direction, can be filled in the border generator with an arbitrary true colour tint.

2004 Jun 29 21

8.11 Low-pass Clock Generation Circuit (CGC)

This block reduces the phase jitter of the synthesized pixel clock. It works as a tracking filter for all relevant synthesized pixel clock frequencies.

8.12 Encoder

8.12.1 VIDEO PATH The encoder generates luminance and colour subcarrier

output signals from the Y, CBand CR baseband signals, which are suitable for use as CVBS or separate Y and C signals.

Input to the encoder, at 27 MHz clock (e.g. DVD), is either originated from computer graphics at pixel clock, fed throughthe FIFO and border generator,ora ITU-R BT.656 style signal.

Luminance is modified in gain and in offset (the offset is programmable in a certain range to enable different black level set-ups). A blanking level can be set after insertion of a fixed synchronization pulse tip level, in accordance with standard composite synchronization schemes.

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

Other manipulations used for the Macrovision anti-taping process, such as additional insertion of AGC super-white pulses (programmable in height), are supported by the SAA7108AE only.

To enable easy analog post filtering, luminance is interpolated from a 13.5 MHz data rate to a 27 MHz data rate, thereby providing luminance in a 10-bit resolution. The transfer characteristics of the luminance interpolation filter are illustrated in Figs 7 and 8. Appropriate transients at start/end of active video and for synchronization pulses are ensured.

Chrominance is modified in gain (programmable separately for CBand CR), and a standard dependent burst is inserted, before baseband colour signals are interpolated from a 6.75 MHz data rate to a 27 MHz data rate. One of the interpolation stages can be bypassed, thus providing a higher colour bandwidth, which can be usedforthe Y and C output. The transfer characteristics of the chrominance interpolation filter are illustrated in Figs 5 and 6.

The amplitude (beginning and ending) of the inserted burst, is programmable in a certain range that is suitable for standard signals and for special effects. After the succeeding quadrature modulator, colour is provided on the subcarrier in 10-bit resolution.

The numeric ratio between the Y and C outputs is in accordance with the standards.

8.12.3 VIDEO PROGRAMMING SYSTEM (VPS) ENCODING Five bytes of VPS information can be loaded via the

I2C-bus and will be encoded in the appropriate format into line 16.

8.12.4 CLOSED CAPTION ENCODER Using this circuit, data in accordance with the specification

of Closed Caption or extended data service, delivered by the control interface, can be encoded (line 21). Two dedicated pairs of bytes (two bytes per field), each pair preceded by run-in clocks and framing code, are possible.

Theactualline number in which data is to be encoded, can be modified in a certain range.

The data clock frequency is in accordance with the definition for NTSC M standard 32 times horizontal line frequency.

DataLOWat the output of the DACs correspondsto0 IRE, data HIGH at the output of the DACs corresponds to approximately 50 IRE.

Itis also possible to encode Closed Caption data for 50 Hz field frequencies at 32 times the horizontal line frequency.

8.12.5 ANTI-TAPING (SAA7108AE ONLY) For more information contact your nearest Philips

Semiconductors sales office.

8.12.2 TELETEXT INSERTION AND ENCODING (NOT

SIMULTANEOUSLY WITH REAL-TIME CONTROL)

Pin TTX_SRES receives a WST or NABTS teletext bitstream sampled at the crystal clock. At each rising edge of the output signal (TTXRQ) a single teletext bit has to be provided after a programmable delay at input pin TTX_SRES.

Phase variant interpolation is achieved on this bitstream in the internal teletext encoder, providing sufficient small phase jitter on the output text lines.

TTXRQ_XCLKO2 provides a fully programmable request signal to the teletext source, indicating the insertion period of bitstream at lines which can be selected independently for both fields. The internal insertion window for text is set to 360 (PAL WST), 296 (NTSC WST) or 288 (NABTS) teletext bits including clock run-in bits. The protocol and timing are illustrated in Fig.51.

Alternatively, this pin can be provided with a buffered crystal clock (XCLK) of 13.5 MHz.

2004 Jun 29 22

8.13 RGB processor

This block contains a dematrix in order to produce RED, GREEN and BLUE signals to be fed to a SCART plug.

Before Y, CBand CR signals are de-matrixed, individual gain adjustment for Y and colour difference signals and 2 times oversampling for luminance and 4 times oversampling for colour difference signals is performed. The transfer curves of luminance and colour difference components of RGB are illustrated in Figs 9 and 10.

8.14 Triple DAC

Both Y and C signals are converted from digital-to-analog in a 10-bit resolution at the output of the video encoder. Y and C signals are also combined into a 10-bit CVBS signal.

The CVBS output signal occurs with the same processing delay as the Y, C and optional RGB or CR-Y-CB outputs. Absolute amplitude at the input of the DAC for CVBS is reduced by15⁄16with respect to Y and C DACs to make maximum use of the conversion ranges.

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

RED, GREEN and BLUE signals are also converted from digital-to-analog, each providing a 10-bit resolution.

The reference currents of all three DACs can be adjusted individually in order to adapt for different output signals. In addition, all reference currents can be adjusted commonly to compensate for small tolerances of the on-chip band gap reference voltage.

Alternatively, all currents can be switched off to reduce power dissipation.

All three outputs can be used to sense for an external load (usually 75 Ω) during a pre-defined output. A flag in the I2C-bus status byte reflects whether a load is applied or not. An automatic sense mode can also be activated, which will immediately indicate any 75 Ω load at any of the three outputs at the dedicated interrupt pin TVD.

If the SAA7108AE; SAA7109AE is required to drive a second (auxiliary) VGA monitor or an HDTV set, the DACs receive the signal coming from the HD data path. In this event, the DACs are clocked at the incoming PIXCLKI instead of the 27 MHz crystal clock used in the video encoder.

8.15 HD data path

This data path enables the SAA7108AE; SAA7109AE to be used with VGA or HDTV monitors. It receives its data directly from the cursor generator and supports RGB and Y-PB-PR output formats (RGB not with Y-PB-PR input formats). No scaling is done in this mode.

Alternatively, the device can be triggered by auxiliary codes in a ITU-R BT.656 data stream via PD7 to PD0.

Only vertical frequencies of 50 and 60 Hz are allowed with the SAA7108AE; SAA7109AE. In slave mode, it is not possible to lock the encoders colour carrier to the line frequency with the PHRES bits.

In the (more common) master mode, the time base of the circuit is continuously free-running. The IC can output a frame sync at pin FSVGC, a vertical sync at pin VSVGC, a horizontal sync at pin HSVGC and a composite blanking signal at pin CBO. All of these signals are defined in the PIXCLK domain. The duration of HSVGC and VSVGC are fixed,they are 64 clocks forHSVGCand 1 line for VSVGC. The leading slopes are in phase and the polarities can be programmed.

The input line length can be programmed. The field length is always derived from the field length of the encoder and the pixel clock frequency that is being used.

CBO acts as a data request signal. The circuit accepts input data at a programmable number of clocks after CBO goes active. This signal is programmable and it is possible to adjust the following (see Figs 49 and 50):

• The horizontal offset

• The length of the active part of the line

• The distance from active start to first expected data

• The vertical offset separately for odd and even fields

• The number of lines per input field.

A gain adjustment either leads the full level swing to the digital-to-analog converters or reduces the amplitude by a factor of 0.69. This enables sync pulses to be added to the signal as it is required for display units that require signals with sync pulses, either regular or 3-level syncs.

8.16 Timing generator

The synchronization of the SAA7108AE; SAA7109AE is able to operate in two modes; slave mode and master mode.

In slave mode, the circuit accepts sync pulses on the bidirectional FSVGC (frame sync), VSVGC (vertical sync) and HSVGC (horizontal sync) pins: the polarities of the signals can be programmed. The frame sync signal is only necessary when the input signal is interlaced, in other casesit may be omitted. If theframesyncsignal is present, it is possible to derive the vertical and the horizontal phase from it by setting the HFS and VFS bits. HSVGC and VSVGC are not necessary in this case, so it is possible to switch the pins to output mode.

2004 Jun 29 23

In most cases, the vertical offsets for odd and even fields are equal. If they are not, then the even field will start later. The SAA7108AE; SAA7109AE will also request the first input lines in the even field, the total number of requested lines will increase by the difference of the offsets.

As stated above, the circuit can be programmed to accept the look-up and cursor data in the first 2 lines of each field. The timing generator provides normal data request pulses forthese lines; the duration is thesameasfor regular lines. The additional request pulses will be suppressed with LUTL set to logic 0; see Table 143. The other vertical timings do not change in this case, so the first active line can be number 2, counted from 0.

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

8.17 Pattern generator for HD sync pulses

The pattern generator provides an appropriate synchronization pattern for the video data path in auxiliary monitororHDTV mode, respectively. It providesmaximum flexibility in terms of raster generation for all interlaced and non-interlaced computer graphics or ATSC formats. The sync engine is capable of providing a combination of event-value pairs which can be used to insert certain values at specified times in the outgoing data stream. It can also be used to generate digital signals associated with time events. They can be used as digital horizontal andvertical synchronization signalsonpins HSM_CSYNC and VSM.

The picture position is adjustable through the programmable relationship between the sync pulses and the video contents.

The generation of embedded analog sync pulses is bound to a number of events which can be defined for a line. Several of these line timing definitions can exist in parallel. Forthe final sync raster composition a certain sequence of lineswithdifferent sync event properties has to be defined. The sequence specifies a series of line types and the number of occurrences of this specific line type. After the sequence has been completed, it restarts from the beginning. All pulse shapes are filtered internally in order to avoid ringing after analog post filters.

The sequence of the generated pulse stream must fit precisely to the incoming data stream in terms of the total number of pixels per line and lines per frame.

The sync engines flexibility is achieved by using a sequence of linked lists carrying the properties for the image, the lines as well as fractions of lines. Figure 11 illustrates the context between the various tables.

The first table serves as an array to hold the correct sequence of lines composing the synchronization raster. It cancontainupto16 entries. Each entry holds a 4-bit index tothe next table and a 10-bit counter value which specifies how often this particular line is invoked. If the necessary line count for a particular line exceeds the 10 bits, it has to use two table entries.

Each index of this table points to a particular line of the next table in the linked list. This table is called the line pattern array and each of the up to seven entries stores up tofour pairs of a duration in pixel clock cycles and an index to a value table. The table entries are used to define portions of a line representing a certain value for a certain number of clock cycles.

The value specified in this table is actually another 3-bit index into a value array which can hold up to eight 8-bit values. If bit 4 (MSB) of the index is logic 1, the value is inserted into the G or Y signal only; if bit 4 = 0, the associated value is inserted into all three signals.

Two additional bits of the entries in the value array (LSBs of the second byte) determine if the associated events appearasa digital pulse on the HSM_CSYNC and/or VSM outputs.

To ease the trigger set-up for the sync generation module, a set of registers is provided to set up the screen raster defined as width and height. A trigger position can be specified as an x, y co-ordinate within the overall dimensions of the screen raster. If the x, y counter matches the specified co-ordinates, a trigger pulse is generated which pre-loads the tables with their initial values.

Table 6 outlines an example on how to set up the sync tables for a 1080i HD raster.

Important note:

Due to a problem in the programming interface, writing to the line pattern array (address D2) might destroy the data of the line type array (address D1). A work around is to write the line pattern array data before writing the line type array. Reading of the arrays is possible but all address pointers must be initialized before the next write operation.

The4-bitindexinthelinecountarraypointstothelinetype array. It holds up to 15 entries where, index 0 is not used, index 1 points to the first entry, index 2 to the second entry of the line type array etc.

Each entry of the line type array can hold up to 8 index pointerstoanother table. These indices point to portions of alinepulsepattern:A line could be split up e.g. into a sync, a blank, and an active portion followed by another blank portion, occupying four entries in one table line.

2004 Jun 29 24

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

handbook, full pagewidth

4-bit line type index

line type pointer

8 + 2-bit value

VALUE ARRAY

8 entries

10-bit line count

LINE COUNT ARRAY

16 entries

3 3 3 3 3 3 3 3

LINE TYPE ARRAY

15 entries

3 3 3 3 3 3 3 3

event type pointer

10-bit duration

4-bit value index

10-bit duration

4-bit value index

line

count

pointer

LINE PATTERN ARRAY

7 entries

line pattern pointer

pattern pointer

10-bit duration

4-bit value index

10-bit duration

4-bit value index

MBL797

Fig.11 Context between the pattern generator tables for DH sync pulses.

2004 Jun 29 25

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

Table 6 Example for set-up of the sync tables

SEQUENCE COMMENT

Write to subaddress D0H

00 points to ﬁrst entry of line count array (index 0) 05 20 generate 5 lines of line type index 2 (remember, it is the second entry of the line type

array); will be the ﬁrst vertical raster pulse

01 40 generate 1 line of line type index 4; will be sync-black-sync-black sequence after the ﬁrst

vertical pulse 0E 60 generate 14 lines of line type index 6; will be the following lines with sync-black sequence 1C 12 generate 540 lines of line type index 1; will be lines with sync and active video 02 60 generate 2 lines of line type index 6; will be the following lines with sync-black sequence 01 50 generate 1 line of line type index 5; will be the following line (line 563) with

sync-black-sync-black-null sequence (null is equivalent to sync tip) 04 20 generate 4 lines of line type index 2; will be the second vertical raster pulse 01 30 generate 1 line of line type index 3; will be the following line with sync-null-sync-black

sequence 0F 60 generate 15 lines of line type index 6; will be the following lines with sync-black sequence 1C 12 generate 540 lines of line type index 1; will be lines with sync and active video 02 60 generate 2 lines of line type index 6; will be the following lines with sync-black sequence;

now, 1125 lines are deﬁned

Write to subaddress D2H (insertion is done into all three analog output signals)

00 points to ﬁrst entry of line pattern array (index 1) 6F 33 2B 30 00 00 00 00 880 × value(3) + 44 × value(3); (subtract 1 from real duration) 6F 43 2B 30 00 00 00 00 880 × value(4) + 44 × value(3) 3B 30 BF 03 BF 03 2B 30 60 × value(3) + 960 × value(0) + 960 × value(0) + 44 × value(3) 2B 10 2B 20 57 30 00 00 44 × value(1) + 44 × value(2) + 88 × value(3) 3B 30 BF 33 BF 33 2B 30 60 × value(3) + 960 × value(3) + 960 × value(3) + 44 × value(3)

Write to subaddress D1H

00 points to ﬁrst entry of line type array (index 1) 34 00 00 00 use pattern entries 4 and 3 in this sequence (for sync and active video) 24 24 00 00 use pattern entries 4, 2, 4 and 2 in this sequence (for 2 × sync-black-null-black) 24 14 00 00 use pattern entries 4, 2, 4 and 1 in this sequence (for sync-black-null-black-null) 14 14 00 00 use pattern entries 4, 1, 4 and 1 in this sequence (for sync-black-sync-black) 14 24 00 00 use pattern entries 4, 1, 4 and 2 in this sequence (for sync-black-sync-black-null) 54 00 00 00 use pattern entries 4 and 5 in this sequence (for sync-black)

2004 Jun 29 26

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

SEQUENCE COMMENT

Write to subaddress D3H (no signals are directed to pins HSM_CSYNC and VSM)

00 points to ﬁrst entry of value array (index 0) CC 00 black level, to be added during active video 80 00 sync level LOW (minimum output voltage) 0A 00 sync level HIGH (3-level sync) CC 00 black level (needed elsewhere) 80 00 null (identical with sync level LOW)

Write to subaddress DCH

0B insertion is active, gain for signal is adapted accordingly

8.18 I2C-bus interface

The I2C-bus interface is a standard slave transceiver, supporting 7-bit slave addresses and 400 kbits/s guaranteed transfer rate. It uses 8-bit subaddressing with an auto-increment function. All registers are read and write, except two read only status bytes.

The register bit map consists of an RGB Look-Up Table (LUT), a cursor bit map and control registers. The LUT containsthree banks of 256 bytes, where each RGB triplet isassigned to one address. Thus a write access needs the LUT address and three data bytes following subaddress FFH. For further write access auto-incrementing of the LUT address is performed. The cursor bit map access is similar to the LUT access but contains only a single byte per address.

The I2C-bus slave address is defined as 88H.

8.19 Power-down modes

In order to reduce the power consumption, the SAA7108AE; SAA7109AE supports 2 Power-down modes, accessible via the I2C-bus. The analog Power-down mode (DOWNA = 1) turns off the digital-to-analog converters and the pixel clock synthesizer. The digital down mode turns off all internal clocks and sets the digital outputs to LOW except the I2C-bus interface. The IC retains its programming and can still be accessed in this mode, but not all registers can be read from or written to. Reading or writing to the look-up tables, the cursor and the HD sync generator require a valid pixel clock. The typical supply current in full power-down is approximately 5 mA.

So in most cases, DOWNA and DOWND should be set to logic 1 simultaneously. If the EIDIV bit is logic 1, it should be set to logic 0 before power-down.

8.20 Programming the graphics acquisition scaler of the video encoder

The encoder section needs to provide a continuous data stream at its analog outputs as well as receive a continuous stream from its data source. Due to the fact that there is no frame memory isolating the data streams, restrictions apply to the input frame timings.

Input and output processing of the encoder section are only coupled through the vertical frequencies. In master mode, the encoder provides a vertical sync and an odd/even pulse to the input processing, in slave mode, the encoder receives them.

The parameters of the input field are mainly given by the memory capacity of the encoder section. The rule is that the scaler and thus the input processing needs to provide the video data in the same time frames as the encoder reads them. So the vertical active video times (and the vertical frequencies) need to be the same.

The second rule is that there has to be data in the buffer FIFO when the encoder enters the active video area. So the vertical offset in the input path needs to be a bit shorter than the offset of the encoder.

The following gives the set of equations required to program the IC for the most common application: A post processor in master mode with non-interlaced video input data.

Due to the fact that the analog Power-down mode turns off the pixel clock synthesizer, there are limitations in some applications. If there is no pixel clock, the IC is not able to set its outputs to LOW.

2004 Jun 29 27

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

Some variables are defined below:

• InPix: the number of active pixels per input line

• InPpl: the length of the entire input line in pixel clocks

• InLin: the number of active lines per input field/frame

• TPclk: the pixel clock period

• RiePclk: the ratio of internal to external pixel clock

• OutPix: the number of active pixels per output line

• OutLin: the number of active lines per output field

• TXclk: the encoder clock period (37.037 ns).

8.20.1 TV DISPLAY WINDOW At 60 Hz, the first visible pixel has the index 256,

710 pixels can be encoded; at 50 Hz, the index is 284, 702 pixels can be visible.

Theoutputlinesshouldbecentred on the screen. It should be noted that the encoder has 2 clocks per pixel; see Table 93.

ADWHS = 256 + 710 − OutPix (60 Hz); ADWHS = 284 + 702 − OutPix (50 Hz); ADWHE = ADWHS + OutPix × 2 (all frequencies)

For vertical, the procedure is the same. At 60 Hz, the first line with video information is number 19, 240 lines can be active. For 50 Hz, the numbers are 23 and 287; see Table 99.

240 OutLin–

FAL 19

FAL 23

LAL = FAL + OutLin (all frequencies) Most TV sets use overscan, and not all pixels respectively

lines are visible. There is no standard for the factor, it is highly recommended to make the number of output pixels and lines adjustable. A reasonable underscan factor is 10 %, giving approximately 640 output pixels per line.

8.20.2 INPUT FRAME AND PIXEL CLOCK The total number of pixel clocks per line and the input

horizontal offset need to be chosen next. The only constraint is that the horizontal blanking has at least 10 clock pulses.

The required pixel clock frequency can be determined in thefollowingway:Due to the limited internal FIFO size, the input path has to provide all pixels in the same time frame as the encoders vertical active time. The scaler also has to process the first and last border lines for the anti-flicker function.

--------------------------------2

287 OutLin–

--------------------------------2

(60 Hz);

(50 Hz);

TPclk

Thus: (60 Hz)

TPclk

---------------------------------------------------------------------------------------InPpl integer

and for the pixel clock generator

PCL

see Tables 102, 104 and 105. The divider PCLE should be set according to Table 104. PCLI may be set to a lower or the same value. Setting a lower value means that the internal pixel clock is higher and the data get sampled up. Thedifferencemaybe 1 at 640 × 480 pixels resolution and 2 at resolutions with 320 pixels per line as a rule of thumb. This allows horizontal upscaling by a maximum factor of 2 respectively 4 (this is the parameter RiePclk).

PCLI PCLE

The equations ensure that the last line of the field has the full number of clock cycles. Many graphic controllers require this. Note that the bit PCLSY needs to be set to ensure that there is not even a fraction of a clock left at the end of the field.

8.20.3 H XOFS can be chosen arbitrarily, the condition being that

XOFS + XPIX ≤ HLEN is fulfilled. Values given by the VESA display timings are preferred.

HLEN = InPpl × RiePclk − 1

XPIX

XINC

XINC needs to be rounded up, it needs to be set to 0 for a scaling factor of 1.

8.20.4 VERTICAL SCALER The input vertical offset can be taken from the assumption

thatthescalershould have just finished writing the first line when the encoder starts reading it:

YOFS

TXclk

-------------- TPclk

ORIZONTAL SCALER

InPix

------------ 2

OutPix

----------------- InPix

FAL 1716× TXclk×

----------------------------------------------------

InPpl TPclk×

FAL 1728× TXclk×

----------------------------------------------------

InPpl TPclk×

262.5 1716× TXclk×

----------------------------------------------------------------------------------------

InPpl integer

312.5 1728× TXclk×

20 PCLE+

×=

RiePclklog

–=

---------------------------2log

RiePclk×=

4096

×=

------------------- RiePclk

InLin 2+



----------------------



OutLin

InLin 2+



----------------------



OutLin

(all frequencies);

(all frequencies)

2.5–=

262.5×

(50 Hz)

312.5×

(60 Hz)

(50 Hz)

2004 Jun 29 28

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

In most cases the vertical offsets will be the same for odd and even fields. The results should be rounded down.

YPIX = InLin YSKIPdefinestheanti-flickerfunction.0 meansmaximum

flicker reduction but minimum vertical bandwidth, 4095 gives no flicker reduction and maximum bandwidth. Note that the maximum value for YINC is 4095. It might be necessary to reduce the value of YSKIP to fulfil this requirement.

YINC

YIWGTO

YIWGTE

OutLin

---------------------InLin 2+

YINC

------------- 2

YINC YSKIP–

------------------------------------- -

YSKIP



× 4096×=

-----------------



4095

2048+=

When YINC = 0 it sets the scaler to scaling factor 1. The initial weighting factors must not be set to 0 in this case. YIWGTE may go negative. In this event, YINC should be added and YOFSE incremented. This can be repeated as often as necessary to make YIWGTE positive.

Note that these equations assume that the input is non-interlaced while the output is interlaced. If the input is interlaced, the initial weighting factors need to be adapted to get the proper phase offsets in the output frame.

If vertical upscaling beyond the upper capabilities is required, the parameter YUPSC may be set to 1. This extends the maximum vertical scaling factor by a factor 2. Only the parameter YINC gets affected, it needs to be divided by 2 to get the same effect.

There are restrictions in this mode:

• The vertical filter YFILT is not available in this mode; the circuit will ignore this value

• The horizontal blanking needs to be long enough to transfer an output line between 2 memory locations. This is 710 internal pixel clocks

Ortheupscaling factor needs to be limited to 1.5andthe horizontal upscaling factor is also limited to less than ∼1.5. In this case a normal blanking length is sufficient.

For C and CVBS outputs, deviating amplitudes of the colour difference signals can be compensated for by independent gain control setting, while gain for luminance is set to predefined values, distinguishable for 7.5 IRE set-up or without set-up.

The RGB, respectively C

-Y-CB path features an

individual gain setting for luminance (GY) and colour difference signals (GCD). Reference levels are measured with a colour bar, 100 % white, 100 % amplitude and 100 % saturation.

The encoder section of the SAA7108AE; SAA7109AE has special input cells for the VGC port. They operate at a wider supply voltage range and have a strict input threshold at1/2V

DD(DVO)

. To achieve full speed of these cells, the EIDIV bit needs to be set to logic 1. In this case the impedance of these cells is approximately 6 kΩ. This may cause trouble with the bootstrapping pins of some graphic chips. So the power-on reset forces the bit to logic 0, the input impedance is regular in this mode.

Table 7

“ITU-R BT.601”

signal component levels

SIGNALS

(1)

COLOUR

YCBC

RGB

White 235 128 128 235 235 235 Yellow 210 16 146 235 235 16 Cyan 170 166 16 16 235 235 Green 145 54 34 16 235 16 Magenta 106 202 222 235 16 235 Red 81 90 240 235 16 16 Blue 41 240 110 16 16 235 Black 16 128 128 16 16 16

Note

1. Transformation:

a) R = Y + 1.3707 × (CR− 128) b) G=Y− 0.3365 × (CB− 128) − 0.6982 × (CR− 128) c) B = Y + 1.7324 × (CB− 128).

8.21 Input levels and formats

The SAA7108AE; SAA7109AE accepts digital Y, C

B,CR

or RGB data with levels (digital codes) in accordance with

“ITU-R BT.601”

. An optional gain adjustment also allows

data to be accepted with the full level swing of 0 to 255.

2004 Jun 29 29

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

Table 8 Usage of bits SLOTand EDGE

DATA SLOT CONTROL

(EXAMPLE FOR FORMAT 0)

SLOT EDGE 1st DATA 2nd DATA

0 0 at rising edge

G3/Y3

0 1 at falling edge

G3/Y3

1 0 at rising edge

R7/CR7

1 1 at falling edge

R7/CR7

Table 9 Pin assignment for input format 0

8 + 8 + 8-BIT 4 : 4 : 4 NON-INTERLACED

RGB/CB-Y-C

PD11 G3/Y3 R7/CR7 PD10 G2/Y2 R6/CR6 PD9 G1/Y1 R5/CR5 PD8 G0/Y0 R4/CR4 PD7 B7/CB7 R3/CR3 PD6 B6/CB6 R2/CR2 PD5 B5/CB5 R1/CR1 PD4 B4/CB4 R0/CR0 PD3 B3/CB3 G7/Y7 PD2 B2/CB2 G6/Y6 PD1 B1/CB1 G5/Y5 PD0 B0/CB0 G4/Y4

FALLING

CLOCK EDGE

at falling edge R7/CR7

at rising edge R7/CR7

at falling edge G3/Y3

at rising edge G3/Y3

RISING

CLOCK EDGE

Table 10 Pin assignment for input format 1

5 + 5 + 5-BIT 4 : 4 : 4 NON-INTERLACED RGB

PD7 G2 X PD6 G1 R4 PD5 G0 R3 PD4 B4 R2 PD3 B3 R1 PD2 B2 R0 PD1 B1 G4 PD0 B0 G3

Table 11 Pin assignment for input format 2

5 + 6 + 5-BIT 4 : 4 : 4 NON-INTERLACED RGB

PD7 G2 R4 PD6 G1 R3 PD5 G0 R2 PD4 B4 R1 PD3 B3 R0 PD2 B2 G5 PD1 B1 G4 PD0 B0 G3

Table 12 Pin assignment for input format 3

8 + 8 + 8-BIT 4:2:2 NON-INTERLACED CB-Y-C

FALLING

PD7 CB7(0) Y7(0) CR7(0) Y7(1) PD6 CB6(0) Y6(0) CR6(0) Y6(1) PD5 CB5(0) Y5(0) CR5(0) Y5(1) PD4 CB4(0) Y4(0) CR4(0) Y4(1) PD3 CB3(0) Y3(0) CR3(0) Y3(1) PD2 CB2(0) Y2(0) CR2(0) Y2(1) PD1 CB1(0) Y1(0) CR1(0) Y1(1) PD0 CB0(0) Y0(0) CR0(0) Y0(1)

CLOCK

EDGE

FALLING

CLOCK EDGE

FALLING

CLOCK EDGE

RISING

CLOCK

EDGE

FALLING

CLOCK

RISING

CLOCK EDGE

RISING

CLOCK EDGE

EDGE

n+1

RISING CLOCK

EDGE

n+1

2004 Jun 29 30

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

Table 13 Pin assignment for input format 4

8 + 8 + 8-BIT 4 : 2 : 2 INTERLACED CB-Y-C

(ITU-R BT.656, 27 MHz CLOCK)

RISING

CLOCK

EDGE

RISING

CLOCK

EDGE

n+1

RISING

CLOCK

EDGE

n+2

RISING CLOCK

EDGE

n+3

Table 14 Pin assignment for input format 5; note 1

8-BIT NON-INTERLACED INDEX COLOUR

FALLING

CLOCK EDGE

RISING

CLOCK EDGE

PD11 X X PD10 X X PD9 X X PD8 X X PD7 INDEX7 X PD6 INDEX6 X PD5 INDEX5 X PD4 INDEX4 X PD3 INDEX3 X PD2 INDEX2 X PD1 INDEX1 X PD0 INDEX0 X

Table 15 Pin assignment for input format 6

8 + 8 + 8-BIT 4 : 4 : 4 NON-INTERLACED

RGB/CB-Y-C

FALLING

CLOCK EDGE

RISING

CLOCK EDGE

PD11 G4/Y4 R7/CR7 PD10 G3/Y3 R6/CR6 PD9 G2/Y2 R5/CR5 PD8 B7/CB7 R4/CR4 PD7 B6/CB6 R3/CR3 PD6 B5/CB5 G7/Y7 PD5 B4/CB4 G6/Y6 PD4 B3/CB3 G5/Y5 PD3 G0/Y0 R2/CR2 PD2 B2/CB2 R1/CR1 PD1 B1/CB1 R0/CR0 PD0 B0/CB0 G1/Y1

Note

1. X = don’t care.

2004 Jun 29 31

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

9 FUNCTIONAL DESCRIPTION OF DIGITAL VIDEO DECODER PART

9.1 Decoder

9.1.1 ANALOG INPUT PROCESSING The SAA7108AE; SAA7109AE offers six analog signal inputs, two analog main channels with source switch, clamp

circuit, analog amplifier, anti-alias filter and video 9-bit CMOS ADC; see Fig.15.

9.1.2 ANALOG CONTROL CIRCUITS The anti-alias filters are adapted to the line-locked clock frequency via a filter control circuit. The characteristics are

illustrated in Fig.12. During the vertical blanking period, gain and clamping control is frozen.

(dB)

−6

−12

−18

−24

−30

−36

−42

024 68101214

MGD138

f (MHz)

Fig.12 Anti-alias filter.

2004 Jun 29 32

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

9.1.2.1 Clamping

The clamping control circuit controls the correct clamping of the analog input signals. A coupling capacitor is used to store and filter the clamping voltage. An internal digital clamp comparator generates the information with respect to clamp-up or clamp-down. The clamping levels for the two ADC channels are fixed for luminance (60) and chrominance (128). Clamping time in normal use is set with the HCL pulse at the back porch of the video signal.

9.1.2.2 Gain control

The gain control circuit receives (via the I2C-bus) the static gain levels for the two analog amplifiers, or controls one of theseamplifiersautomaticallyvia a built-in Automatic Gain Control (AGC) as part of the Analog Input Control (AICO).

HSY

TV line

HCL

MGL065

analog line blanking

255

GAIN CLAMP

The AGC (automatic gain control for luminance) is used to amplify a CVBS or Y signal to the required signal amplitude, which is matched to the ADCs input voltage range.TheAGCactivetimeisthe sync bottom of the video signal.

Signal (white) peak control limits the gain at signal overshoots. The influence of supply voltage variation within the specified range is automatically eliminated by clampingandautomatic gain control. The flow charts show more details of the AGC; see Figs 16 and 17.

analog input level

+3 dB

0 dB

(1 V (p-p) 18/56 Ω)

−6 dB

maximum

range 9 dB

minimum

controlled

ADC input level

0 dB

MHB325

Fig.13 Analog line with clamp (HCL) and gain

range (HSY).

2004 Jun 29 33

Fig.14 Automatic gain range.

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2004 Jun 29 34

dbook, full pagewidth

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

AI24 AI23

AI2D

AI22 AI21

AI12

AI1D

AI11

P6 P7

P8 P9

P10

P11 P12 P13

SOURCE

SWITCH

SOURCE

SWITCH

MODE

CONTROL

MODE3 MODE2 MODE1 MODE0

CLAMP

CIRCUIT

CLAMP

CIRCUIT

CLAMP

CONTROL

HCL

GLIMB GLIMT WIPA SLTCA

ANALOG

AMPLIFIER

DAC9

ANALOG

AMPLIFIER

DAC9

GAIN

CONTROL

HSY

HOLDG GAFIX WPOFF GUDL[1:0 GAI[28:20 GAI[18:10 HLNRS UPTCV

ANTI-ALIAS

FILTER

ANTI-ALIAS

FILTER

ANTI-ALIAS

CONTROL

]

] ]

BYPASS SWITCH

FUSE[1:0

VBLNK SVREF

]

FUSE[1:0

VERTICAL BLANKING CONTROL

VBSL

ANALOG CONTROL

TEST

SELECTOR

AND

BUFFER

AOSL[1:0

ADC2

ADC1

M10

]

AOUT

CROSS MULTIPLEXER

9 999

CVBS/CHRCVBS/LUM

AD1BYPAD2BYP

Fig.15 Analog input processing using the SAA7108AE; SAA7109AE as differential front-end with 9-bit ADC.

MHB892

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

ANALOG INPUT

NO ACTION

+1/F

ANTI-ALIAS FILTER

248

+1/L

AMPLIFIER

ADC

VBLK

254

X = 0

−1/LLC2

gain

HOLDG

+1/LLC2 −1/LLC2

DAC

LUMA/CHROMA DECODER

HSY

254

X = 1

+/− 0

STOP

X = system variable. Y = (IAGV − FGVI) > GUDL. VBLK = vertical blanking pulse. HSY = horizontal sync pulse. AGV = actual gain value. FGV = frozen gain value.

GAIN ACCUMULATOR (18 BITS)

ACTUAL GAIN VALUE 9-BIT (AGV) [−3/+6 dB

AGV

Fig.16 Gain flow chart.

2004 Jun 29 35

GAIN VALUE 9-BIT

HSY

UPDATE

]

FGV

MHB531

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

ANALOG INPUT

ADC

NO BLANKING ACTIVE

+ CLAMP − CLAMP

WIPE = white peak level (254). SBOT = sync bottom level (1). CLL = clamp level [60 Y (128 C)]. HSY = horizontal sync pulse. HCL = horizontal clamp pulse.

VBLK

GAIN -><- CLAMP

10 10

HCL HSY

01 10

CLL

NO CLAMP

+ GAIN − GAIN

SBOT

Fig.17 Clamp and gain flow.

fast − GAIN

WIPE

slow + GAIN

MGC647

2004 Jun 29 36

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2004 Jun 29 37

9.1.3 CHROMINANCE AND LUMINANCE PROCESSING

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

CVBS-IN

or CHR-IN

CVBS-IN

or Y-IN

QUADRATURE

DEMODULATOR

SUBCARRIER

GENERATION 1

HUEC

LDEL

YCOMB

SUBCARRIER

GENERATION 2

CHROMINANCE

INCREMENT

DELAY

COMPENSATION

QUADRATURE

MODULATOR

LOW-PASS 1

DOWNSAMPLING

LCBW[2:0

LDEL YCOMB

CHROMINANCE

INCREMENT DTO-RESET

SUBCARRIER

INCREMENT

GENERATION

AND

DIVIDER

SUBTRACTOR

CHR

INTERPOLATION

LOW-PASS 3

LUBW

ADAPTIVE

COMB FILTER

SET_RAW

]

SET_VBI

CCOMB YCOMB

LDEL

BYPS

PHASE

DEMODULATOR

AMPLITUDE

DETECTOR

BURST GATE

ACCUMULATOR

LOOP FILTER

LUMINANCE-PEAKING

Y-DELAY ADJUSTMENT

LUFI[3:0 CSTD[2:0 YDEL[2:0

LOW-PASS,

]

SET_RAW

]

SET_VBI

]

LOW-PASS 2

CHBW

SECAM

PROCESSING

CHROMA

GAIN

CONTROL

UV-

ADJUSTMENT

Y/CVBS

DBRI[7:0

DCON[7:0

DSAT[7:0 RAWG[7:0 RAWO[7:0

PAL DELAY LINE

RECOMBINATION

]

] ]

COLO

BRIGHTNESS

CONTRAST

SATURATION

CONTROL

RAW DATA

GAIN AND

OFFSET

CONTROL

SET_RAW

SET_VBI

SECAM

Y-OUT/ CVBS-OUT

UV-OUT

HREF-OUT

CDTO

RTCO

CSTD[2:0

INCS

]

FCTC

ACGC

CGAIN[6:0

IDEL[3:0

Fig.18 Chrominance and luminance processing.

CODE

] ]

handbook, full pagewidth

SECS

SET_RAW

SET_VBI

fH/2 switch signal

DCVF

MHB532

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

9.1.3.1 Chrominance path

The 9-bit CVBS or chrominance input signal is fed to the inputofaquadraturedemodulator,whereitismultipliedby twotime-multiplexed subcarrier signalsfromthe subcarrier generation block 1 (0 and 90° phase relationship to the demodulator axis). The frequency is dependent on the chosen colour standard.

The time-multiplexed output signals of the multipliers are low-pass filtered (low-pass 1). Eight characteristics are programmable via LCBW3 to LCBW0 to achieve the desired bandwidth for the colour difference signals (PAL, NTSC) or the 0° and 90° FM signals (SECAM).

Thechrominance low-pass 1characteristicalso influences the grade of cross-luminance reduction during horizontal colour transients (large chrominance bandwidth means strong suppression of cross-luminance). If the Y comb filter is disabled when YCOMB = 0 the filter directly influences the width of the chrominance notch within the luminance path (large chrominance bandwidth means wide chrominance notch resulting to lower luminance bandwidth).

The low-pass filtered signals are fed to the adaptive comb filter block. The chrominance components are separated from the luminance via a two-line vertical stage (four lines forPAL standards) and a decision logiccircuitbetween the filtered and the non-filtered output signals: this block is bypassed for SECAM signals. The comb filter logic can be enabled independently for the succeeding luminance and chrominance processing by YCOMB (subaddress 09H, bit 6) and/or CCOMB (subaddress 0EH, bit 0). It is always bypassed during VBI or raw data lines, programmable by the LCRn registers (subaddresses 41H to 57H); see Section 9.2.

The separated CB-CR components are further processed by a second filter stage (low-pass 2) to modify the chrominance bandwidth without influencing the luminance path. It’s characteristic is controlled by CHBW (subaddress 10H, bit 3). For the complete transfer characteristic of low-pass filters 1 and 2 see Figs 19 and 20.

The SECAM processing (bypassed for QAM standards) contains the following blocks:

• Baseband ‘bell’ filters to reconstruct the amplitude and phase equalized 0° and 90° FM signals

• Phase demodulator and differentiator (FM demodulation)

• De-emphasis filter to compensate the pre-emphasized input signal, including frequency offset compensation (DB or DR white carrier values are subtracted from the signal, controlled by the SECAM switch signal).

The succeeding chrominance gain control block amplifies or attenuates the CB-CR signal according to the required ITU 601/656 levels. It is controlled by the output signal from the amplitude detection circuit within the burst processing block.

The burst processing block provides the feedback loop of the chrominance PLL and contains the following:

• Burst gate accumulator

• Colour identification and killer

• Comparisonnominal/actual burstamplitude(PAL/NTSC

standards only)

• Loop filter chrominance gain control (PAL/NTSC standards only)

• Loop filter chrominance PLL (only active for PAL/NTSC standards)

• PAL/SECAM sequence detection, H/2-switch generation.

The increment generation circuit produces the Discrete Time Oscillator (DTO) increment for both subcarrier generation blocks. It contains a division by the increment of the line-locked clock generator to create a stable phase-locked sine signal under all conditions (e.g. for non-standard signals).

The PAL delay line block eliminates crosstalk between the chrominance channels in accordance with the PAL standard requirements. For NTSC colour standards, the delay line can be used as an additional vertical filter. If desired, it can be switched off by DCVF = 1. It is always disabledduringVBIor raw data lines programmable by the LCRn registers (subaddresses 41H to 57H); see Section 9.2. The embedded line delay is also used for SECAM recombination (cross-over switches).

2004 Jun 29 38

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

(1) LCBW[2:0] = 000. (2) LCBW[2:0] = 010. (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110.

(5) LCBW[2:0] = 001. (6) LCBW[2:0] = 011. (7) LCBW[2:0] = 101. (8) LCBW[2:0] = 111.

(dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−48

−51

−54

−57

−60

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

(dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−48

−51

−54

−57

−60

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

(1) (2) (3) (4)

(5) (6) (7) (8)

MHB533

f (MHz)

Fig.19 Transfer characteristics of the chrominance low-pass at CHBW = 0.

2004 Jun 29 39

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

(1) LCBW[2:0] = 000. (2) LCBW[2:0] = 010. (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110.

(5) LCBW[2:0] = 001. (6) LCBW[2:0] = 011. (7) LCBW[2:0] = 101. (8) LCBW[2:0] = 111.

(dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−48

−51

−54

−57

−60

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

(dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−48

−51

−54

−57

−60

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

(1) (2) (3) (4)

(5) (6) (7) (8)

MHB534

f (MHz)

Fig.20 Transfer characteristics of the chrominance low-pass at CHBW = 1.

2004 Jun 29 40

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

9.1.3.2 Luminance path

The rejection of the chrominance components within the 9-bit CVBS or Y input signal is done by subtracting the re-modulated chrominance signal from the CVBS input.

The comb filtered CB-CR components are interpolated (upsampled) by the low-pass 3 block. It’s characteristic is controlled by LUBW (subaddress 09H, bit 4) to modify the width of the chrominance ‘notch’ without influencing the chrominance path. The programmable frequency characteristics available, in conjunction with the LCBW2 to LCBW0 settings, can be seen in Figs 21 to 24. It should be noted that these frequency curves are only valid for Y comb disabled filter mode (YCOMB = 0). In comb filter mode the frequency response is flat. The centre frequency of the notch is automatically adapted to the chosen colour standard.

The interpolated CB-CR samples are multiplied by two time-multiplexed subcarrier signals from the subcarrier generation block 2. This second DTO is locked to the first subcarrier generator by an increment delay circuit matched to the processing delay, which is different for PAL and NTSC standards according to the chosen comb filter algorithm. The two modulated signals are finally added to create the re-modulated chrominance signal.

The frequency characteristic of the separated luminance signal can be further modified by the succeeding luminance filter block. It can be configured as peaking (resolution enhancement) or low-pass block by LUFI3 to LUFI0 (subaddress 09H, bits 3 to 0). The 16 resulting frequency characteristics can be seen in Fig.25. The LUFI3 to LUFI0 settings can be used as a user programmable sharpness control.

The luminance filter block also contains the adjustable Y delay part; programmable by YDEL2 to YDEL0 (subaddress 11H, bits 2 to 0).

2004 Jun 29 41

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

(1) LCBW[2:0] = 000. (2) LCBW[2:0] = 010. (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110.

(5) LCBW[2:0] = 001. (6) LCBW[2:0] = 011. (7) LCBW[2:0] = 101. (8) LCBW[2:0] = 111.

(dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−48

−51

−54

−57

−60

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

(dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−48

−51

−54

−57

−60

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

(1) (2) (3) (4)

(5) (6) (7) (8)

MHB535

f (MHz)

Fig.21 Transfer characteristics of the luminance notch filter in 3.58 MHz mode (Y-comb filter disabled) at

LUBW = 0.

2004 Jun 29 42

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

(1) LCBW[2:0] = 000 (2) LCBW[2:0] = 010 (3) LCBW[2:0] = 100 (4) LCBW[2:0] = 110

(5) LCBW[2:0] = 001 (6) LCBW[2:0] = 011 (7) LCBW[2:0] = 101 (8) LCBW[2:0] = 111

(dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−48

−51

−54

−57

−60

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

(dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−48

−51

−54

−57

−60

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

(1) (2) (3) (4)

(5) (6) (7) (8)

MHB536

f (MHz)

Fig.22 Transfer characteristics of the luminance notch filter in 3.58 MHz mode (Y-comb filter disabled) at

LUBW =1.

2004 Jun 29 43

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

(1) LCBW[2:0] = 000. (2) LCBW[2:0] = 010. (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110.

(5) LCBW[2:0] = 001. (6) LCBW[2:0] = 011. (7) LCBW[2:0] = 101. (8) LCBW[2:0] = 111.

(dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−48

−51

−54

−57

−60

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

(dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−48

−51

−54

−57

−60

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

(1) (2) (3) (4)

(5) (6) (7) (8)

MHB537

f (MHz)

Fig.23 Transfer characteristics of the luminance notch filter in 4.43 MHz mode (Y-comb filter disabled) at

LUBW = 0.

2004 Jun 29 44

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

(1) LCBW[2:0] = 000. (2) LCBW[2:0] = 010. (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110.

(5) LCBW[2:0] = 001. (6) LCBW[2:0] = 011. (7) LCBW[2:0] = 101. (8) LCBW[2:0] = 111.

(dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−48

−51

−54

−57

−60

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

(dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−48

−51

−54

−57

−60

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

(1) (2) (3) (4)

(5) (6) (7) (8)

MHB538

f (MHz)

Fig.24 Transfer characteristics of the luminance notch filter in 4.43 MHz mode (Y-comb filter disabled) at

LUBW = 1.

2004 Jun 29 45

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

(1) LUFI[3:0] = 0001. (2) LUFI[3:0] = 0010. (3) LUFI[3:0] = 0011. (4) LUFI[3:0] = 0100. (5) LUFI[3:0] = 0101. (6) LUFI[3:0] = 0110. (7) LUFI[3:0] = 0111. (8) LUFI[3:0] = 0000.

(9) LUFI[3:0] = 1000. (10) LUFI[3:0] = 1001. (11) LUFI[3:0] = 1010. (12) LUFI[3:0] = 1011. (13) LUFI[3:0] = 1100. (14) LUFI[3:0] = 1101. (15) LUFI[3:0] = 1110. (16) LUFI[3:0] = 1111.

(dB)

(1) (2) (3) (4) (5) (6) (7) (8)

−1 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

f (MHz)

(dB)

−3

−6

−9

−12

−15

−18

(9) (10) (11) (12) (13) (14) (15) (16)

−21

−24

−27

−30

−33

−36

−39

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

f (MHz)

MHB539

Fig.25 Transfer characteristics of the luminance peaking/low-pass filter (sharpness).

2004 Jun 29 46

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

9.1.3.3 Brightness Contrast Saturation (BCS) control and decoder output levels

The resulting Y (CVBS) and CB-CR signals are fed to the BCS block, which contains the following functions:

• Chrominance saturation control by DSAT7 to DSAT0

• Luminance contrast and brightness control by DCON7 to DCON0 and DBRI7 to DBRI0

• Raw data (CVBS) gain and offset adjustment by RAWG7 to RAWG0 and RAWO7 to RAWO0

• Limiting Y-CB-CR or CVBS to the values 1 (minimum) and 254 (maximum) to fulfil

“ITU Recommendation 601/656”

handbook, full pagewidth

+255 +235

+128

LUMINANCE 100%

+16

white

black

+255 +240

+212 +212

+128

CB-COMPONENT

+44 +16

blue 100% blue 75%

colourless

yellow 75% yellow 100%

a. Y output range. b. CB output range. c. CR output range.

“ITU Recommendation 601/656”

Equations for modification to the Y-CB-CR levels via BCS control I2C-bus bytes DBRI, DCON and DSAT.

Luminance:

Chrominance:

It should be noted that the resulting levels are limited to 1 to 254 in accordance with

OUT

CRCB()

OUT

digital levels with default BCS (decoder) settings DCON[7:0] = 44H, DBRI[7:0] = 80H and DSAT[7:0] = 40H.

DCON

Int

-----------------

Int

DSAT

--------------- 64

Y 128–()× DBRI+=

CRCB, 128–()× 128+=

“ITU Recommendation 601/656”

+255 +240

+128

CR-COMPONENT

+44 +16

red 100% red 75%

colourless

cyan 75%

cyan 100%

MHB730

Fig.26 Y-CB-CR range for scaler input and X port output.

2004 Jun 29 47

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

+255 +209

+71 +60

LUMINANCE

SYNC

white

black black shoulder

sync bottom

+255

+199

+60

white

LUMINANCE

black shoulder = black

SYNC

sync bottom

MGD700

a. Sources containing 7.5 IRE black level offset (e.g. NTSC M). b. Sources not containing black level offset.

CVBS levels with default settings RAWG[7:0] = 64 and RAWO[7:0] = 128. Equation for modification of the raw data levels via bytes RAWG and RAWO:

RAWG

OUT

Int

------------------

CVBS

It should be noted that the resulting levels are limited to 1 to 254 in accordance with “

CVBS

nom

128–()× RAWO+=

ITU Recommendation 601/656”

Fig.27 CVBS (raw data) range for scaler input, data slicer and X port output.

2004 Jun 29 48

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

9.1.4 SYNCHRONIZATION The prefiltered luminance signal is fed to the

synchronization stage. Its bandwidth is further reduced to 1 MHz by a low-pass filter. The sync pulses are sliced and fed to the phase detectors where they are compared with the sub-divided clock frequency. The resulting output signal is applied to the loop filter to accumulate all phase deviations. Internal signals (e.g. HCL and HSY) are generated in accordance with analog front-end requirements. The loop filter signal drives an oscillator to generate the line frequency control signal (LFCO); see Fig.28.

The detection of ‘pseudo syncs’ as part of the Macrovision copy protection standard is also done within the synchronization circuit.

The result is reported as flag COPRO within the decoder status byte at subaddress 1FH.

9.1.5 CLOCK GENERATION CIRCUIT The internal CGC generates all clock signals required for

the video input processor.

The internal signal LFCO is a digital-to-analog converted signal provided by the horizontal PLL. It is a multiple of the line frequency:

6.75 MHz = 429 × fH (50 Hz), or

6.75 MHz = 432 × fH (60 Hz).

The LFCO signal is multiplied internally by a factor of 2 and 4 in the PLL circuit (including phase detector, loop filtering, VCO and frequency divider) to obtain the output clock signals. The rectangular output clocks have a 50 % duty cycle.

Table 16 Decoder clock frequencies

CLOCK FREQUENCY (MHz)

XTAL 24.576 or 32.110 LLC 27 LLC2 13.5 LLC4 (internal) 6.75 LLC8 (virtual) 3.375

LFCO

BAND PASS

FC = LLC/4

ZERO

CROSS

DETECTION

PHASE

DETECTION

LOOP

FILTER

DIVIDER

1/2

OSCILLATOR

DIVIDER

1/2

MHB330

LLC

LLC2

Fig.28 Block diagram of the clock generation circuit.

9.1.6 POWER-ON RESET AND CE INPUT Amissingclock,insufficient digital or analog V

supplyvoltages(below 2.7 V) will start the reset sequence; all outputs

DDAd

are forced to 3-state (see Fig.29). The indicator output RESd is LOW for approximately 128 LLC after the internal reset and can be applied to reset other circuits of the digital TV system.

It is possible to force a reset by pulling the Chip Enable (CE) to ground. After the rising edge of CE and sufficient power supply voltage, the outputs LLC, LLC2 and SDAd return from 3-state to active, while the other signals have to be activated via programming.

2004 Jun 29 49

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

XTALO

LLCINT

RESINT

CLOCK

PLL

LLC

POC V

ANALOG

POC

LOGIC

DDA

RESINT

POC V

DIGITAL

POC

DELAY

CLK0

DDD

RES

LLC

RES

(internal

reset)

POC = Power-on Control. CE = chip enable input. XTALO = crystal oscillator output. LLCINT = internal system clock. RESINT = internal reset. LLC = line-locked clock output. RES = reset output.

some ms

20 to 200 µs

PLL-delay

1 ms

Fig.29 Power-on control circuit.

2004 Jun 29 50

896 LCC

digital delay

128 LCC

MHB331

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

9.2 Decoder output formatter

The output interface block of the decoder part contains the ITU 656 formatter for the expansion port data output XPD7 to XPD0 (see Section 10.4.1) and the control circuit for the signals needed for the internal paths to the scaler and data slicer part. It also controls the selection of the reference signals for the RT port (RTCO, RTS0 and RTS1) and the expansion port (XRH, XRV and XDQ).

The generation of the decoder data type control signals SET_RAW and SET VBI is also done within this block. These signals are decoded from the requested data type for the scaler input and/or the data slicer, selectable by the control registers LCR2 to LCR24; see Section 18.2.4.2.

Table 17 Data formats at decoder output

DATA TYPE NUMBER DATA TYPE DECODER OUTPUT DATA FORMAT

0 teletext EuroWST, CCST raw 1 European Closed Caption raw 2 Video Programming Service (VPS) raw 3 Wide screen signalling bits raw 4 US teletext (WST) raw 5 US Closed Caption (line 21) raw 6 video component signal, VBI region Y-CB-CR4:2:2 7 CVBS data raw 8 teletext raw

9 VITC/EBU time codes (Europe) raw 10 VITC/SMPTE time codes (USA) raw 11 reserved raw 12 US NABTS raw 13 MOJI (Japanese) raw 14 Japanese format switch (L20/22) raw 15 video component signal, active video region Y-CB-CR4:2:2

For each LCR value, from 2 to 23, the data type can be programmed individually. LCR2 to LCR23 refer to line numbers. The selection in LCR24 values is valid for the rest of the corresponding field. The upper nibble contains the value for field 1 (odd), the lower nibble for field 2 (even). The relationship between LCR values and line numbers can be adjusted via VOFF8 to VOFF0, located in subaddresses 5BH (bit 4) and 5AH (bits 7 to 0) and FOFF subaddress 5BH (bit 7). The recommended values are VOFF[8:0] = 03H for 50 Hz sources (with FOFF = 0) and VOFF[8:0] = 06H for 60 Hz sources (with FOFF = 1), to accommodate line number conventions as used for PAL, SECAM and NTSC standards; see Tables 18 to 21.

2004 Jun 29 51

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2004 Jun 29 52

Table 18 Relationship of LCR to line numbers in 525 lines/60 Hz systems (part 1) Vertical line offset, VOFF[8:0] = 06H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and

59H[7:0]); FOFF = 1 (subaddress 5BH[7])

Linenumber (1st ﬁeld)

Linenumber (2nd ﬁeld)

LCR 24 23456789

Table 19 Relationship of LCR to line numbers in 525 lines/60 Hz systems (part 2)

Vertical line offset, VOFF[8:0] = 06H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and 59H[7:0]); FOFF = 1 (subaddress 5BH[7])

Linenumber (1st ﬁeld)

Linenumber (2nd ﬁeld)

LCR 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

521 522 523 524 525 1 2 3 4 5 6 7 8 9

active video equalization pulses serration pulses equalization pulses

259 260 261 262 263 264 265 266 267 268 269 270 271 272

active video equalization pulses serration pulses equalization pulses

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

nominal VBI lines F1 active video

273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288

nominal VBI lines F2 active video

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

Table 20 Relationship of LCR to line numbers in 625 lines/50 Hz systems (part 1) Vertical line offset, VOFF[8:0] = 03H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and

59H[7:0]); FOFF = 0 (subaddress 5BH[7])

Linenumber (1st ﬁeld)

Linenumber (2nd ﬁeld)

LCR 24 2345

Table 21 Relationship of LCR to line numbers in 625 lines/50 Hz systems (part 2)

Vertical line offset, VOFF[8:0] = 03H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and 59H[7:0]); FOFF = 0 (subaddress 5BH[7])

Linenumber (1st ﬁeld)

Linenumber (2nd ﬁeld)

LCR 67891011121314151617181920212223 24

62162262362462512345

active video equalization pulses serration pulses equalization pulses

309 310 311 312 313 314 315 316 317 318

active video equalization pulses serration pulses equalization pulses

678910111213141516171819202122232425

nominal VBI lines F1 active video

319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338

nominal VBI lines F2 active video

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

625

ITU counting

single field counting

CVBS

HREF

F_ITU656

(1)

V123

622 309

623 310

624 311

312

...

VGATE

FID

ITU counting

single field counting

CVBS

HREF

F_ITU656

(1)

V123

VGATE

FID

VSTO[8:0] = 134H

310

309

310

309

VSTO[8:0] = 134H

311 311

312 312

(a) 1st field

313

31413152316331743185319

313

(b) 2nd field

VSTA[8:0] = 15H

336

335

...

VSTA[8:0] = 15H

MHB540

(1) The inactive going edge of the V123 signal indicates whether the field is odd or even. If HREF is active during

the falling edge of V123, the field is ODD (field 1). If HREF is inactive during the falling edge of V123, the field is EVEN. The specific position of the slope is dependent on the internal processing delay and may change a few clock cycles from version to version.

The control signals listed above are available on pins RTS0, RTS1, XRH and XRV according to the following table:

NAME RTS0 (PIN K13) RTS1 (PIN L10) XRH (PIN N2) XRV (PIN L5)

HREF X X X − F_ITU656 −−−X V123 X X − X VGATE X X −− FID X X −−

For further information see programming section, Tables 171, 172 and 173.

Fig.30 Vertical timing diagram for 50 Hz/625 line systems.

2004 Jun 29 53

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

ITU counting

single field counting

CVBS

HREF

F_ITU656

(1)

V123

525 262

1 1

9910

...

VGATE

FID

ITU counting

single field counting

CVBS

HREF

F_ITU656

(1)

V123

VGATE

FID

VSTO[8:0] = 101H

263

262

263

262

VSTO[8:0] = 101H

264

(a) 1st field

265

266326742685269627072718272

(b) 2nd field

VSTA[8:0] = 011H

285

284

...

VSTA[8:0] = 011H

MHB541

(1) The inactive going edge of the V123 signal indicates whether the field is odd or even. If HREF is active during

The control signals listed above are available on pins RTS0, RTS1, XRH and XRV according to the following table:

NAME RTS0 (PIN K13 RTS1 (PIN L10) XRH (PIN N2) XRV (PIN L5)

HREF X X X − F_ITU656 −−−X V123 X X − X VGATE X X −− FID X X −−

For further information see programming section, Tables 171, 172 and 173.

Fig.31 Vertical timing diagram for 60 Hz/525 line systems.

2004 Jun 29 54

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

CVBS input

expansion port

data output

HREF (50 Hz)

CREF

CREF2

HS (50 Hz)

programming range

(step size: 8/LLC)

HREF (60 Hz)

CREF

108

burst

processing delay ADC to expansion port:

140 × 1/LLC

12 × 2/LLC

720 × 2/LLC

5 × 2/LLC

720 × 2/LLC

144 × 2/LLC

16 × 2/LLC

138 × 2/LLC

sync clipped

2 × 2/LLC

−107

CREF2

HS (60 Hz)

programming range

(step size: 8/LLC)

Thesignals HREF, HS,CREF2 and CREFare available on pinsRTS0 and/or RTS1(see Section 18.2.2.19 Tables 171 and 172); their polarity can be inverted via RTP0 and/or RTP1.

The signals HREF and HS are available on pin XRH (see Section 18.2.2.20 Table 173).

107

1 × 2/LLC

2 × 2/LLC

Fig.32 Horizontal timing diagram (50/60 Hz).

2004 Jun 29 55

−106

MHB542

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

9.3 Scaler

TheHigh Performance video Scaler (HPS) is based on the system as implemented in the SAA7140, but enhanced in some aspects. Vertical upsampling is supported and the processing pipeline buffer capacity is enhanced, to allow more flexible video stream timing at the image port, discontinuous transfers and handshake. The internal data flow from block to block is discontinuous dynamically, due to the scaling process.

The flow is controlled by internal data valid and data request flags (internal handshake signalling) between the sub-blocks. Therefore the entire scaler acts as a pipeline buffer. Depending on the actually programmed scaling parameters the effective buffer can exceed to an entire line. The access/bandwidth requirements to the VGA frame buffer are reduced significantly.

The high performance video scaler in the SAA7108AE; SAA7109AE has the following major blocks.

• Acquisition control (horizontal and vertical timer) and task handling (the region/field/frame based processing)

• Prescaler, for horizontal downscaling by an integer factor, combined with appropriate band limiting filters, especially anti-aliasing for CIF format

• Brightness, saturation and contrast control for scaled output data

• Line buffer, with asynchronous read and write, to support vertical upscaling (e.g. for videophone application, converting 240 into 288 lines, Y-CB-C 4:2:2)

• Vertical scaling, with phase accurate Linear Phase Interpolation (LPI) for zoom and downscaling, or phase accurate Accumulation Mode (ACM) for large downscaling ratios and better anti-alias suppression

• Variable Phase Delay (VPD), operates as horizontal phase accurate interpolation for arbitrary non-integer scaling ratios, supporting conversion between square and rectangular pixel sampling

• Output formatter for scaled Y-CB-CR4:2:2, Y-CB-CR4:1:1 and Y only (format also for raw data)

• FIFO, 32-bit wide, with 64 pixel capacity in Y-CB-C formats

• Output interface, 8 or 16-bit (only if extended by H port) data pins wide, synchronous or asynchronous operation, with stream events on discrete pins, or coded in the data stream.

The overall H and V zooming (HV_zoom) is restricted by the input/output data rate relationships. With a safety margin of 2 % for running in and running out, the maximum HV_zoom is equal to:

0.98

-------------------------------------------------------------------------------------------------------------------------------------in_pixel in_lines× out_cycle_per_pix× T_out_clk×

For example:

1. Input from decoder: 50 Hz, 720 pixel, 288 lines, 16-bit data at 13.5 MHz data rate, 1 cycle per pixel; output: 8-bit data at 27 MHz, 2 cycles per pixel; the maximum HV_zoom is equal to:

0.98

2. Input from X port: 60 Hz, 720 pixel, 240 lines, 8-bit data at 27 MHz data rate (ITU 656), 2 cycles per pixel; output via I + H port: 16-bit data at 27 MHz clock, 1 cycle per pixel; the maximum HV_zoom is equal to:

0.98

The video scaler receives its input signal from the video decoder or from the expansion port (X port). It gets 16-bit Y-CB-CR4:2:2 input data at a continuous rate of

13.5 MHz from the decoder. A discontinuous data stream

can be accepted from the expansion port, normally 8-bit wide ITU 656 like Y-CB-CRdata, accompanied by a pixel qualifier on XDQ.

Theinputdatastreamissortedinto two data paths, one for luminance (or raw samples), and one for time multiplexed chrominance CBand CR samples. A Y-CB-CR4:1:1 input format is converted to 4 :2:2 for the horizontal prescaling and vertical filter scaling operation.

Thescaler operation is defined bytwoprogramming pages A and B, representing two different tasks that can be applied field alternating or to define two regions in a field (e.g. with different scaling range, factors, and signal source during odd and even fields).

Each programming page contains control for:

• Signal source selection and formats

• Task handling and trigger conditions

• Input and output acquisition window definition

• H prescaler, V scaler and H phase scaling.

Raw VBI data will be handled as specific input format and need its own programming page (equals own task).

T_input_field T_v_blanking–

20 ms 24 64 µs×–

-------------------------------------------------------720 288× 2× 37 ns×

16.666 ms 22 64 µs×–

-------------------------------------------------------------720 240× 1× 37 ns×

1.18=×

2.34=×

2004 Jun 29 56

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

In VBI pass through operation the processing of prescaler and vertical scaling has to be disabled, however the horizontal fine scaling VPD can be activated. Upscaling (oversampling, zooming), free of frequency folding, up to factor 3.5 can be achieved, as required by some software data slicing algorithms.

These raw samples are transported through the image port as valid data and can be output as Y only format. The lines are framed by SAV and EAV codes.

9.3.1 ACQUISITION CONTROL AND TASK HANDLING (SUBADDRESSES 80H, 90H, 91H, 94H TO 9FH

AND C4H TO CFH)

The acquisition control receives horizontal and vertical synchronization signals from the decoder section or from the X port. The acquisition window is generated via pixel and line counters at the appropriate places in the data path. Only qualified pixels and lines (lines with qualified pixel) are counted from the X port.

The acquisition window parameters are as follows:

• Signal source selection: input video stream and formats

from the decoder, or from the X port (programming bits SCSRC[1:0] 91H[5:4] and FSC[2:0] 91H[2:0])

Remark: The input of raw VBI data from the internal decoder should be controlled via the decoder output formatter and the LCR registers (see Section 9.2)

• Vertical offset: defined in lines of the video source,

parameter YO[11:0] 99H[3:0] 98H[7:0]

• Vertical length: defined in lines of the video source,

parameter YS[11:0] 9BH[3:0] 9AH[7:0]

• Vertical length: defined in number of target lines, as a

result of vertical scaling, parameter YD[11:0] 9FH[3:0] 9EH[7:0]

• Horizontal offset: defined in number of pixels of the

video source, parameter XO[11:0] 95H[3:0] 94H[7:0]

• Horizontal length: defined in number of pixels of the

video source, parameter XS[11:0] 97H[3:0] 96H[7:0]

• Horizontal destination size: defined in target pixels after

fine scaling, parameter XD[11:0] 9DH[3:0] 9CH[7:0].

9.3.1.1 Input ﬁeld processing

The trigger event for the field sequence detection from external signals (X port) are defined in subaddress 92H. The state of the scalers horizontal reference signal at the time of the vertical reference edge is taken from the X port asfield sequence identifier (FID).Forexample, if the falling edge of the XRV input signal is the reference and the state of XRH input is logic 0 at that time, the detected field ID is logic 0.

The bits XFDV[92H[7]] and XFDH[92H[6]] define the detection event and state of the flag from the X port. For the default setting of XFDV and XFDH at ‘00’ is taken from the state of the horizontal input at the falling edge of the vertical input.

The scaler gets corresponding field ID information directly from the SAA7108AE; SAA7109AE decoder path.

The FID flag is used to determine whether the first or second field of a frame is going to be processed within the scaler, and it is also used as trigger conditions for the task handling (see bits STRC[1:0] 90H[1:0]).

According to ITU 656, FID at logic 0 means first field of a frame. To ease the application, the polarities of the detection results on the X port signals and the internal decoder ID can be changed via XFDH.

As the V sync from the decoder path has a half line timing (due to the interlaced video signal), but the scaler processing only recognises full lines, during 1st fields from the decoder the line count of the scaler can possibly shift by one line, compared to the 2nd field. This can be compensated for by switching the vertical trigger event, as defined by XDV0, to the opposite V sync edge or by using theverticalscalersphaseoffsets.Theverticaltimingofthe decoder can be seen in Figs 30 and 31.

As the horizontal and vertical reference events inside the ITU 656 data stream (from X port) and the real-time reference signals from the decoder path are processed differently, the trigger events for the input acquisition also have to be programmed differently.

The source start offset XO(11:0) and YO(11:0) opens the acquisition window, and the target size (XD11 to XD0, YD11 to YD0) closes the window, however the window is cut vertically if there are less output lines than required. The trigger events for the pixel and line counts are the horizontal and vertical reference edges as defined in subaddress 92H.

The task handling is controlled by subaddress 90H; see Section 9.3.1.2.

2004 Jun 29 57

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

Table 22 Processing trigger and start

XDV1

92H[5]

0 1 0 4/7 (50/60 Hz, 1st field), respectively 3/6 (50/60 Hz, 2nd field) (decoder count) 0 0 0 2/5 (50/60 Hz, 1st field), respectively 2/5 (50/60 Hz, 2nd field) (decoder count) 000External ITU 656 stream: The processing starts earliest with SAV at line number 23

9.3.1.2 Task handling

The task handler controls the switching between the two programming register sets. It is controlled by subaddresses 90H and C0H. A task is enabled via the global control bits TEA[80H[4]] and TEB[80H[5]]. The handler is then triggered by events which can be defined for each register set.

In the event of a programming error the task handling and the complete scaler can be reset to the initial states by the software reset bit SWRST[88H[5]] being set to logic 0. A software reset must be done after programming especiallyiftheprogrammingregisters,relatedacquisition window and scaler are reprogrammed while a task is active.

The difference in the disabling/enabling of a task, which is evaluatedat the end of a runningtask(whenSWRST is set to logic 0) is that it sets the internal state machines directly to their idle states.

The start condition for the handler is defined by bits STRC[1:0]90H[1:0]andmeans: start immediately, wait for next V sync, next FID at logic 0 or next FID at logic 1. The FID is evaluated if the vertical and horizontal offsets are reached.

XDV0

92H[4]

XDH

92H[2]

DESCRIPTION

Internal decoder: The processing triggers at the falling edge of the V123 pulse

(see Figs 30 (50 Hz) and 31 (60 Hz)), and starts earliest with the rising edge of the decoder HREF at line number:

(50 Hz system), respectively line 20 (60 Hz system) (according ITU 656 count)

Remarks:

• To activate a task, the start condition must be

fulfilled and the acquisition window offsets must be reached. For example, in case of ‘start immediately’,

and two regions are defined for one field, the offset of thelower region must be greater than(offset + length)of the upper region, if not, the actual counted H and V position at the end of the upper task is beyond the programmed offsets and the processing will ‘wait for next V’.

• Basically,thetrigger conditions are checked when a task is activated. It is important to know that they are

not checked while a task is inactive. So it is not possible to trigger to the next logic 0 or logic 1 with overlapping offset and active video ranges between the tasks (e.g. task A STRC[2:0] = 2, YO[11:0] = 310 and task B STRC[2:0] = 3, YO[11:0] = 310 results in an output field rate of50⁄3Hz).

• After power-on or software reset (via SWRST[88H[5]]) task B gets priority over task A.

With RPTSK[90H[2]] at logic 1 the actual running task is repeated (under the defined trigger conditions) before handing control over to the alternate task.

To support field rate reduction, the handler is also enabled to skip fields (bits FSKP[2:0] 90H[5:3]) before executing thetask.ATOGGLEflag is generated (used for the correct output field processing), which changes state at the beginning of a task every time a task is activated; examples are given in Section 9.3.1.3.

2004 Jun 29 58

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

9.3.1.3 Output ﬁeld processing

As a reference for the output field processing, two signals are available for the back-end hardware.

These signals are the input field ID from the scaler source and a TOGGLE flag, which shows that an active task is used an odd (1, 3, 5...) or even (2, 4, 6...) number of times. Usingasingleorbothtasksand reducing the field or frame rate with the task handling functionality, the TOGGLE information can be used to reconstruct an interlaced scaled picture at a reduced frame rate. The TOGGLE flag is not synchronized to the input field detection, as it is only dependent on the interpretation of this information by the external hardware i.e. whether the output of the scaler is processed correctly; see Section 9.3.3.

When OFIDC = 0, the scalers input field ID is available as output field ID on bit 6 of SAV and EAV, and respectively on pin IGP0 (IGP1), if the FID output is selected.

When OFIDC[90H[6]] = 1, the TOGGLE information is available as output field ID on bit 6 of SAV and EAV, and respectively on pin IGP0 (IGP1) if the FID output is selected.

Additionally bit 7 of SAV and EAV can be defined via CONLH[90H[7]]. When CONLH[90H[7]] = 0 (default) it sets bit 7 to logic 1; a logic 1 inverts the SAV/EAV bit 7. So it is possible to mark the output of both tasks by different SAV/EAV codes. This bit can also be seen as ‘task flag’ on pins IGP0 (IGP1), if the TASK output is selected.

2004 Jun 29 59

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2004 Jun 29 60

Table 23 Example for ﬁeld processing

FIELD SEQUENCE FRAME/FIELD

SUBJECT

EXAMPLE 1

(1)

EXAMPLE 2

(2)(3)

EXAMPLE 3

(2)(4)(5)

EXAMPLE 4

(2)(4)(6)

1/1 1/2 2/1 1/1 1/2 2/1 2/2 1/1 1/2 2/1 2/2 3/1 3/2 1/1 1/2 2/1 2/2 3/1 3/2

Processed by task A A A B A B A B B A B B A B B A B B A State of detected

0100101010101 0 10 1 01

ITU 656 FID TOGGLE ﬂag 1 0 1 1 1 0 0 1 0 1 1 0 0 0 Bit 6 of SAV/EAV byte 0 1 0 0 1 0 1 1 0 1 1 0 0 0 Required sequence

conversion at the vertical

(8)

scaler

(9)

Output

↓

OOOOOOOOOOOOONOOONOOO

(7) (7)

↓

111 111

↓

(7) (7)

↓

Notes

1. Single task every field; OFIDC = 0; subaddress 90H at 40H; TEB[80H[5]] = 0.

2. Tasks are used to scale to different output windows, priority on task B after SWRST.

3. Both tasks at1⁄2frame rate; OFIDC = 0; subaddresses 90H at 43H and C0H at 42H.

4. In examples 3 and 4 the association between input FID and tasks can be flipped, dependent on which time the SWRST is de-asserted.

5. Task B at2⁄3frame rate constructed from neighbouring motion phases; task A at1⁄3frame rate of equidistant motion phases; OFIDC = 1; subaddresses 90H at 41H and C0H at 45H.

6. Task A and B at1⁄3frame rate of equidistant motion phases; OFIDC = 1; subaddresses 90H at 41H and C0H at 49H.

7. State of prior field.

8. It is assumed that input/output FID = 0 (upper lines); UP = upper lines; LO = lower lines.

9. O = data output; NO = no output.

00 00

↓

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

9.3.2 HORIZONTAL SCALING The overall horizontal scaling factor has to be split into a

binary and a rational value according to the following equation:

H scale ratio

--------------------------- XPSC[5:0]

output pixel

-----------------------------input pixel

1024

×=

------------------------------XSCY[12:0]

where,the parameter of the prescaler XPSC[5:0] = 1 to 63 and the parameter of VPD phase interpolation XSCY[12:0] = 300 to 8191 (0 to 299 are only theoretical values). For example,1⁄

is split into1⁄4× 1.14286. The

3.5

binary factor is processed by the prescaler, the arbitrary non-integer ratio is achieved via the variable phase delay VPD circuitry, called horizontal fine scaling. The latter calculates horizontally interpolated new samples with a 6-bit phase accuracy, which relates to less than 1 ns jitter for regular sampling schemes. Together the prescaler and fine scaler form the horizontal scaler of the SAA7108AE; SAA7109AE.

Using the accumulation length function of the prescaler (XACL[5:0] A1H[5:0]), application and destination dependent (e.g. scale for display or for a compression machine), a compromise between visible bandwidth and alias suppression can be found.

• The bit XC2_1[A2H[3]], which defines the weighting of the incoming pixels during the averaging process

– XC2_1 = 0 ⇒ 1 + 1...+ 1 + 1 – XC2_1 = 1 ⇒ 1 + 2...+ 2 + 1.

Theprescaler creates a prescaledependent FIR low-pass, with up to 64 + 7 filter taps. The parameter XACL[5:0] can be used to vary the low-pass characteristic for a given integer prescale of1⁄

XPSC[5:0]

. The user can therewith decide between signal bandwidth (sharpness impression) and alias.

The equation for the XPSC[5:0] calculation is:

XPSC[5:0] lower integer of

Npix_in

----------------------Npix_out

Where:

the range is 1 to 63 (value 0 is not allowed); Npix_in = number of input pixel, and Npix_out = number of desired output pixel over the

complete horizontal scaler.

The use of the prescaler results in a XACL[5:0] and XC2_1 dependent gain amplification. The amplification

can be calculated according to the equation: DC gain = [(XACL[5:0] − XC2_1) + 1] × (XC2_1 + 1)

9.3.2.1 Horizontal prescaler (subaddresses A0H to A7H and D0H to D7H)

The prescaling function consists of an FIR anti-alias filter stage and an integer prescaler, which together form an adaptiveprescaledependent low-pass filter to balance the sharpness and aliasing effects.

The FIR pre-filter stage implements different low-pass characteristics to reduce the anti-alias for downscales in the range of 1 to1⁄2. A CIF optimized filter is built-in, which reduces artefacts for CIF output formats (to be used in combination with the prescaler set to1⁄2scale); see Table 24.

The function of the prescaler is defined by:

• An integer prescaling ratio XPSC[5:0] A0H[5:0] (equals

1 to 63), which covers the integer downscale range 1to1⁄

• An averaging sequence length XACL[5:0] A1H[5:0]

(equals 0 to 63); range 1 to 64

• A DC gain renormalization XDCG[2:0] A2H[2:0];

1 down to1⁄

128

)

It is recommended to use sequence lengths and weights,

which results in a 2

DC gain amplification, as these

amplitudes can be renormalized by the XDCG[2:0] controlled shifter of the prescaler.

The renormalization range of XDCG[2:0] is 1, to1⁄

128

------

⁄2... down

Other amplifications have to be normalized by using the following BCS control circuitry. In these cases the prescaler has to be set to an overall gain ≤1, e.g. for an accumulation sequence of ‘1 + 1 + 1’ (XACL[5:0] = 2 and XC2_1 = 0), XDCG[2:0] must be set to ‘010’, which equals1⁄4 and the BCS has to amplify the signal to4⁄

(SATN[7:0] and CONT[7:0] value = lower integer of

⁄3× 64).

The use of XACL[5:0] is XPSC[5:0] dependent. XACL[5:0] must be <2 × XPSC[5:0].

XACL[5:0] can be used to find a compromise between bandwidth (sharpness) and alias effects.

2004 Jun 29 61

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Remark: Due to bandwidth considerations XPSC[5:0] and XACL[5:0] can be chosen differently to the previously mentioned equations or Table 25, as the horizontal phase scaling is able to scale in the range from zooming up by factor 3 to downscaling by a factor of

1024

⁄

8191

Figs 35 and 36 show some frequency characteristics of the prescaler.

Table 25 shows the recommended prescaler programming.Otherprogramming, than given in Table 25, may result in better alias suppression, but the resulting DC gain amplification needs to be compensated by the BCS control, according to the equation:

XDCG[2:0]

CONT[7:0] SATN[7:0] lower integer of

---------------------------------DC gain 64×

Where:

XDCG[2:0]

≥ DC gain

DC gain = (XC2_1 + 1) × XACL[5:0] + (1 − XC2_1).

Table 24 FIR preﬁlter functions

PFUV[1:0] A2H[7:6]

PFY[1:0] A2H[5:4]

LUMINANCE FILTER

COEFFICIENTS

00 bypassed bypassed 01 121 121 10 −1 1 1.75 4.5 1.75 1 −1 381083 11 12221 12221

For example, if XACL[5:0] = 5, XC2_1 = 1, then DC gain = 10 and the required XDCG[2:0] = 4.

The horizontal source acquisition timing and the prescaling ratio is identical for both the luminance and chrominance path, but the FIR filter settings can be defined differently in the two channels.

Fade-in and fade-out of the filters is achieved by copying an original source sample each as first and last pixel after prescaling.

Figs 33 and 34 show the frequency characteristics of the selectable FIR filters.

CHROMINANCE COEFFICIENTS

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HD-CODEC SAA7108AE; SAA7109AE

(1) PFY[1:0] = 01. (2) PFY[1:0] = 10. (3) PFY[1:0] = 11.

(dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

(3)

(1)

(2)

f_sig/f_clock

Fig.33 Luminance prefilter characteristic.

MHB543

(1) PFUV[1:0] = 01. (2) PFUV[1:0] = 10. (3) PFUV[1:0] = 11.

(dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2 0.225 0.25

(1)

(2)

(3)

f_sig/f_clock

Fig.34 Chrominance prefilter characteristic.

MHB544

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Philips Semiconductors Product speciﬁcation

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XC2_1 = 0; Zero’s at

×=

------------------------ XACL 1+

with XACL = (1), (2), (3), (4) or (5)

Fig.35 Examples for prescaler filter characteristics: effect of increasing XACL[5:0].

(dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

(1)(2)(3)(4)(5)

MHB545

f_sig/f_clock

(1) XC2_1 = 0 and

XACL[5:0] = 1.

(2) XC2_1 = 1 and

XACL[5:0] = 2.

(3) XC2_1 = 0 and

XACL[5:0] = 3.

(4) XC2_1 = 1 and

XACL[5:0] = 4.

(5) XC2_1 = 0 and

XACL[5:0] = 7.

(6) XC2_1 = 1 and

XACL[5:0] = 8.

(dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

(1)

(2)

(3)(4)(5)(6)

3 dB at 0.25

6 dB at 0.33

Fig.36 Examples for prescaler filter characteristics: setting XC2_1 = 1.

MHB546

f_sig/f_clock

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Table 25 Example of XACL[5:0] usage

PRESCALE

RATIO

XPSC

[5:0]

RECOMMENDED VALUES

FOR LOWER BANDWIDTH

REQUIREMENTS

FOR HIGHER BANDWIDTH

REQUIREMENTS

XACL[5:0] XC2_1 XDCG[2:0] XACL[5:0] XC2_1 XDCG[2:0]

FIR

PREFILTER

PFY[1:0]/

PFUV[1:0]

110 0 0 0 0 0 0to2

⁄

2 2 1 2 1 0 1 0 to 2

(1 2 1) ×1⁄

(1)

(1 1) ×1⁄

(1)

34 1 3 3 0 2 2

(12221)×1⁄

(1)

(1 1 1 1) ×1⁄

(1)

47 0 3 4 1 3 2

(11111111)×1⁄

(1)

(12221)×1⁄

(1)

58 1 4 7 0 3 2

(122222221)×1⁄

(1)

(11111111)×1⁄

(1)

68 1 4 7 0 3 3

(122222221)×1⁄

(1)

(11111111)×1⁄

(1)

78 1 4 7 0 3 3

(122222221)×1⁄

(1)

(11111111)×1⁄

(1)

815 0 4 8 1 4 3

(1111111111111111)×1⁄

(1)

(122222221)×1⁄

(1)

915 0 4 8 1 4 3

(1111111111111111)×1⁄

(1)

(122222221)×1⁄

(1)

10 16 1 5 8 1 4 3

(12222222222222221)×1⁄

(1)

(122222221)×1⁄

(1)

13 16 1 5 16 1 5 3 15 31 0 5 16 1 5 3 16 31 0 5 16 1 5 3 19 32 1 6 32 1 6 3 31 32 1 6 32 1 6 3 32 63 1 7 32 1 6 3 35 63 1 7 63 1 7 3

Note

1. Resulting FIR function.

2004 Jun 29 65

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9.3.2.2 Horizontal ﬁne scaling (variable phase delay ﬁlter; subaddresses A8H to AFH and D8H to DFH)

Thehorizontal fine scaling (VPD) shouldoperateat scaling ratios between1⁄2and 2 (0.8 and 1.6), but can also be used for direct scaling in the range from1⁄ (theoretical) zoom 3.5 (restriction due to the internal data path architecture), without prescaler.

In combination with the prescaler a compromise between sharpness impression and alias can be found, which is signal source and application dependent.

For the luminance channel a filter structure with 10 taps is implemented, for the chrominance a filter with 4 taps.

Luminance and chrominance scale increments (XSCY[12:0]A9H[4:0] A8H[7:0] and XSCC[12:0] ADH[4:0] ACH[7:0]) are defined independently, but must be set in a 2 : 1 relationship in the actual data path implementation. The phase offsets XPHY[7:0] AAH[7:0] and XPHC[7:0] AEH[7:0] can be used to shift the sample phases slightly. XPHY[7:0] and XPHC[7:0] covers the phase offset range

7.999T to1⁄32T. The phase offsets should also be

programmed in a 2 : 1 ratio. The underlying phase controlling DTO has a 13-bit

resolution. According to the equations

Npix_in

XSCY[12:0] 1024

XSCC[12:0]

The VPD covers the scale range from 0.125 to zoom 3.5. The VPD acts equivalent to a polyphase filter with 64 possible phases. In combination with the prescaler, it is possible to get high accurate samples from a highly anti-aliased integer downscaled input picture.

--------------------------- XPSC[5:0]

XSCY[12:0]

------------------------------2

×=

----------------------Npix_out

7.999

and

9.3.3.1 Line FIFO buffer (subaddresses 91H, B4H and C1H, E4H)

The line FIFO buffer is a dual ported RAM structure for 768 pixels, with asynchronous write and read access. The line buffer can be used for various functions, but not all functions may be available simultaneously.

Theline buffer can bufferacomplete unscaled active video line or more than one shorter lines (only for non-mirror mode), for selective repetition for vertical zoom-up.

For zooming up from 240 lines to 288 lines e.g., every fourth line is requested (read) twice from the vertical scaling circuitry for calculation.

For conversion of a 4 : 2 : 0 or 4:1:0 input sampling scheme (MPEG, video phone, Indeo YUV-9) to ITU like sampling scheme 4:2:2, the chrominance line buffer is read twice or four times, before being refilled again by the source. By means of the input acquisition window definition it has to be preserved, that the processing starts with a line containing luminance and chrominance information for 4:2:0 and 4:1:0 input. The bits FSC[2:1] 91H[2:1] define the distance between the Y/C lines. In case of 4 :2:2 and 4 : 1 : 1 FSC2 and FSC1 have to be set to ‘00’.

The line buffer can also be used for mirroring, i.e. for flippingtheimage left to right, for the vanity picture in video phone application (bit YMIR[B4H[4]]). In mirror mode only one active prescaled line can be held in the FIFO at a time.

The line buffer can be utilized as excessive pipeline buffer for discontinuous and variable rate transfer conditions at the expansion port or image port.

9.3.3.2 Vertical scaler (subaddresses B0H to BFH and E0H to EFH)

Vertical scaling of any ratio from 64 (theoretical zoom) to1⁄63 (icon) can be applied.

9.3.3 VERTICAL SCALING The vertical scaler of the SAA7108AE; SAA7109AE

decoder part consists of a line FIFO buffer for line repetition and the vertical scaler block, which implements the vertical scaling on the input data stream in 2 different operational modes from theoretical zoom by 64 down to icon size1⁄64. The vertical scaler is located between the BCS and horizontal fine scaler, so that the BCS can be used to compensate for the DC gain amplification of the ACM mode (see Section 9.3.3.2) as the internal RAMs are only 8-bit wide.

2004 Jun 29 66

The vertical scaling block consists of another line delay, and the vertical filter structure, that can operate in two different modes. These are the Linear Phase Interpolation (LPI) and Accumulation (ACM) modes, controlled by YMODE[B4H[0]].

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• LPI mode: In the linear phase interpolation mode (YMODE = 0)two neighbouring linesofthe source video stream are added together, but weighted by factors corresponding to the vertical position (phase) of the target output line relative to the source lines. This linear interpolation has a 6-bit phase resolution, which equals 64 intra line phases. It interpolates between two consecutive input lines only. The LPI mode should be applied for scaling ratios around 1 (down to1⁄2), it must be applied for vertical zooming.

• ACM mode: The vertical Accumulation (ACM) mode (YMODE = 1) represents a vertical averaging window over multiple lines, sliding over the field. This mode also generates phase correct output lines. The averaging windowlengthcorrespondsto the scaling ratio, resulting in an adaptive vertical low-pass effect, to greatly reduce aliasing artefacts. ACM can be applied for downscales only from ratio 1 down to1⁄64. ACM results in a scale dependent DC gain amplification, which has to be precorrected by the BCS control of the scaler part.

The phase and scale controlling DTO calculates in 16-bit resolution, controlled by parameters YSCY[15:0] B1H[7:0] B0H[7:0]and YSCC[15:0]B3H[7:0] B2H[7:0], continuously over the entire filed. A start offset can be applied to the phase processing by means of the parameters YPY3[7:0] to YPY0[7:0] in BFH[7:0] to BCH[7:0] and YPC3[7:0] to YPC0[7:0]inBBH[7:0] to B8H[7:0]. The start phase covers the range of

By programming appropriate, opposite, vertical start phase values (subaddresses B8H to BFH and E8H to EFH)depending on odd/even field ID of the source videostream and A/B page cycle, frameIDconversionand field rate conversion are supported (i.e. de-interlacing, re-interlacing).

Figs 37 and 38 and Tables 26 and 27 describe the use of the offsets.

Remark: The vertical start phase, as well as the scaling ratio are defined independently for luminance and chrominance channels, but must be set to the same values in the actual implementation for accurate 4:2:2 output processing.

The vertical processing communicates on its input side with the line FIFO buffer. The scale related equations are:

• Scaling increment calculation for ACM and LPI mode, downscale and zoom: YSCY[15:0] and YSCC[15:0]

lower integer of= 1024

255

⁄32to1⁄32 lines offset.

 

Nline_in

------------------------Nline_out

• BCS value to compensate DC gain in ACM mode (contrast and saturation have to be set): CONT[7:0] A5H[7:0] respectively SATN[7:0] A6H[7:0]

Nline_out

lower integer of



-------------------------



Nline_in

1024



-------------------------------



YSCY[15:0]

, or

64×

9.3.3.3 Use of the vertical phase offsets

As shown in Section 9.3.1.3, the scaler processing may run randomly over the interlaced input sequence. Additionally the interpretation and timing between ITU 656 field ID and real-time detection by means of the state of H sync at the falling edge of V sync may result in different field ID interpretation.

A vertically scaled interlaced output also gets a larger vertical sampling phase error, if the interlaced input fields are processed, without regard to the actual scale at the starting point of operation (see Fig.37).

The four events to be considered are illustrated in Fig.38. In Tables 26 and 27 PHO is a usable common phase

offset. It should be noted that the equations in Fig.38 also

produce an interpolated output for the unscaled case, as the geometrical reference position for all conversions is the position of the first line of the lower field; see Table 26.

If there is no need for UP-LO and LO-UP conversion and the input field ID is the reference for the back-end operation, then it is UP-LO = UP-UP and LO-UP = LO-LO and the1⁄2line phase shift (PHO + 16) that can be skipped; this case is given in Table 27.

The SAA7108AE; SAA7109AE supports 4 phase offset registers per task and component (luminance and chrominance). The value of 20H represents a phase shift of one line.

The registers are assigned to the following events; e.g. subaddresses B8H to BBH:

• B8H: 00 = input field ID 0, task status bit 0 (toggle status, see Section 9.3.1.3)

• B9H: 01 = input field ID 0, task status bit 1

• BAH: 10 = input field ID 1, task status bit 0

• BBH: 11 = input field ID 1, task status bit 1.

2004 Jun 29 67

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Depending on the input signal (interlaced or non-interlaced) and the task processing (50 Hz or field reduced processing with one or two tasks, see examples in Section 9.3.1.3), other combinations may also be possible, but the basic equations are the same.

unscaled input

ﬁeld 1 ﬁeld 2 ﬁeld 1 ﬁeld 2 ﬁeld 1 ﬁeld 2

scale dependent start offset

scaled output,

no phase offset

mismatched vertical line distances

scaled output,

with phase offset

correct scale dependent position

Fig.37 Basic problem of interlaced vertical scaling (example: downscale3⁄5).

MHB547

2004 Jun 29 68

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

handbook, full pagewidth

Offset

1024

------------ 32

input line shift 16==

-- 2

input line shift

-- 2

ﬁeld 1 ﬁeld 2 upper

B A

32 1 line shift===

scale increment+

-- 2

lower

YSCY[15:0]

------------------------------ -

16+==

ﬁeld 1 ﬁeld 2

case UP-UP

D = no offset = 0

case LO-LO

scale increment

-- 2

ﬁeld 1 ﬁeld 2

case UP-LO

YSCY[15:0]

------------------------------ 64

case LO-UP

MHB548

Fig.38 Derivation of the phase related equations (example: interlace vertical scaling down to3⁄5, with field

conversion).

Table 26 Examples for vertical phase offset usage: global equations

INPUT FIELD UNDER

PROCESSING

OUTPUT FIELD

INTERPRETED AS

USED

ABBREVIATION

EQUATION FOR PHASE OFFSET

CALCULATION (DECIMAL VALUES)

Upper input lines upper output lines UP-UP PHO + 16 Upper input lines lower output lines UP-LO

PHO

Lower input lines upper output lines LO-UP PHO Lower input lines lower output lines LO-LO

PHO

YSCY[15:0]

------------------------------64

YSCY[15:0]

------------------------------64

16++

2004 Jun 29 69

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Table 27 Vertical phase offset usage; assignment of the phase offsets

DETECTED INPUT

FIELD ID

TASK STATUS BIT

0 = upper lines 0 YPY0[7:0] and

0 = upper lines 1 YPY1[7:0] and

VERTICAL PHASE

OFFSET

YPC0[7:0]

YPC1[7:0]

CASE EQUATION TO BE USED

(1)

case 1 case 2 case 3

UP-UP (PHO)

(2)

UP-UP

(3)

UP-LO case 1 UP-UP (PHO) case 2 UP-LO case 3 UP-UP

1 = lower lines 0 YPY2[7:0] and

YPC2[7:0]

case 1

LO-LO



PHO



YSCY[15:0]

------------------------------64

16–+

case 2 LO-UP case 3 LO-LO

1 = lower lines 1 YPY3[7:0] and

YPC3[7:0]

case 1

LO-LO



PHO



YSCY[15:0]

------------------------------64

16–+

case 2 LO-LO case 3 LO-UP

Notes

1. Case 1: OFIDC[90H[6]] = 0; scaler input field ID as output ID; back-end interprets output field ID at logic 0 as upper output lines.

2. Case 2: OFIDC[90H[6]] = 1; task status bit as output ID; back-end interprets output field ID at logic 0 as upper output lines.

3. Case 3: OFIDC[90H[6]] = 1; task status bit as output ID; back-end interprets output field ID at logic 1 as upper output lines.

9.4 VBI data decoder and capture

(subaddresses 40H to 7FH)

The SAA7108AE; SAA7109AE contains a versatile VBI data decoder.

The implementation and programming model accords to the VBI data slicer the built-in multimedia video data acquisition circuit of the SAA5284.

The circuitry recovers the actual clock phase during the clock run-in period, slices the data bits with the selected data rate, and groups them into bytes. The result is buffered into a dedicated VBI data FIFO with a capacity of 2 × 56 bytes (2 × 14 Dwords). The clock frequency, signal source, field frequency and accepted error count must be defined in subaddress 40H.

The VBI data standards that are supported are given in Table 28.

2004 Jun 29 70

For lines 2 to 24 of a field, per VBI line, 1 of 16 standards can be selected (LCRxxx[41:57[7:0]]: 23 × 2 × 4-bit programming bits). The definition for line 24 is valid for the restofthe corresponding field, normally no text data (video data) should be selected there (LCR24 = FFH) to stop the activity of the VBI data slicer during active video.

To adjust the slicers processing to the input signal source, there are offsets in the horizontal and vertical direction available (parameters HOFF[5B,59[2:0,7:0]], VOFF[5B,5A[4,7:0]] and FOFF[5B[7]]).

In difference to the scalers counting, the slicers offsets define the position of the horizontal and vertical trigger events related to the processed video field. The trigger events are the falling edge of HREF and the falling edge of V123 from the decoder processing part.

The relationship of these programming values to the input signal and the recommended values can be seen in Tables 18 to 21.

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Table 28 Data types supported by the data slicer block

DATA TYPE

NUMBER

0000 teletext EuroWST, CCST 6.9375 27H WST625 always 0001 European Closed Caption 0.500 001 CC625 0010 VPS 5 9951H VPS 0011 wide screen signalling bits 5 1E3C1FH WSS 0100 US teletext (WST) 5.7272 27H WST525 always 0101 US Closed Caption (line 21) 0.503 001 CC525 0110 (video data selected) 5 none disable 0111 (raw data selected) 5 none disable 1000 teletext 6.9375 programmable general text optional 1001 VITC/EBU time codes (Europe) 1.8125 programmable VITC625 1010 VITC/SMPTE time codes (USA) 1.7898 programmable VITC525 1011 5 programmable open 1100 US NABTS 5.7272 programmable NABTS optional 1101 MOJI (Japanese) 5.7272 programmable (A7H) Japtext 1110 Japanese format switch (L20/22) 5 programmable open 1111 no sliced data transmitted

STANDARD TYPE

(video data selected)

DATA RATE

(Mbits/s)

5 none disable

FRAMING CODE

WINDOW

HAM

CHECK

9.5 Image port output formatter

(subaddresses 84H to 87H)

The output interface consists of a FIFO for video and for sliced text data, an arbitration circuit, which controls the mixed transfer of video and sliced text data over the I port, and a decoding and multiplexing unit, which generates the 8 or 16-bit wide output data stream together with the accompanying reference and help information.

The clock for the output interface can be derived from an internal clock, decoder, expansion port or an externally provided clock which is appropriate, for example, for the VGA and frame buffer. The clock can be up to 33 MHz. The scaler provides the following video related timing reference events (signals), which are available on pins as defined by subaddresses 84H and 85H:

• Output field ID

• Start and end of vertical active video range

• Start and end of active video line

• Data qualifier or gated clock

• Actually activated programming page (if CONLH is

used)

• Threshold controlled FIFO filling flags (empty, full, filled)

• Sliced data marker.

The disconnected data stream at the scaler output is accompanied by a data valid flag (or data qualifier), or is transported via a gated clock. Clock cycles with invalid dataon the I port data bus (includingtheHPDpins in 16-bit output mode) are marked with code 00H.

The output interface also arbitrates the transfer between scaled video data and sliced text data over the I port output.

The bits VITX1 and VITX0 (subaddress 86H) are used to control the arbitration.

The serialization of the internal 32-bit Dwords to 8-bit or 16-bit output (optional), as well as the insertion of the extendedITU 656 codes (SAV/EAV for video data, ANCor SAV/EAV codes for sliced text data) are also done here.

Forhandshaking with the VGA controller, or other memory or bus interface circuitry, programmable FIFO flags are provided; see Section 9.5.2.

2004 Jun 29 71

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9.5.1 SCALER OUTPUT FORMATTER

(SUBADDRESSES 93H AND C3H)

The output formatter organizes the packing into the output FIFO. The following formats are available: Y-CB-CR4:2:2, Y-CB-CR4:1:1, Y-CB-CR4:2:0, Y-CB-CR4:1:0, Yonly (e.g. for raw samples). The formatting is controlled by FSI[2:0] 93H[2:0], FOI[1:0] 93H[4:3] and FYSK[93H[5]].

The data formats are defined on Dwords, or multiples thereof, and are similar to the video formats as recommended for PCI multimedia applications (see SAA7146A). Planar formats are not supported.

Table 29 Byte stream for different output formats

OUTPUT FORMAT BYTE SEQUENCE FOR 8-BIT OUTPUT MODES

Y-CB-CR4:2:2 CB0Y0CR0Y1CB2Y2CR2Y3CB4Y4CR4Y5 CB6Y6 Y-CB-CR4:1:1 CB0Y0CR0Y1CB4Y2CR4Y3Y4 Y5Y6 Y7 CB8Y8 Yonly Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13

Table 30 Explanation to Table 29

NAME EXPLANATION

CBnC Yn Y (luminance) component, pixel number n = 0, 1, 2, 3 to 719 CRnC

(B − Y) colour difference component, pixel number n = 0, 2, 4 to 718

(R − Y) colour difference component, pixel number n= 0, 2, 4 to 718

FSI[2:0] defines the horizontal packing of the data, FOI[1:0] defines how many Y only lines are expected before a Y/C line will be formatted. If FYSK is set to logic 0 preceding Y only lines will be skipped, and the output will always start with a Y/C line.

Additionallytheoutputformatter limits the amplitude range of the video data (controlled by ILLV[85H[5]]); see Table 31.

Table 31 Limiting range on I port

LIMIT STEP

ILLV[85H[5]]

0 1 to 254 01 to FE 00 FF 1 8 to 247 08 to F7 00 to 07 F8 to FF

2004 Jun 29 72

DECIMAL VALUE HEXADECIMAL VALUE LOWER RANGE UPPER RANGE

VALID RANGE SUPPRESSED CODES (HEXADECIMAL VALUE)

Philips Semiconductors Product speciﬁcation

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9.5.2 VIDEO FIFO (SUBADDRESS 86H)

The video FIFO at the scaler output contains 32 Dwords. That corresponds to 64 pixels in 16-bit Y-CB-CR4:2:2 format.Butastheentirescalercan act as a pipeline buffer, the actually available buffer capacity for the image port is much higher, and can exceed beyond a video line.

The image port and the video FIFO, can operate with the video source clock (synchronous mode) or with an externallyprovided clock (asynchronous,and burst mode), as appropriate for the VGA controller or attached frame buffer.

The video FIFO provides 4 internal flags, which report to what extent the FIFO is actually filled. These are:

• The FIFO Almost Empty (FAE) flag

• TheFIFOCombined(FC)flag or FIFO filled, which is set

at almost full level and reset, with hysteresis, only after the level crosses below the almost empty mark

• The FIFO Almost Full (FAF) flag

• The FIFO Overflow (FOVL) flag.

The trigger levels for FAE and FAF are programmable by FFL[1:0] 86H[3:2] (16, 24, 28, full) and FEL[1:0] 86H[1:0] (16, 8, 4, empty).

The state of this flag can be seen on pins IGP0 or IGP1. The pin mapping is defined by subaddresses 84H and 85H; see Section 10.5.

9.5.3 TEXT FIFO

The data of the terminal VBI data slicer is collected in the text FIFO before transmission over the I port is requested (normally before the video window starts) and partitioned intotwoFIFOsections.Acompleteline is fed into the FIFO before a data transfer is requested. So normally, one line of text data is ready for transfer while the next text line is collected. Thus sliced text data is delivered as a block of qualified data, without any qualification gaps in the byte stream of the I port.

The decoded VBI data is collected in the dedicated VBI data FIFO. Once the capture of a line is completed, the FIFO can be streamed through the image port, preceded by a header, giving the line number and standard.

The VBI data period can be signalled via the sliced data flag on pin IGP0 or IGP1. The decoded VBI data is lead by the ITU ancillary data header (DID[5:0] 5DH[5:0] at value <3EH)orby SAV/EAV codes selected by DID[5:0] at value 3EH or 3FH. IGP0 or IGP1 is set if the first byte of the ANC header is valid on the I port bus; it is reset if an SAV occurs. Therefore it may frame multiple lines of text data output, in case the video processing starts with a distance of several video lines to the region of text data. Valid sliced data from the text FIFO is available on the I port as long as the IGP0 or IGP1 flag is set and the data qualifier is active on pin IDQ.

The decoded VBI data is presented in two different data formats, controlled by bit RECODE.

RECODE = 1: values 00H and FFH will be recoded to even parity values 03H and FCH

RECODE = 0: values 00H and FFH may occur in the data stream as detected.

9.5.4 VIDEO AND TEXT ARBITRATION (SUBADDRESS 86H) Slicedtext data and scaled video data are transferred over

the same bus, the I port. The mixed transfer is controlled by an arbitration circuit. If the video data is transferred without any interrupt and the video FIFO does not need to buffer any output pixel, the text data is inserted after the end of a scaled video line, normally during the video blanking interval.

2004 Jun 29 73

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9.5.5 DATA STREAM CODING AND REFERENCE SIGNAL

GENERATION (SUBADDRESSES 84H, 85H AND 93H)

As horizontal and vertical reference signals are logic 1, activegate signals are generated, whichframethe transfer of the valid output data. Alternatively, the horizontal and vertical trigger pulses can be generated on the rising edges of the gates.

Dueto the dynamic FIFO behaviour of the complete scaler path, the output signal timing has no fixed timing relationship to the real-time input video stream. Thus fixed propagation delays, in terms of clock cycles, related to the analog input can not be defined.

The data stream is accompanied by a data qualifier. Additionally invalid data cycles are marked with code 00H.

Table 32 SAV/EAV codes on the I port

SAV/EAV CODES ON I PORT

EVENT DESCRIPTION

(2)

OF SAV/EAV BYTE = 0 MSB

FIELD ID = 0 FIELD ID = 1 FIELD ID = 0 FIELD ID = 1

Nextpixel is FIRST pixel of any

0E 49 80 C7 HREF = active;

active line Previous pixel was LAST pixel

13 54 9D DA HREF= inactive; of any active line, but not the last

Nextpixel is FIRST pixel of any

25 62 AB EC HREF = active; V-blanking line

Previous pixel was LAST pixel

38 7F B6 F1 HREF = inactive; of the last active line or of any V-blanking line

No valid data, do not capture and do not increment pointer

If ITU 656 like codes are not required, they can be suppressed in the output stream.

As a further option, it is possible to provide the scaler with an external gating signal on pin ITRDY. It is therefore possible to hold the data output for a certain time and to get valid output data in bursts of a guaranteed length.

The sketched reference signals and events can be mapped to the I port output pins IDQ, IGPH, IGPV, IGP0 and IGP1. The polarities of all the outputs can be modified to enable flexible use. The default polarity for the qualifier and reference signals is logic 1 (active).

Table 32 shows the relevant and supported SAV and EAV coding.

(1)

(HEX)

(2)

OF SAV/EAV BYTE = 1

COMMENTMSB

VREF = active

VREF = inactive

00 IDQ pin inactive

Notes

1. The leading byte sequence is: FFH-00H-00H.

2. The MSB of the SAV/EAV code byte is controlled by: a) Scaler output data: task A ⇒ MSB = CONLH[90H[7]]; task B ⇒ MSB = CONLH[C0H[7]]. b) VBI data slicer output data: DID[5:0] 5DH[5:0] = 3EH ⇒ MSB = 1; DID[5:0] 5DH[5:0] = 3FH ⇒ MSB = 0.

2004 Jun 29 74

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2004 Jun 29 75

invalid data

end of raw VBI line

00 00 FF 00 00 SAV SDID DC IDI1 IDI2 D

...

FF 00 00 EAV

ANC header active for DID (subaddress 5DH) <3EH

timing reference code

ANC header internal header sliced data

00 FF FF DID SDID DC IDI1 IDI2 D

sliced data invalid dataand filling data

1_3D1_4D2_1

1_2

1_1

1_3D1_4

DC_3DDC_4

CS BC 00 00...

CS BC FF 00 00 EAV 00 00... ...

ANC data output is only filled up to the Dword boundary

timing reference codeinternal header

...

Fig.39 Sliced data formats on the I port in 8-bit mode.

Table 33 Explanation to Fig.39

NAME EXPLANATION

SAV start of active data; see Table 34

(1)

SDID sliced data identiﬁcation: NEP

(2)

, EP

, SDID5 to SDID0, freely programmable via I2C-bus subaddress 5EH, bits 5 to 0, e. g. to be used as

source identiﬁer

(1)

DC Dword count: NEP

(2)

, EP

, DC5 to DC0. DC describes the number of succeeding 32-bit words:

• For SAV/EAV mode DC is fixed to 11 Dwords (byte value 4BH)

• For ANC mode it is: DC =1⁄4(C + n), where C = 2 (the two data identification bytes IDI1 and IDI2) and n = number of decoded bytes

according to the chosen text standard.

Note that the number of valid bytes inside the stream can be seen in the BC byte. IDI1 internal data identiﬁcation 1: OP IDI2 internal data identiﬁcation 2: OP D D

Dword number n, byte number m

n_m

last Dword byte 4, note: for SAV/EAV framing DC is ﬁxed to 0BH, missing data bytes are ﬁlled up; the ﬁll value is A0H

DC_4

CS the check sum byte, the check sum is accumulated from the SAV (respectively DID) byte to the D

(3)

, FID (ﬁeld 1 = 0, ﬁeld 2 = 1), LineNumber8 to LineNumber3 = Dword 1 byte 1; see Table 34

(3)

, LineNumber2 to LineNumber0, DataType3 to DataType0 = Dword 1 byte 2; see Table 34

byte

DC_4

BC number of valid sliced bytes counted from the IDI1 byte EAV end of active data; see Table 34

Philips Semiconductors Product speciﬁcation

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...

MHB549

Notes

1. Inverted EP (bit 7); for EP see note 2.

2. Even parity (bit 6) of bits 5 to 0.

3. Odd parity (bit 7) of bits 6 to 0.

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

Table 34 Bytes stream of the data slicer

NICK

NAME

DID, SAV, EAV

COMMENT BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

subaddress

NEP

(1)

(2)

0 1 0 FID

(3)

(4)

5DH = 00H subaddress 5DH;

NEP EP 0 D4[5DH] D3[5DH] D2[5DH] D1[5DH] D0[5DH]

bit 5 = 1 subaddress 5DH

1 FID

(3)

(6)

(7)

P3 P2 P1 P0

bit 5 = 3EH; note 5 subaddress 5DH

0 FID

(3)

(6)

(7)

P3 P2 P1 P0

bit 5 = 3FH; note 5

SDID programmable via

NEP EP D5[5EH] D4[5EH] D3[5EH] D2[5EH] D1[5EH] D0[5EH]

subaddress 5EH

(8)

DC IDI1 OP

NEP EP

(9)

IDI2 OP LN2

FID

(2)

(3)

(10)

DC5 DC4 DC3 DC2 DC1 DC0 LN8 LN1

(10) (10)

LN7 LN0

(10) (10)

LN6

DT3

(10) (11)

LN5 DT2

(10) (11)

LN4 DT1

(10) (11)

LN3

DT0 CS check sum byte CS6 CS6 CS5 CS4 CS3 CS2 CS1 CS0 BC valid byte count OP 0 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0

Notes

1. NEP = inverted EP (see note 2).

2. EP = Even Parity of bits 5 to 0.

3. FID = 0: field 1; FID = 1: field 2.

4. I1 = 0 and I0 = 0: before line 1; I1 = 0 and I0 = 1: lines 1 to 23; I1 = 1 and I0 = 0: after line 23; I1 = 1 and I0 = 1: line 24 to end of field.

5. Subaddress 5DH at 3EH and 3FH are used for ITU 656 like SAV/EAV header generation; recommended value.

6. V = 0: active video; V = 1: blanking.

7. H = 0: start of line; H = 1: end of line.

8. DC = Data Count in Dwords according to the data type.

9. OP = Odd Parity of bits 6 to 0.

10. LN = Line Number.

11. DT = Data Type according to table.

(4)

(10) (11)

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9.6 Audio clock generation

(subaddresses 30H to 3FH)

The SAA7108AE; SAA7109AE incorporates the generation of a field-locked audio clock, as an auxiliary function for video capture. An audio sample clock, that is locked to the field frequency, ensures that there is always the same predefined number of audio samples associated with a field, or a set of fields. This ensures synchronous playback of audio and video after digital recording (e.g. capture to hard disk), MPEG or other compression or non-linear editing.

9.6.1 MASTER AUDIO CLOCK

The audio clock is synthesized from the same crystal frequency as the line-locked video clock is generated. The master audio clock is defined by the parameters:

Table 35 Programming examples for audio master clock generation

CRYSTAL

FREQUENCY

(MHz)

AMCLK = 256 × 48 kHz (12.288 MHz)

32.11

24.576

AMCLK = 256 × 44.1 kHz (11.2896 MHz)

32.11

24.576

AMCLK = 256 × 32 kHz (8.192 MHz)

32.11

24.576

FIELD

(Hz)

50 245760 3C000 3210190 30FBCE

59.94 205005 320CD 3210190 30FBCE 50 −−−−

59.94 −−−−

50 225792 37200 2949362 2D00F2

59.94 188348 2DFBC 2949362 2D00F2 50 225792 37200 3853517 3ACCCD

59.94 188348 2DFBC 3853517 3ACCCD

50 163840 28000 2140127 20A7DF

59.94 136670 215DE 2140127 20A7DF 50 163840 28000 2796203 2AAAAB

59.94 136670 215DE 2796203 2AAAAB

DECIMAL HEX DECIMAL HEX

ACPF ACNI

• Audio master Clocks Per Field, ACPF[17:0] 32H[1:0] 31H[7:0] 30H[7:0] according to the equation:

ACPF[17:0] round

• Audio master Clocks Nominal Increment, ACNI[21:0] 36H[5:0] 35H[7:0] 34H[7:0] according to the equation:

ACNI[21:0] round

See Table 35 for examples. Remark: For standard applications the synthesized audio

clock AMCLK can be used directly as master clock and as input clock for port AMXCLK (short cut) to generate ASCLK and ALRCLK. For high-end applications it is recommended to use an external analog PLL circuit to enhance the performance of the generated audio clock.

audio frequency



------------------------------------------



field frequency

audio frequency



---------------------------------------------



crystal frequency

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9.6.2 SIGNALS ASCLK AND ALRCLK Two binary divided signals ASCLK and ALRCLK are provided for slower serial digital audio signal transmission and for

channel-select. The frequencies of these signals are defined by the parameters:

AMXCLK

• SDIV[5:0] 38H[5:0] according to the equation: ⇒

• LRDIV[5:0] 39H[5:0] according to the equation: ⇒

= SDIV[5:0]

ASCLK

ALRCLK

------------------------------------- SDIV 1+()2×

ASCLK

= LRDIV[5:0]

-------------------------- LRDIV 2×

-------------------2f

---------------------- 2f

AMXCLK

ASCLK

ASCLK ALRCLK

1–=

See Table 36 for examples.

Table 36 Programming examples for ASCLK/ALRCLK clock generation

AMXCLK

(MHz)

12.288

11.2896

8.192

9.6.3 O

ASCLK

(kHz)

1536 3 03

768 7 07 8 08

1411.2 3 03

2822.4 1 01 32 10 1024 3 03 2048 1 01 32 10

THER CONTROL SIGNALS

SDIV

DECIMAL HEX DECIMAL HEX

ALRCLK

(kHz)

44.1

LRDIV

16 10

Further control signals are available to define reference clock edges and vertical references; see Table 37.

Table 37 Control signals

CONTROL

SIGNAL

APLL[3AH[3]] Audio PLL mode:

0: PLL closed 1: PLL open

AMVR[3AH[2]] Audio Master clock Vertical Reference:

0: internal vertical reference 1: external vertical reference

LRPH[3AH[1]] ALRCLK Phase:

0: invert ASCLK, ALRCLK edges triggered by falling edge of ASCLK 1: do not invert ASCLK, ALRCLK edges triggered by rising edge of ASCLK

SCPH[3AH[0]] ASCLK Phase:

0: invert AMXCLK, ASCLK edges triggered by falling edge of AMXCLK 1: do not invert AMXCLK, ASCLK edges triggered by rising edge of AMXCLK

2004 Jun 29 78

DESCRIPTION

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

10 INPUT/OUTPUT INTERFACES AND PORTS OF

DIGITAL VIDEO DECODER PART

The SAA7108AE; SAA7109AE has 5 different I/O interfaces. These are:

• Analog video input interface, for analog CVBS and/or Y and C input signals

• Audio clock port

• Digital real-time signal port (RT port)

• Digitalvideoexpansion port (X port), for unscaled digital

video input and output

• Digital image port (I port) for scaled video data output and programming

• Digital host port (H port) for extension of the image port or expansion port from 8 to 16-bit.

Table 38 Analog pin description

SYMBOL PIN I/O DESCRIPTION BIT

AI24 to AI21 P6, P7, P9

and P10 AI12 and AI11 P11 and P13 AOUT M10 O analog video output, for test purposes AOSL1 and AOSL0 AI1D and AI2D P12 and P8 I analog reference pins for differential ADC operation −

I analog video signal inputs, e.g. 2 CVBS signals and

two Y/C pairs can be connected simultaneously

10.1 Analog terminals

The SAA7108AE; SAA7109AE has 6 analog inputs AI21 to AI24, AI11 and AI12 (see Table 38) for composite videoCVBS or S-video Y/C signalpairs.Additionally, there are two differential reference inputs, which must be connected to ground via a capacitor equivalent to the decoupling capacitors at the 6 inputs. There are no peripheral components required other than the decoupling capacitors and 18 Ω/56 Ω termination resistors, one set per connected input signal (see also application example in Fig.53). Two anti-alias filters are integrated, and self adjusting via the clock frequency.

Clamp and gain control for the two ADCs are also integrated. An analog video output pin (AOUT) is provided for testing purposes.

MODE3 to MODE0

10.2 Audio clock signals

The SAA7108AE; SAA7109AE also synchronizes the audio clock and sampling rate to the video frame rate, via a very slow PLL. This ensures that the multimedia capture and compression processes always gather the same predefined number of samples per video frame.

An audio master clock AMCLK and two divided clocks, ASCLK and ALRCLK, are generated; see Table 39.

• ASCLK: can be used as audio serial clock

• ALRCLK: audio left/right channel clock.

The ratios are programmable; see Section 9.6.

Table 39 Audio clock pin description

SYMBOL PIN I/O DESCRIPTION BIT

AMCLK K12 O audio master clock output ACPF[17:0] 32H[1:0] 31H[7:0] 30H[7:0]

and ACNI[21:0] 36H[5:0] 35H[7:0] 34H[7:0]

AMXCLK J12 I external audio master clock input for the clock

division circuit, can be directly connected to output AMCLK for standard applications

ASCLK K14 O serial audio clock output, can be synchronized to

rising or falling edge of AMXCLK

ALRCLK J13 O audio channel (left/right) clock output, can be

synchronized to rising or falling edge of ASCLK

−

SDIV[5:0] 38H[5:0] and SCPH[3AH[0]]

LRDIV[5:0] 39H[5:0] and LRPH[3AH[1]]

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10.3 Clock and real-time synchronization signals

A crystal accurate frequency reference is required for the generation of the line-locked video (pixel) clock LLC, and the frame-locked audio serial bit clock. An oscillator is built-in, for fundamental or 3rd-harmonic crystals. The supported crystal frequencies are 32.11 or 24.576 MHz (defined during reset by strapping pin ALRCLK).

Alternatively pins XTALId and XTALIe can be driven from an external single-ended oscillator.

The crystal oscillation can be propagated as clock to other ICs in the system via pin XTOUTd.

Table 40 Clock and real-time synchronization signals

SYMBOL PIN I/O DESCRIPTION BIT Crystal oscillator

XTALId P2 I input for crystal oscillator, or reference clock − XTALOd P3 O output of crystal oscillator − XTOUTd P4 O reference (crystal) clock output drive (optional) XTOUTE[14H[3]]

Real-time signals (RT port)

LLC M14 O line-locked clock; nominal 27 MHz, double pixel clock locked to the

selected video input signal LLC2 L14 O line-locked pixel clock; nominal 13.5 MHz − RTCO L13 O real-time control output; transfers real-time status information

supporting RTC level 3.1 (see external document

Description”

RTS0 K13 O real-time status information line 0; can be programmed to carry

various real-time informations; see Table 171 RTS1 L10 O real-time status information line 1; can be programmed to carry

various real-time informations; see Table 172

, available on request)

The Line-Locked Clock (LLC) is the double pixel clock at a nominal 27 MHz. It is locked to the selected video input, generating baseband video pixels according to

recommendation 601”

circuits, a direct pixel clock LLC2 is also provided. The pins for line and field timing reference signals are

RTCO, RTS1 and RTS0. Various real-time status information can be selected for the RTS pins. The signals are always available (output) and reflect the synchronization operation of the decoder part in the SAA7108AE; SAA7109AE. The function of the RTS1 and RTS0pins can be definedbybits RTSE1[3:0] 12H[7:4] and RTSE0[3:0] 12H[3:0]; see Table 40.

. In order to support interfacing

−

“ITU

“RTC Functional

RTSE0[3:0] 12H[3:0]

RTSE1[3:0] 12H[7:4]

2004 Jun 29 80

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10.4 Video expansion port (X port)

The expansion port is intended for transporting video streamsof image data from other digitalvideocircuitssuch as MPEG encoder/decoder and video phone codec, to the image port (I port); see Table 41.

The expansion port consists of two groups of signals/pins:

• 8-bit data, I/O, regular video components Y-CB-C 4:2:2, i.e. CB-Y-CR-Y, byte serial, exceptionally raw video samples (e.g. ADC test). In input mode the data bus can be extended to 16-bit by pins HPD7 to HPD0.

• Clock, synchronization and auxiliary signals, accompanying the data stream, I/O.

Table 41 Signals dedicated to the expansion port

SYMBOL PIN I/O DESCRIPTION BIT

XPD7 to XPD0

XCLK M3 I/O clock at expansion port: if output, then copy of

XDQ M4 I/O data valid ﬂag of the expansion port input

XRDY N3 O data request ﬂag = ready to receive, to work with

XRH N2 I/O horizontal reference signal for the X port: as

XRV L5 I/O vertical reference signal for the X port: as output:

XTRI K1 I port control: switches X port input to 3-state XPE[1:0] 83H[1:0]

K2, K3,

L1 to L3,

M1, M2

and N1

I/O X port data: in output mode controlled by decoder

section, for data format see Table 42; in input mode Y-CB-CR4:2:2 serial input data or luminance part of a 16-bit Y-CB-CR4:2:2 input

LLC; as input normally a double pixel clock of up to 32 MHz or a gated clock (clock gated with a qualiﬁer)

(qualiﬁer): if output, then decoder (HREF and VGATE) gate (see Fig.32)

optional buffer in external device, to prevent internal buffer overﬂow; second function: input related task ﬂag A/B

output: HREF or HS from the decoder (see Fig.32); as input: a reference edge for horizontal input timing and a polarity for input ﬁeld ID detection can be deﬁned

V123 or ﬁeld ID from the decoder, see Figs 30 and 31; as input: a reference edge for vertical input timing and for input ﬁeld ID detection can be deﬁned

As output, these are direct copies of the decoder signals. The data transfers through the expansion port represent a

single D1 port, with half duplex mode. The SAV and EAV codes may be inserted optionally for data input (controlled by bit XCODE[92H[3]]). The input/output direction is switched for complete fields only.

OFTS[2:0] 13H[2:0], 91H[7:0] and C1H[7:0]

XCKS[92H[0]]

−

XRQT[83H[2]]

XRHS[13H[6]], XFDH[92H[6]] and XDH[92H[2]]

XRVS[1:0] 13H[5:4], XFDV[92H[7]] and XDV[1:0] 92H[5:4]

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10.4.1 X PORT CONFIGURED AS OUTPUT

Ifthedataoutputisenabledat the expansion port, then the data stream from the decoder is present. The data format of the 8-bit data bus is dependent on the chosen data type which is selectable by the line control registers LCR2 to LCR24; see Table 17. In contrast to the image port, the sliced data format is not available on the expansion port. Instead, raw CVBS samples are always transferred if any sliced data type is selected.

Detailsofsome of the data types on the expansion port are as follows:

• Active video: (data type 15) contains components Y-CB-CR4:2:2 signal, 720 active pixels per line. The amplitude and offsets are programmable via DBRI7 to DBRI0, DCON7 to DCON0, DSAT7 to DSAT0, OFFU1, OFFU0, OFFV1 and OFFV0. For nominal levels see Fig.26.

• Test line: (data type 6) is similar to the active video format, with some constraints within the data processing:

– adaptive chrominance comb filter, vertical filter

(chrominance comb filter for NTSC standards, PAL phase error correction) within the chrominance processing are disabled

– adaptive luminance comb filter, peaking and

chrominance trap are bypassed within the luminance processing.

Thisdatatypeisdefinedforfutureenhancements.Itcan be activated for lines containing standard test signals within the vertical blanking period. Currently most sources do not contain test lines. For nominal levels see Fig.26.

• Raw samples (data types 0 to 5 and 7 to 14): CB-C

samples are similar to data type 6, but CVBS samples aretransferred instead ofprocessed luminance samples within the Y time slots.

The amplitude and offset of the CVBS signal is programmable via RAWG7 to RAWG0 and RAWO7 to RAWO0, see Chapter 18, Tables 178 and 179. For nominal levels see Fig.27.

The relationship of LCR programming to line numbers is described in Section 9.2; see Tables 18 to 21.

The data type selections by LCR are overruled by setting OFTS2 = 1 (subaddress 13H bit 2). This setting is mainly intended for device production testing. The VPO-bus carries the upper or lower 8 bits of the two ADCs depending on the OFTS[1:0] 13H[1:0] settings; see Table 173. The output configuration is done via MODE[3:0] 02H[3:0] settings; see Table 155. If a Y/C mode is selected, the expansion port carries the multiplexed output signals of both ADCs, in CVBS mode theoutput of only one ADC. No timing reference codes are generated in this mode.

Remark: The LSBs (bit 0) of the ADCs are also available on pin RTS0; see Table 171.

The SAV/EAV timing reference codes define the start and end of valid data regions. The ITU-blanking code sequence ‘- 80 - 10 - 80 - 10 -...’ is transmitted during the horizontal blanking period, between EAV and SAV.

The position of the F bit is constant according to ITU 656; see Tables 44 and 45.

The V bit can be generated in two different ways (see Tables 44 and 45) controlled via OFTS1 and OFTS0; see Table 173.

F and V bits change synchronously with the EAV code.

Table 42 Data format on the expansion port

BLANKING

PERIOD

TIMING

REFERENCE

CODE (HEX)

(1)

720 PIXELS Y-CB-CR4:2:2 DATA

(2)

TIMING

REFERENCE

CODE (HEX)

(1)

BLANKING

PERIOD

... 80 10 FF 00 00 SAV CB0Y0CR0Y1CB2 Y2 ... CR718 Y719 FF 00 00 EAV 80 10 ...

Notes

1. The generation of the timing reference codes can be suppressed by setting OFTS[2:0] to ‘010’; see Table 173. In

this event the code sequence is replaced by the standard ‘- 80 - 10 -’ blanking values.

2. If raw samples or sliced data are selected by the line control registers (LCR2 to LCR24), the Y samples are replaced

by CVBS samples.

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Table 43 SAV/EAV format on expansion port XPD7 to XPD0

BIT 7

1 ﬁeld bit vertical blanking bit format reserved; evaluation not

for vertical timing see Tables 44 and 45

Table 44 525 lines/60 Hz vertical timing

LINE NUMBER F (ITU 656)

1 to 3 1 1 according to selected VGATE position type via

4to19 0 1

20 0 0 21 0 0

22 to 261 0 0

262 0 0 263 0 0

264 and 265 0 1

266 to 282 1 1

283 1 0 284 1 0

285 to 524 1 0

525 1 0

BIT 6

(F)

1st field: F = 0 2nd field: F = 1

BIT 5

(V)

VBI: V = 1 active video: V = 0

OFTS[2:0] = 000 (ITU 656) OFTS[2:0] = 001

BIT 4

(H)

H = 0 in SAV format H = 1 in EAV format

VSTA and VSTO (subaddresses 15H to 17H); see Tables 175 to 177

BIT 3

recommended (protection bits according to ITU 656)

(P3)

BIT 2

(P2)

BIT 1

(P1)

BIT 0

(P0)

Table 45 625 lines/50 Hz vertical timing

LINE NUMBER F (ITU 656)

OFTS[2:0] = 000 (ITU 656) OFTS[1:0] = 10

1 to 22 0 1 according to selected VGATE position type via

23 0 0

24 to 309 0 0

310 0 0

311 and 312 0 1

313 to 335 1 1

336 1 0

337 to 622 1 0

623 1 0

624 and 625 1 1

2004 Jun 29 83

VSTA and VSTO (subaddresses 15H to 17H); see Tables 175 to 177

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

10.4.2 X PORT CONFIGURED AS INPUT

If data input mode is selected at the expansion port, then the scaler can choose its input data stream from the on-chip video decoder, or from the expansion port (controlled by bit SCSRC[1:0] 91H[5:4]). Byte serial Y-CB-CR4:2:2,orsubsets for other sampling schemes, or raw samples from an external ADC may be input (see also bits FSC[2:0] 91H[2:0]). The input data stream must beaccompanied by an external clock XCLK, qualifier XDQ and reference signals XRH and XRV. Instead of the reference signal, embedded SAV and EAV codes, according to ITU 656, can also be accepted. The protection bits are not evaluated.

XRH and XRV carry the horizontal and vertical synchronization signals for the digital video stream through the expansion port. The field ID of the input video stream is carried in the phase (edge) of XRV and state of XRH, or directly as FS (frame sync, odd/even signal) on the XRV pin (controlled by XFDV[92H[7]], XFDH[92H[6]] and XDV[1:0] 92H[5:4]).

The trigger events on XRH (rising/falling edge) and XRV (rising/falling both edges) for the scalers acquisition window are defined by XDV[1:0] 92H[5:4] and XDH[92H[2]]. The signal polarity of the qualifier can also be defined by bit XDQ[92H[1]]. As an alternative to the qualifier, the input clock can be applied to a gated clock (clock gated with a data qualifier, controlled by bit XCKS[92H[0]]). In this event, all input data will be qualified.

10.5 Image port (I port)

The image port transfers data from the scaler as well as from the VBI data slicer, if selected (maximum 33 MHz). The reference clock is available at the ICLK pin as an output or as an input (maximum 33 MHz). As an output, the ICLK is derived from the line-locked decoder or expansion port input clock. The data stream from the scaler output is normally discontinuous. Therefore valid data during a clock cycle is accompanied by a data qualifying (data valid) flag on pin IDQ. For pin constrained applicationsthe IDQ pin can be programmedtofunctionas a gated clock output (bit ICKS2[80H[2]]).

The data formats at the image port are defined in Dwords of 32 bits (4 bytes), such as the related FIFO structures. However, the physical data stream at the image port is only 16-bit or 8-bit wide; in 16-bit mode data pins HPD7 to HPD0 are used for chrominance data. The four bytes of the Dwords are serialized in words or bytes.

The available formats are as follows:

• Y-CB-CR4:2:2

• Y-CB-CR4:1:1

• Raw samples

• Decoded VBI data.

For handshaking with the receiving VGA controller, or other memory or bus interface circuitry, F, H and V reference signals and programmable FIFO flags are provided. The information is provided on pins IGP0, IGP1, IGPH and IGPV. The function on these pins is controlled via subaddresses 84H and 85H.

VBIdataiscollected over an entire line in its own FIFO and transferred as an uninterrupted block of bytes. Decoded VBI data can be signed by the VBI flag on pins IGP0 and IGP1.

Because scaled video data and decoded VBI data may come from different and asynchronous sources, an arbitration scheme is needed. Normally the VBI data slicer has priority.

The image port consists of the pins and/or signals, as given in Table 46.

Forpin constrained applications,orinterfaces, the relevant timingand data reference signalscanalso be encoded into the data stream. Therefore the corresponding pins do not need to be connected. The minimum image port configuration requires 9 pins only, i.e. 8 pins for data including codes, and 1 pin for clock or gated clock. The inserted codes are defined in close relationship to the ITU-R BT.656 (D1) recommendation, where possible.

2004 Jun 29 84

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

The following deviations from are implemented at the SAA7108AE; SAA7109AEs image port interface:

• SAV and EAV codes are only present in those lines, where data is to be transferred, i.e. active video lines, or VBI raw samples, no codes for empty lines

• There may be more or less than 720 pixels between SAV and EAV

• The data content and number of clock cycles during horizontal and vertical blanking is undefined, and may be not constant

• The data stream may be interleaved with not-valid data codes, 00H, but SAV and EAV 4-byte codes are not interleaved with not-valid data codes

• There may be an irregular pattern of not-valid data, or IDQ, and as a result, ‘CB-Y-CR- Y -’ is not in a fixed phase to a regular clock divider

Table 46 Signals dedicated to the image port

SYMBOL PIN I/O DESCRIPTION BIT

IPD7 to IPD0

ICLK H12 I/O continuous reference clock at image port,

IDQ H14 O data valid ﬂag at image port, qualiﬁer, with

IGPH G12 O horizontal reference output signal, copy of

IGPV F13 O vertical reference output signal, copy of the

IGP1 G13 O general purpose output signal for I port IDG12[86H[4]], IDG1[1:0] 84H[5:4],

IGP0 F14 O general purpose output signal for I port IDG02[86H[5]], IDG0[1:0] 84H[7:6],

ITRDY J14 I target ready input signals − ITRI G14 I port control, switches I port into 3-state IPE[1:0] 87H[1:0]

E14, D14, C14, B14, E13, D13,

C13 and B13

“ITU 656 recommendation”

I/O I port data ICODE[93H[7]], ISWP[1:0] 85H[7:6]

can be input or output, as output decoder LLC or XCLK from X port

programmable polarity; secondary function: gated clock

the horizontal gate signal of the scaler,with programmable polarity; alternative function: HRESET pulse

vertical gate signal of the scaler, with programmable polarity; alternative function: VRESET pulse

• VBI raw sample streams are enveloped with SAV and EAV, like normal video

• Decoded VBI data is transported as Ancillary (ANC) data, two modes:

– direct decoded VBI data bytes (8-bit) are directly

placed in the ANC data field, 00H and FFH codes may appear in the data block (violation to ITU-R BT.656)

– recoded VBI data bytes (8-bit) directly placed in ANC

data field, 00H and FFH codes will be recoded to even parity codes 03H and FCH to suppress invalid ITU-R BT.656 codes.

There are no empty cycles in the ancillary code or its data field. The data codes 00H and FFH are suppressed (changed to 01H or FEH respectively) in the active video stream, as well as in the VBI raw sample stream (VBI pass-through). As an option the number range can be limited further.

and IPE[1:0] 87H[1:0]

ICKS[1:0] 80H[1:0] and IPE[1:0] 87H[1:0]

ICKS2[80H[2]], IDQP[85H[0]] and IPE[1:0] 87H[1:0]

IDH[1:0] 84H[1:0], IRHP[85H[1]] and IPE[1:0] 87H[1:0]

IDV[1:0] 84H[3:2], IRVP[85H[2]] and IPE[1:0] 87H[1:0]

IG1P[85H[3]] and IPE[1:0] 87H[1:0]

IG0P[85H[4]] and IPE[1:0] 87H[1:0]

2004 Jun 29 85

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

10.6 Host port for 16-bit extension of video data I/O (H port)

The H port, pins HPD, can be used to extend the data I/O paths to 16-bit. The I port has functional priority. If I8_16[93H[6]] is set to logic 1 the output drivers of the H port are enabled and are

dependent on the I port enable control. When I8_16 = 0, the HPD output is disabled.

Table 47 Signals dedicated to the host port

SYMBOL PIN I/O DESCRIPTION BIT

HPD7 to HPD0

A13, D12, C12, B12,

A12, C11, B11 and A11

I/O 16-bit extension for digital I/O

(chrominance component)

IPE[1:0] 87H[1:0], ITRI[8FH[6]] and I8_16[93H[6]]

10.7 Basic input and output timing diagrams for the I and X ports

10.7.1 I PORT OUTPUT TIMING

Thefollowingdiagrams(Figs 40 to 46)illustratetheoutput timing via the I port. IGPH and IGPV are indicated as logic 1 active gate signals. If reference pulses are programmed, these pulses are generated on the rising edgeofthe logic 1 active gates. Valid data is accompanied by the output data qualifier on pin IDQ. In addition, invalid cycles are marked with output code 00H.

The IDQ output pin may be defined to be a gated clock output signal (ICLK AND internal IDQ).

ICLK

IDQ

10.7.2 X PORT INPUT TIMING The input timing requirements at the X port are the same

as those for the I port output. However, the following differences should be noted:

• It is not necessary to mark invalid cycles with a 00H code

• No constraints on the input qualifier (can be a random pattern)

• XCLK may by a gated clock (XCLK AND external XDQ).

Remark: All timings illustrated are given for an uninterrupted output stream (no handshake with the external hardware).

IPD[7:0

IGPH

]

00 FF 00 00 SAV 00

Fig.40 Output timing at the I port for serial 8-bit data at start of a line (ICODE = 1).

2004 Jun 29 86

Y00

MHB550

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

ICLK

IDQ

IPD[7:0

IGPH

ICLK

IDQ

]

Y00

Fig.41 Output timing at the I port for serial 8-bit data at start of a line (ICODE = 0).

Y00

MHB551

IPD[7:0

IGPH

]

Y00

Fig.42 Output timing at the I port for serial 8-bit data at end of a line (ICODE = 1).

2004 Jun 29 87

Y00FF0000EAV00

MHB552

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

ICLK

IDQ

IPD[7:0

IGPH

ICLK

IDQ

]

Y00

Fig.43 Output timing at the I port for serial 8-bit data at end of a line (ICODE = 0).

MHB553

IPD[7:0

HPD[7:0

IGPH

]

00 FF 00 00 Y0 Y1 00 Y2 Y3

]

00 00 SAV 00 00

n−1

00 FF 00 00

00 00 EAV 00

Fig.44 Output timing for 16-bit data output via the I and H port with codes (ICODE = 1), timing is like 8-bit output,

but packages of 2 bytes per valid cycle.

2004 Jun 29 88

MHB554

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

handbook, full pagewidth

IDQ

IGPH

IGPV

MHB555

handbook, full pagewidth

ICLK

IDQ

]

IPD[7:0

]

HPD[7:0

sliced data

flag on IGP0

or IGP1

Fig.45 Horizontal and vertical gate output timing.

00 00 FF FF DID SDID XX YY ZZ CS

00 FF 00 SAV00 00 00BC FF EAV

00 00 00

MHB733

Fig.46 Output timing for sliced VBI data in 8-bit serial output mode (dotted graphs for SAV/EAV mode).

2004 Jun 29 89

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

11 BOUNDARY SCAN TEST

The SAA7108AE; SAA7109AE has built-in logic and 2 times5 dedicated pins to support boundary scan testing, separately for the encoder and decoder part, which allows board testing without special hardware (nails). The SAA7108AE; SAA7109AE follows the

“IEEE Std. 1149.1 Standard Test Access Port and Boundary-Scan Architecture”

chaired by Philips. The 10 special pins are Test Mode Select (TMSe and

TMSd), Test Clock (TCKe and TCKd), Test Reset (TRSTe and TRSTd), Test Data Input (TDIe and TDId) andTest Data Output(TDOe and TDOd),where extension ‘e’ refers to the encoder part and extension ‘d’ refers to the decoder part.

Table 48 BST instructions supported by the SAA7108AE; SAA7109AE

INSTRUCTION DESCRIPTION

BYPASS This mandatory instruction provides a minimum length serial path (1 bit) between TDIe (or TDId)

EXTEST This mandatory instruction allows testing of off-chip circuitry and board level interconnections.

SAMPLE This mandatory instruction can be used to take a sample of the inputs during normal operation of

CLAMP This optional instruction is useful for testing when not all ICs have BST. This instruction addresses

IDCODE This optional instruction will provide information on the components manufacturer, part number and

INTEST This optional instruction allows testing of the internal logic (no support for customers available).

USER1 This private instruction allows testing by the manufacturer (no support for customers available).

set by the Joint Test Action Group (JTAG)

and TDOe (or TDOd) when no test operation of the component is required.

the component. It can also be used to preload data values into the latched outputs of the boundary scan register.

the bypass register while the boundary scan register is in external test mode.

version number.

The Boundary Scan Test (BST) functions BYPASS, EXTEST, INTEST, SAMPLE, CLAMP and IDCODE are all supported; see Table 48. Details about the JTAG BST-TEST can be found in the specification “

1149.1”

Description Language (BSDL) of the SAA7108AE; SAA7109AE are available on request.

. Two files containing the detailed Boundary Scan

IEEE Std.

11.1 Initialization of boundary scan circuit

The Test Access Port (TAP) controller of an IC should be in the reset state (TEST_LOGIC_RESET) when the IC is in functional mode. This reset state also forces the instruction register into a functional instruction such as IDCODE or BYPASS.

To solve the power-up reset, the standard specifies that the TAP controller will be forced asynchronously to the TEST_LOGIC_RESET state by setting the TRSTe or TRSTd pin LOW.

11.2 Device identiﬁcation codes

A device identification register is specified in

1149.1b-1994”

for the specification of the IC manufacturer, the IC part number and the IC version number. Its biggest advantage

2004 Jun 29 90

. It is a 32-bit register which contains fields

“IEEE Std.

is the possibility to check for the correct ICs mounted after production and to determine the version number of the ICs during field service.

When the IDCODE instruction is loaded into the BST instruction register, the identification register will be connected between TDIe (or TDId) and TDOe (or TDOd) of the IC. The identification register will load a component specific code during the CAPTURE_DATA_REGISTER state of the TAP controller, this code can subsequently be shifted out. At board level this code can be used to verify component manufacturer, type and version number. The device identification register contains 32 bits, numbered 31 to 0, where bit 31 is the most significant bit (nearest to TDIe or TDId) and bit 0 is the least significant bit (nearest to TDOe or TDOd); see Fig.47.

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

handbook, full pagewidth

TDIe

(or TDId)

MSB LSB

28 27 12 11 1 0

nnnn

4-bit

version

code

0111000100000100

(0111000100010100)

16-bit part number 11-bit manufacturer

00000010101

identification

TDOe

(or TDOd)

MBL786

a. SAA7108AE.

handbook, full pagewidth

TDIe

(or TDId)

MSB LSB

28 27 12 11 1 0

nnnn

4-bit

version

code

0111000100000101

(0111000100010100)

16-bit part number 11-bit manufacturer

00000010101

identification

TDOe

(or TDOd)

MBL787

b. SAA7109AE.

Fig.47 32 bits of identification code.

12 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134); all ground pins connected together and grounded (0 V); all supply pins connected together.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V V V V V

DDD DDA i(A) i(n) i(D)

digital supply voltage −0.5 +4.6 V analog supply voltage −0.5 +4.6 V input voltage at analog inputs −0.5 +4.6 V input voltage at pins XTALI, SDA and SCL −0.5 V

+ 0.5 V

DDD

input voltage at digital inputs or I/O pins outputs in 3-state −0.5 +4.6 V

outputs in 3-state;

−0.5 +5.5 V

note 1 ∆V T T V

stg

amb

esd

voltage difference between V

SSA(n)

and V

SSD(n)

− 100 mV storage temperature −65 +150 °C ambient temperature 0 70 °C electrostatic discharge voltage humanbody model;

−±2000 V

note 2 machine model;

−±150 V

note 3

Notes

1. Condition for maximum voltage at digital inputs or I/O pins: 3.0 V < V

DDD

< 3.6 V.

2. Class 2 according to EIA/JESD22-114-B.

3. Class A according to EIA/JESD22-115-A.

2004 Jun 29 91

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

13 THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

th(j-a)

thermal resistance from junction to ambient in free air 32

Note

1. The overall R

value can vary depending on the board layout. To minimize the effective R

th(j-a)

ground pins must be connected to the power and ground layers directly. An ample copper area direct under the SAA7108AE; SAA7109AE with a number of through-hole plating, which connect to the ground layer (four-layer board: second layer), can also reduce the effective R

. Please do not use any solder-stop varnish under the chip.

th(j-a)

In addition the usage of soldering glue with a high thermal conductance after curing is recommended.

14 CHARACTERISTICS OF THE DIGITAL VIDEO ENCODER PART

= 0 to 70 °C (typical values measured at T

amb

=25°C); unless otherwise speciﬁed.

amb

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

DDA

DDIe

DD(DVO)

analog supply voltage 3.15 3.3 3.45 V digital supply voltage 3.15 3.3 3.45 V digital supply voltage

(DVO)

1.045 1.1 1.155 V

1.425 1.5 1.575 V

1.71 1.8 1.89 V

2.375 2.5 2.625 V

3.135 3.3 3.465 V

DDA

DDD

analog supply current note 1 1 110 115 mA digital supply current note 2 1 175 200 mA

Inputs

LOW-level input voltage V

DD(DVO)

= 1.1 V, 1.5 V,

−0.1 − +0.2 V

1.8 V or 2.5 V; note 3 V

DD(DVO)

pins RESe, TMSe, TCKe,

= 3.3 V; note 3 −0.5 − +0.8 V

−0.5 − +0.8 V

TRSTe and TDIe

HIGH-level input voltage V

DD(DVO)

= 1.1 V, 1.5 V,

DD(DVO)

− 0.2 − V

1.8 V or 2.5 V; note 3 V

DD(DVO)

pins RESe, TMSe, TCKe,

= 3.3 V; note 3 2 − V

2 − V

TRSTe and TDIe

input leakage current −−10 µA input capacitance clocks −−10 pF

data −−10 pF I/Os at high-impedance −−10 pF

(1)

all power and

th(j-a)

DD(DVO)

+ 0.3 V

DDIe

K/W

+ 0.1 V

+ 0.3 V

2004 Jun 29 92

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Outputs

C-bus; pins SDAe and SCLe

Clock timing; pins PIXCLKI and PIXCLKO

PIXCLK

d(CLKD)

δ duty factor t

Input timing

SU;DAT

HD;DAT

SU;DAT

HD;DAT

Crystal oscillator

nom

∆f/f

nom

LOW-level output voltage V

DD(DVO)

= 1.1 V, 1.5 V,

0 − 0.1 V

1.8 V or 2.5 V; note 3 V

DD(DVO)

pins TDOe,

= 3.3 V; note 3 0 − 0.4 V

0 − 0.4 V TTXRQ_XCLKO2, VSM and HSM_CSYNC

HIGH-level output voltage V

DD(DVO)

= 1.1 V, 1.5 V,

DD(DVO)

− 0.1 − V

DD(DVO)

1.8 V or 2.5 V; note 3 V

DD(DVO)

pins TDOe,

= 3.3 V; note 3 2.4 − V

2.4 − V

DD(DVO) DDIe

V TTXRQ_XCLKO2, VSM and HSM_CSYNC

LOW-level input voltage −0.5 − 0.3V HIGH-level input voltage 0.7V

DDIe

− V

DDIe

+ 0.3 V

input current Vi= LOW or HIGH −10 − +10 µA LOW-level output voltage

IOL=3mA −−0.4 V

(pin SDAe) output current during acknowledge 3 −− mA

cycle time note 4 12 −− ns delay from PIXCLKO to

note 5 −−−ns

PIXCLKI

note 4 40 50 60 % output 40 50 60 %

duty factor t

HIGH/TPIXCLK HIGH/TCLKO2

rise time note 4 −−1.5 ns fall time note 4 −−1.5 ns

input data set-up time pins PD11 to PD0 2 −− ns input data hold time pins PD11 to PD0 0.9 −− ns input data set-up time pins HSVGC, VSVGC

2 −− ns

and FSVGC; note 6

input data hold time pins HSVGC, VSVGC

1.5 −− ns

and FSVGC; note 6

nominal frequency − 27 − MHz permissible deviation of

note 7 −50 − +50 10

−6

nominal frequency

2004 Jun 29 93

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

CRYSTAL SPECIFICATION T

amb

Data and reference signal output timing

o(h)(gfx)

o(d)(gfx)

o(h)

o(d)

CVBS and RGB outputs

o(CVBS)(p-p)

o(VBS)(p-p)

o(C)(p-p)

o(RGB)(p-p)

∆V

DAC

ILE

lf(DAC)

DLE

lf(DAC)

ambient temperature 0 − 70 °C load capacitance 8 −− pF series resistance −−80 Ω motional capacitance

1.2 1.5 1.8 fF

(typical) parallel capacitance

2.8 3.5 4.2 pF

(typical)

output load capacitance 8 − 40 pF output hold time to

graphics controller output delay time to

graphics controller output hold time pins TDOe,

pins HSVGC, VSVGC, FSVGC and CBO

1.5 −− ns

−−10 ns

3 −− ns TTXRQ_XCLKO2, VSM and HSM_CSYNC

output delay time pins TDOe,

−−25 ns TTXRQ_XCLKO2, VSM and HSM_CSYNC

output voltage CVBS

see Table 49 − 1.23 − V

(peak-to-peak value) output voltage VBS

see Table 49 − 1 − V

(S-video) (peak-to-peak value)

output voltage C

see Table 49 − 0.89 − V

(S-video) (peak-to-peak value)

output voltage R, G, B

see Table 49 − 0.7 − V

(peak-to-peak value) inequality of output signal

− 2 − %

voltages output load resistance − 37.5 −Ω output signal bandwidth

−3 dB; note 8 − 170 − MHz

of DACs low frequency integral

−−±3 LSB

linearity error of DACs low frequency differential

−−±1 LSB

linearity error of DACs

2004 Jun 29 94

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

Notes

1. Minimum value for I2C-bus bit DOWNA = 1.

2. Minimum value for I2C-bus bit DOWND = 1.

3. Levels refer to pins PD11 to PD0, FSVGC, PIXCLKI, VSVGC, PIXCLKO, CBO, TVD, and HSVGC, being inputs or outputs directly connected to a graphics controller. Input sensitivity is1/2V

DD(DVO)

The reference voltage1/2V

4. The data is for both input and output direction.

5. This parameter is arbitrary, if PIXCLKI is looped through the VGC.

6. Tested with programming IFBP = 1.

7. If an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of subcarrier frequency and line/field frequency.

+ 100 mV for HIGH and1/2V

is generated on chip.

DD(DVO)

− 100 mV for LOW.

8. with C

-----------------------------------------------------------

3dB–

2π R

o(L)Cext

5 pF+()()

= 20 pF (typical).

ext

15 CHARACTERISTICS OF THE DIGITAL VIDEO DECODER PART

= 3.0 to 3.6 V;V

DDD

= 3.1 to 3.5 V;T

DDA

= 0 to 70 °C (typical values measured at T

amb

=25°C); timings and levels

amb

refer to drawings and conditions illustrated in Fig.52; unless otherwise speciﬁed.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V I

DDD

digital supply voltage 3.15 3.3 3.45 V digital supply current X port 3-state; 8-bit I port − 90 − mA power dissipation digital

− 300 − mW

part V I

DDA

analog supply voltage 3.15 3.3 3.45 V

analog supply current AOSL1 and AOSL0 = 0

CVBS mode − 47 − mA Y/C mode − 72 − mA

tot(A+D)

tot(A+D)(pd)

power dissipation analog

part

total power dissipation

analog and digital part

total power dissipation

CVBS mode − 150 − mW Y/C mode − 240 − mW CVBS mode − 450 − mW Y/C mode − 540 − mW

CE pulled down to ground − 5 − mW analog and digital part in Power-down mode

tot(A+D)(ps)

total power dissipation analog and digital part in

I2C-bus controlled via

address 88H = 0FH

− 75 − mW

power-save mode

Analog part

clamp

clamping current VI= 0.9 V DC −±8 −µA

2004 Jun 29 95

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

i(p-p)

Zi input impedance clamping current off 200 −− kΩ C

9-bit analog-to-digital converters

B analog bandwidth at −3dB − 7 − MHz φ

diff

clk(ADC)

DLE

dc(d)

ILE

dc(i)

Digital inputs

IL(SDAd,SCLd)

IH(SDAd,SCLd)

IL(XTALId)

IH(XTALId)

IL(n)

IH(n)

LI/O

Digital outputs; note 1 V

OL(SDAd)

OL(clk)

OH(clk)

input voltage (peak-to-peak value)

for normal video levels

1 V (p-p), −3dB

− 0.7 − V

termination 27/47 Ω and

AC coupling required;

coupling capacitor = 22 nF

input capacitance −−10 pF channel crosstalk fi< 5 MHz −−−50 dB

differential phase

− 2 − deg (ampliﬁer plus anti-alias ﬁlter bypassed)

differential gain (ampliﬁer

− 2 − % plus anti-alias ﬁlter bypassed)

ADC clock frequency 12.8 − 14.3 MHz DC differential linearity

− 0.7 − LSB error

DC integral linearity error − 1 − LSB

LOW-level input voltage

−0.5 − +0.3V

DDD

pins SDAd and SCLd HIGH-level input voltage

0.7V

DDD

− V

DDD

+ 0.5 V

pins SDAd and SCLd LOW-level CMOS input

−0.3 − +0.8 V voltage pin XTALId

HIGH-level CMOS input

2.0 − V

DDD

+ 0.3 V

voltage pin XTALId LOW-level input voltage all

−0.3 − +0.8 V other inputs

HIGH-level input voltage

2.0 − 5.5 V all other inputs

input leakage current −−1 µA I/O leakage current −−10 µA input capacitance I/O at high-impedance −−8pF

LOW-level output voltage

SDAd at 3 mA sink current −−0.4 V

pin SDAd LOW-level output voltage

−0.5 − +0.6 V for clocks

HIGH-level output voltage

2.4 − V

DDD

+ 0.5 V

for clocks

2004 Jun 29 96

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Clock output timing (LLC and LLC2); note 2 C

L(LLC)

δ duty factors for t

d(LLC-LLC2)

Horizontal PLL

H(nom)

∆fH/f

H(nom)

Subcarrier PLL

sc(nom)

∆f

Crystal oscillator for 32.11 MHz; note 3 f

xtal(nom)

∆f

xtal(nom)

∆f

xtal(nom)(T)

CRYSTAL SPECIFICATION (X1) T

amb(X1)

Crystal oscillator for 24.576 MHz; note 3 f

xtal(nom)

∆f

xtal(nom)

LOW-level output voltage

0 − 0.4 V

all other digital outputs HIGH-level output voltage

2.4 − V

DDD

+ 0.5 V

all other digital outputs

output load capacitance 15 − 50 pF cycle time pin LLC 35 − 39 ns

pin LLC2 70 − 78 ns

LLCH/tLLC

and t

LLC2H/tLLC2

rise time LLC and LLC2 0.2 V to V fall time LLC and LLC2 V delay time between LLC

and LLC2 output

CL=40pF 40 − 60 %

− 0.2 V −−5ns

DDD

− 0.2 V to 0.2 V −−5ns

DDD

measured at 1.5 V;

−4 − +8 ns

CL=25pF

nominal line frequency 50 Hz ﬁeld − 15625 − Hz

60 Hz ﬁeld − 15734 − Hz

permissible static deviation −−5.7 %

nominal subcarrier frequency

PAL BGHI − 4433619 − Hz NTSC M − 3579545 − Hz PAL M − 3575612 − Hz PAL N − 3582056 − Hz

lock-in range ±400 −− Hz

nominal frequency 3rd-harmonic − 32.11 − MHz permissible nominal

−−±70 × 10

−6

frequency deviation permissible nominal

−−±30 × 10

−6

frequency deviation with temperature

ambient temperature 0 − 70 °C load capacitance 8 −− pF series resonance resistor − 40 80 Ω motional capacitance − 1.5 ±20 % − fF parallel capacitance − 4.3 ±20 % − pF

nominal frequency 3rd-harmonic − 24.576 − MHz permissible nominal

−−±50 × 10

−6

frequency deviation

2004 Jun 29 97

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

∆f

xtal(nom)(T)

permissible nominal

−−±20 × 10 frequency deviation with temperature

CRYSTAL SPECIFICATION (X1) T

amb(X1)

ambient temperature 0 − 70 °C load capacitance 8 −− pF series resonance resistor − 40 80 Ω motional capacitance − 1.5 ±20 % − fF parallel capacitance − 3.5 ±20 % − pF

Clock input timing (XCLK)

δ duty factors for t t

cycle time 31 − 45 ns

LLCH/tLLC

40 50 60 % rise time −−5ns fall time −−5ns

Data and control signal input timing X port, related to XCLK input

SU;DAT

HD;DAT

input data set-up time − 10 − ns input data hold time − 3 − ns

Clock output timing

δ duty factors for

output load capacitance 15 − 50 pF cycle time 35 − 39 ns

35 − 65 % t

XCLKH/tXCLKL

rise time 0.6 to 2.6 V −−5ns fall time 2.6 to 0.6 V −−5ns

Data and control signal output timing X port, related to XCLK output (for XPCK[1:0] 83H[5:4] = 00 is default);

note 2 C

OHD;DAT

output load capacitance 15 − 50 pF output hold time CL=15pF − 14 − ns propagation delay from

CL=15pF − 24 − ns positive edge of XCLK output

Control signal output timing RT port, related to LLC output

OHD;DAT

output load capacitance 15 − 50 pF output hold time CL=15pF − 14 − ns propagation delay from

CL=15pF − 24 − ns positive edge of LLC output

ICLK output timing

δ duty factors for t

output load capacitance 15 − 50 pF cycle time 31 − 45 ns

ICLKH/tICLKL

35 − 65 %

−6

2004 Jun 29 98

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Data and control signal output timing I port, related to ICLK output (for IPCK[1:0] 87H[5:4] = 00 is default)

OHD;DAT

o(d)

ICLK input timing

Notes

1. The levels must be measured with load circuits; 1.2 kΩ at 3 V (TTL load); CL= 50 pF.

2. The effects of rise and fall times are included in the calculation of t drawings and conditions illustrated in Fig.52.

3. The crystal oscillator drive level is 0.28 mW (typ.).

rise time 0.6 to 2.6 V −−5ns fall time 2.6 to 0.6 V −−5ns

output load capacitance at

15 − 50 pF

all outputs output data hold time CL=15pF − 12 − ns output delay time CL=15pF − 22 − ns

cycle time 31 − 100 ns

OHD;DAT

and tPD. Timings and levels refer to

16 TIMING

16.1 Digital video encoder part

handbook, full pagewidth

PIXCLKO

d(CLKD)

PIXCLKI

PDn

any output

HIGH

HD;DAT

o(h)

o(d)

PIXCLK

SU;DAT

HD;DAT

SU;DAT

0.5V V

MBL789

DD(DVO)

Fig.48 Input/output timing specification.

2004 Jun 29 99

Philips Semiconductors Product speciﬁcation

HD-CODEC SAA7108AE; SAA7109AE

handbook, full pagewidth

HSVGC

CBO

XOFS

IDEL

XPIX

HLEN

MHB905

Fig.49 Horizontal input timing.

handbook, full pagewidth

HSVGC

VSVGC

CBO

YOFS

Fig.50 Vertical input timing.

2004 Jun 29 100

YPIX

MHB906

Philips SAA7108AE, SAA7109AE User Guide

Specifications and Main Features

Frequently Asked Questions

User Manual

1 FEATURES

1.1 Video decoder

1.2 Video scaler

1.3 Video encoder

1.4 Common features

2 APPLICATIONS

3 GENERAL DESCRIPTION

4 ORDERING INFORMATION

5 QUICK REFERENCE DATA

6 BLOCK DIAGRAMS

7 PINNING

8.1 Reset conditions

8.2 Input formatter

8.3 RGB LUT

8.4 Cursor insertion

8.5 RGB Y-CB-CR matrix

8.6 Horizontal scaler

8.10 Oscillator and Discrete Time Oscillator (DTO)

8.8 FIFO

8.9 Border generator

8.11 Low-pass Clock Generation Circuit (CGC)

8.12 Encoder

8.13 RGB processor

8.14 Triple DAC

8.15 HD data path

8.16 Timing generator

8.17 Pattern generator for HD sync pulses

8.18 I2C-bus interface

8.19 Power-down modes

8.20 Programming the graphics acquisition scaler of the video encoder

8.21 Input levels and formats

9 FUNCTIONAL DESCRIPTION OF DIGITAL VIDEO DECODER PART

9.1 Decoder

9.2 Decoder output formatter

9.3 Scaler

10.1 Analog terminals

10.2 Audio clock signals

10.3 Clock and real-time synchronization signals

10.4 Video expansion port (X port)

10.5 Image port (I port)

10.6 Host port for 16-bit extension of video data I/O (H port)

10.7 Basic input and output timing diagrams for the I and X ports

11 BOUNDARY SCAN TEST

11.1 Initialization of boundary scan circuit

12 LIMITING VALUES

13 THERMAL CHARACTERISTICS

14 CHARACTERISTICS OF THE DIGITAL VIDEO ENCODER PART

15 CHARACTERISTICS OF THE DIGITAL VIDEO DECODER PART

16 TIMING

16.1 Digital video encoder part