Philips SAA6752HS User Manual

INTEGRATED CIRCUITS

DATA SH EET

SAA6752HS

MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer

Product speciﬁcation Supersedes data of 2002 Dec 09

2004 Jan 26

Philips Semiconductors Product speciﬁcation

MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer

CONTENTS

1 FEATURES

1.1 Video input and preprocessing

1.2 Video compression

1.3 Audio input

1.4 Audio compression

1.5 Stream multiplexer

1.6 Output interface

1.7 Control domain

1.8 Other features 2 GENERAL DESCRIPTION

2.1 General

2.2 Application fields 3 QUICK REFERENCE DATA 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING 7 FUNCTIONAL DESCRIPTION

7.1 System operation

7.2 Digital video input

7.3 Video compression

7.4 Digital audio input

7.5 Audio compression

7.6 SDRAM interface

7.7 Multiplexer

7.8 MPEG stream output port

7.9 Clock generation

7.10 Power control and reset

7.11 I2C-bus interface

7.12 Exception handling

SAA6752HS

8 BOUNDARY SCAN TEST

8.1 Initialization of boundary scan circuit

8.2 Device identification codes 9I

10 LIMITING VALUES 11 THERMAL CHARACTERISTICS 12 CHARACTERISTICS 13 PACKAGE OUTLINE 14 SOLDERING

14.1 Introduction to soldering surface mount

14.2 Reflow soldering

14.3 Wave soldering

14.4 Manual soldering

14.5 Suitability of surface mount IC packages for

15 DATA SHEET STATUS 16 DEFINITIONS 17 DISCLAIMERS 18 PURCHASE OF PHILIPS I2C COMPONENTS

C-BUS CONTROL AND STATUS

REGISTERS

packages

wave and reflow soldering methods

2004 Jan 26 2

Philips Semiconductors Product speciﬁcation

MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer

1 FEATURES

1.1 Video input and preprocessing

• Digital YUVinputaccording to 27 MHz) and

• Support of enhanced containing decoded VBI data readable via I2C-bus; Closed Caption (CC), Wide Screen Signalling (WSS) and copyright information with Copy Generation Management System (CGMS)

• Processing of non-broadcast video signals from analog VCR according to IEC 756

• Twovideo clockinput pins forswitching two digitalvideo sources

•

“ITU-R BT.601”

Standard Interchange Format (SIF)

• 4:2:2to4:2:0 colour format conversion

• Decimation filtering for all format conversions

• Adaptive median filterand motion compensated filter for

input noise reduction.

1.2 Video compression

• Real-time MPEG-2 encoding compliant to Main Profile at Main Level (MP@ML) for 625 and 525 interlaced line systems

• Supported resolutions: D1, 2/3D1, 1/2D1 and SIF

• IPB frame, IP frame and I frame only encoding

supported at all modes

• Supported bit rates: up to 25 Mbit/s I-only encoding; up to 15 Mbit/s IP-only or IBP encoding.

• Variable video bit rate mode for constant picture quality and constant bit rate mode to gain optimum picture quality from a fixed channel transfer rate

• Access to bit rate control parameters whilst encoding to support external real-time control algorithms (e.g. constrained variable bit rate control)

• Programmable Group Of Pictures (GOP) structure

• Innovative motion estimation with wide search range

• Adaptive quantization

• Motion compensated noise filter.

“ITU-R BT.601”

“ITU-R BT.656”

format conversion to 1/2D1, 2/3D1 and

“ITU-R BT.656”

input format

(8 bits at

SAA6752HS

1.3 Audio input

• Audio inputs: I2S format or EIAJ format (16, 18 or 20 bits), master or slave mode at 32, 44.1 and 48 kHz

• Two digital I2S input ports for selection between two digital audio sources

• Audio clock generation: 256fs or 384fs (where fs= 48 kHz) locked to video frame rate (if video is present and locking is enabled)

• Sample rate conversion to 48 kHz (locked to video frame rate if enabled) for slave mode operation in all modes except Digital Versatile Disc (DVD) compliant bypass.

1.4 Audio compression

• Dolby

• MPEG-1 layer 2 audio encoding at 256 kbit/s or

• Input data bypass for Linear Pulse Code Modulation

• Preamble Pc, Preamble Pd and bit stream information

• Audio mute via I2C-bus control for all modes except

(1) Dolby is a registered trademark of Dolby Laboratories

(2) AC-3 is a registered trademark of Dolby Laboratories

(1)

Digital Consumer Encoding (DDCE) also known as AC-3 256 kbit/s or 384 kbit/s (only for SAA6752HS/V103)

384 kbit/s

(LPCM) and compressed audio data [MPEG-1, MPEG-2, Dolby Digital (DD) and Digital Theatre System (DTS)] according to IEC 61937

captured for identification of modes during bypass of compressed audio data for MPEG-1, MPEG-2, DD and DTS according to IEC 61937

DVD-compliant bypass.

Licensing Corporation.

(2)

2 channel audio encoding at

2004 Jan 26 3

Philips Semiconductors Product speciﬁcation

MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer

1.5 Stream multiplexer

• Multiplexingof video and audiostreamsaccording to the MPEG-2 systems standard (

• Generation and output of MPEG-2 Transport Streams (TS), MPEG-2 Program Streams (PS), Packetized Elementary Streams (PES) and Elementary Streams (ES) compliant to the DVD, D-VHS and DVB standards

• MPEG time stamp (PTS/DTS/SCR/PCR) generation and insertion (synchronization)

• Insertion of metadata

• Optional generation of empty time slots for subsequent

insertion of application specific data packets

• Optionalinsertion ofuser data inthe GOP headerand in the picture header

• Optional automatic insertion of Closed Caption data according to DVD or ATSC standard

• Optional generation of transport streams with variable bit rate.

1.6 Output interface

• Parallel interface 8-bit master/slave output

• 3-state output port

• Glueless interfacing with IEEE 1394 chip sets (for

example, PDI 1394 L11)

• Data Expansion Bus Interface (DEBI) interface.

1.7 Control domain

• All control done via I2C-bus

• I2C-bus slave transceiver up to 400 kbit/s

• I2C-bus slave address select pin

• Host interrupt flag pin.

1.8 Other features

• Single external clock or single crystal 27 MHz

• Separate 27 MHz system clock output

• Interface voltage 3.3 V

• TTL compatible digital outputs

• Power supply voltage 3.3 and 2.5 V

• Boundary Scan Test (BST) supported

• Power-down mode

• Single SDRAM system memory (16 Mbit@16 bit or

64 Mbit@16 bit).

“ISO 13818-1”

)

SAA6752HS

2 GENERAL DESCRIPTION

2.1 General

Philips Semiconductors’ second generation real time MPEG-2 encoder, the SAA6752HS, is a highly integrated single-chip audio and video encoding solution with flexible multiplexing functionality. With our expertise in two critical areas for consumer video encoding, noise filtering and motion estimation, we have pushed the boundaries for video quality even further, providing enhanced quality for low bit rates and enabling increased recording times for a given storage capacity. The SAA6752HS will also enable a key driver for new consumer digital recording applications and system cost reduction. By integrating all audio encoding and multiplexing functionality we will be moving from a three chip to a one chip system, with cost efficient design and process technology, thus providing a truly low cost, high quality encoding system.

The SAA6752HS/V104 is intended for customers whose application does not require the DDCE function.

The SAA6752HS gives significant advantages to customers developing digital recording applications:

• Fast time-to-market and low development resources. By adding a simple external video input

processor IC, an audio analog-to-digital converter, and an external SDRAM, analog video and audio sources are compressed into high quality MPEG-2 video and MPEG-1layer 2 or AC-3 audiostreams,multiplexed into a single program or transport stream for simple connection to various storage media or broadcast media. Hence, making designeffort for our customers a minimum, as well as removing the need for in-depth experience in MPEG encoding.

• Low system host resources. All video and audio encoding algorithms and software arerun onan internal

(1)

MIPS small amount of communication from the system host processor to set up and control required encoding parameters via the I2C-bus.

processor. The SAA6752HS only requires a

2004 Jan 26 4

(1) MIPS is a registered trademark of MIPS Technologies.

Philips Semiconductors Product speciﬁcation

MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer

2.2 Application ﬁelds

2.2.1 DVD BASED OPTICAL DISC RECORDERS (DVD+RW, DVD-RW, DVD-RAM)

Emerging optical disc based recording systems target to replace the existing consumer recording (VCR) and playback (DVD and VCD) products. The first generation recordable DVD based products will want to maximise recording times for the 4.7 Gbyte storage capacity. For these systems the SAA6752HS is critical, with its superior noise filtering and motion estimation, in enabling high quality at low bit rates.

Playback compatibility with existing DVD decoding solutions will also be important, which is why the SAA6752HS provides Dolby digital consumer (AC-3) audio encoding to allow playback through existing players implementing DDCE (AC-3) decoding dominant in current DVD platforms.

The DVD stream is based on MPEG Program Stream (PS). The SAA6752HS directly outputs MPEG PS compliant to the DVD standard.

SAA6752HS

2.2.3 DIGITAL VCR (DVHS) RECORDING A DVHS player records streams based on MPEG

Transport Streams (TS) packedin logical tape tracks. The SAA6752HS output streams are compliant with DVHS standard requirements.

2.2.4 VIDEO EDITING/TRANSMISSION/SURVEILLANCE/

CONFERENCING

The SAA6752HS can operate as a stand-alone device in all the above applications. The SAA6752HS full features and flexibility allows customers to tailor functionality and performance to specific application requirements. All required control settings such as GOP size and bit rate modes can be selected via the I2C-bus.

2.2.2 HDD BASED TIME SHIFT RECORDING

Hard Disc Drive (HDD) based time-shift systems enable Personalized TV (PTV) functionality, providingconsumers with new powers of control over what and when to watch broadcast content. With the audio and video content recorded digitally, identification, search and retrieval becomes a ‘no brainer’ task as compared to traditional VCR functionality. Combine this with electronic program guides and intelligent control, and the PTV can also analyse the viewers watching habits to search for programs likely to be of interest and automatically recorded in anticipation of the viewers preferences.

Since HDD recorders are closed systems, the recording format stream can be proprietary. The SAA6752HS flexiblemultiplexingformats support a number ofrecording stream formats for HDD including MPEG Transport Stream (TS) or MPEG Packetized Elementary Stream (PES).

2004 Jan 26 5

Philips Semiconductors Product speciﬁcation

MPEG-2 video and MPEG-audio/AC-3

SAA6752HS

audio encoder with multiplexer

3 QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

DDP

DDCO

DDA

DD(tot)

tot

DCXO

SDRAM

SCL

B output bit-rate 1.5 − 25 Mbit/s V

amb

digital supply voltage (pad cells) 3.0 3.3 3.6 V digital supply voltage (core) 2.3 2.5 2.7 V analog supply voltage (oscillator and PLL) 2.3 2.5 2.7 V total analog plus digital supply current 407 453 525 mA total power dissipation 0.95 1.16 1.48 W quartz frequency (digital controlled tuning) 27 × [1 − (200 × 10−6)] 27 27 × [1 + (200 × 10−6)] MHz SDRAM clock frequency − 108 − MHz I2C-bus input clock frequency 100 − 400 kHz

HIGH-level digital input voltage 1.7 − 3.6 V LOW-level digital input voltage −0.5 − +0.7 V HIGH-level digital output voltage V

− 0.4 − V

DDP

V LOW-level digital output voltage 0 − 0.4 V ambient temperature 0 − 70 °C

4 ORDERING INFORMATION

PACKAGE

TYPE NUMBER

NAME DESCRIPTION VERSION

SAA6752HS/V103 SAA6752HS/V104

(1)(3)

SQFP208 plastic shrink quad ﬂat package; 208 leads (lead length 1.3 mm);

(2)(4)

body 28 × 28 × 3.4 mm; high stand-off height

Notes

1. MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer.

2. MPEG-2 video and MPEG-audio encoder with multiplexer, but without AC-3 audio encoder.

3. SAA6752HS/V103 is a replacement of SAA6752HS/V101 with enhanced functionality.

4. SAA6752HS/V104 is a replacement of SAA6752HS/V102 with enhanced functionality.

SOT316-1

2004 Jan 26 6

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2004 Jan 26 7

16 Mbit @ 16-bit or 64 Mbit @ 16-bit audio clock

system

clock

reference

SDRAM-INTERFACE

STREAM DOMAIN SCHEDULER

digital

video

input

SAA6752HS

VIDEO

FRONT-END

ROMRAM

ull pagewidth

SDRAM

system clock

output

SYSTEM

CLOCK

REFERENCE

CLOCK 27 MHz

external clock

5 BLOCK DIAGRAM

Philips Semiconductors Product speciﬁcation

MPEG-2 video and MPEG-audio/AC-3

audio encoder with multiplexer

digital audio

input

I2C-BUS

C-bus

AUDIO

INTERFACE

GPIO RAM ROM TAP

host interrupt reset boundary scan

AUDIO

COMPRESSION

RESET

CONTROL

VIDEO

COMPRESSION

MIPS

CPU

PI-bus

STREAM

MULTIPEXER

Fig.1 Block diagram.

OUTPUT

INTERFACE

STATIC

MEM

DEBUG

ONLY

MHC128

MPEG output

SAA6752HS

Philips Semiconductors Product speciﬁcation

MPEG-2 video and MPEG-audio/AC-3

SAA6752HS

audio encoder with multiplexer

6 PINNING

max

SYMBOL PIN INPUT/OUTPUT

SSP

1 ground − pad ground SDATA1 2 input − I2S-bus serial data input port 1 with internal pull-down resistor SCLK1 3 input/output 4 I2S-bus serial clock port 1 with internal pull-down resistor SWS1 4 input/output 4 I2S-bus word select port 1 with internal pull-down resistor V

DDP

5 supply − pad ring supply voltage (3.3 V) SDATA2 6 input/output 4 I2S-bus serial data port 2 with internal pull-down resistor SCLK2 7 input/output 4 I2S-bus serial clock port 2 with internal pull-down resistor SWS2 8 input/output 4 I2S-bus word select port 2 with internal pull-down resistor ACLK 9 output 4 audio clock output (256fs or 384fs) V

SSP

10 ground − pad ground

IDQ 11 input − reserved input with internal pull-down resistor; (recommended

YUV0 12 input − video input signal bit 0 (LSB) YUV1 13 input − video input signal bit 1 YUV2 14 input − video input signal bit 2 YUV3 15 input − video input signal bit 3 YUV4 16 input − video input signal bit 4 YUV5 17 input − video input signal bit 5 YUV6 18 input − video input signal bit 6 YUV7 19 input − video input signal bit 7 (MSB) V

SSP

20 ground − pad ground HSYNC 21 input − horizontal sync input (video) with internal pull-down resistor VSYNC 22 input − vertical sync input (video) with internal pull-down resistor FID 23 input − video ﬁeld identiﬁcation input (odd/even ﬁeld) with internal

VCLK1 24 input − video clock input 1 (27 MHz) with internal pull-down resistor V

SSCO

DDCO

DDP

25 ground − core ground

26 ground − core ground

27 supply − core supply voltage (2.5 V)

28 supply − core supply voltage (2.5 V)

29 supply − pad ring supply voltage (3.3 V) VCLK2 30 input − video clock input 2 (27 MHz) with internal pull-down resistor PDOAV 31 3-state output 4 parallel stream data output for audio/video identiﬁer PDIDS 32 input − parallel stream data input for data strobe [request for packet in

PDOSYNC 33 3-state output 4 parallel stream data output for packet sync V

SSP

34 ground − pad ground PDOVAL 35 3-state output 4 parallel stream data valid output with internal pull-up resistor PDO0 36 3-state output 4 parallel stream data output bit 0 (LSB)

(1)

(mA)

to connect to pin V

DESCRIPTION

)

SSP

pull-down resistor

Data Expansion Bus Interface(DEBI) slave mode] with internal pull-up resistor

2004 Jan 26 8

Philips Semiconductors Product speciﬁcation

MPEG-2 video and MPEG-audio/AC-3

SAA6752HS

audio encoder with multiplexer

max

SYMBOL PIN INPUT/OUTPUT

PDO1 37 3-state output 4 parallel stream data output bit 1 PDO2 38 3-state output 4 parallel stream data output bit 2 V

DDP

39 supply − pad ring supply voltage (3.3 V) PDO3 40 3-state output 4 parallel stream data output bit 3 PDO4 41 3-state output 4 parallel stream data output bit 4 PDO5 42 3-state output 4 parallel stream data output bit 5 PDO6 43 3-state output 4 parallel stream data output bit 6 V

SSP

44 ground − pad ground PDO7 45 3-state output 4 parallel stream data output bit 7 (MSB) PDIOCLK 46 input/output 4 parallel stream clock input/output I2CADDRSEL 47 input − I2C-bus address select input with internal pull-up resistor SD_DQ15 48 input/output 8 SDRAM data input/output bit 15 (MSB) V

DDP

49 supply − pad ring supply voltage (3.3 V) SD_DQ0 50 input/output 8 SDRAM data input/output bit 0 (LSB) SD_DQ14 51 input/output 8 SDRAM data input/output bit 14 SD_DQ1 52 input/output 8 SDRAM data input/output bit 1 V

SSP

53 ground − pad ground SD_DQ13 54 input/output 8 SDRAM data input/output bit 13 SD_DQ2 55 input/output 8 SDRAM data input/output bit 2 SD_DQ12 56 input/output 8 SDRAM data input/output bit 12 V

DDP

57 supply − pad ring supply voltage (3.3 V) SD_DQ3 58 input/output 8 SDRAM data input/output bit 3 SD_DQ11 59 input/output 8 SDRAM data input/output bit 11 SD_DQ4 60 input/output 8 SDRAM data input/output bit 4 SD_DQ10 61 input/output 8 SDRAM data input/output bit 10 V

SSP

62 ground − pad ground SD_DQ5 63 input/output 8 SDRAM data input/output bit 5 SD_DQ9 64 input/output 8 SDRAM data input/output bit 9 SD_DQ6 65 input/output 8 SDRAM data input/output bit 6 SD_DQ8 66 input/output 8 SDRAM data input/output bit 8 V

DDP

67 supply − pad ring supply voltage (3.3 V) SD_DQ7 68 input/output 8 SDRAM data input/output bit 7 SD_DQM1 69 output 8 SDRAM data mask enable output bit 1 SD_DQM0 70 output 8 SDRAM data mask enable output bit 0 (LSB) SD_WE 71 output 8 SDRAM write enable output (active LOW) V

SSP

72 ground − pad ground SD_CAS 73 output 8 SDRAM column address strobe output (active LOW) SD_CLK 74 output 8 SDRAM clock output SD_RAS 75 output 8 SDRAM row address strobe output (active LOW) SD_CKE 76 output 8 SDRAM clock enable output

(1)

(mA)

DESCRIPTION

2004 Jan 26 9

Philips Semiconductors Product speciﬁcation

MPEG-2 video and MPEG-audio/AC-3

SAA6752HS

audio encoder with multiplexer

max

SYMBOL PIN INPUT/OUTPUT

SSCO

DDCO

DDP

77 ground − core ground

78 ground − core and substrate ground

79 supply − core supply voltage (2.5 V)

80 supply − core supply voltage (2.5 V)

81 supply − pad ring supply voltage (3.3 V) SD_CS 82 output 8 SDRAM chip select output (active LOW) SD_A13 83 output 8 SDRAM address output bit 13 (bank selection for 64 Mbit) SD_A9 84 output 8 SDRAM address output bit 9 SD_A8 85 output 8 SDRAM address output bit 8 V

SSP

86 ground − pad ground SD_A11 87 output 8 SDRAM address output bit 11 (bank selection for 16 Mbit) SD_A7 88 output 8 SDRAM address output bit 7 SD_A12 89 output 8 SDRAM address output bit 12 (bank selection for 64 Mbit) SD_A6 90 output 8 SDRAM address output bit 6 V

DDP

91 supply − pad ring supply voltage (3.3 V) SD_A10 92 output 8 SDRAM address output bit 10 SD_A5 93 output 8 SDRAM address output bit 5 SD_A0 94 output 8 SDRAM address output bit 0 (LSB) SD_A4 95 output 8 SDRAM address output bit 4 V

SSP

96 ground − pad ground SD_A1 97 output 8 SDRAM address output bit 1 SD_A3 98 output 8 SDRAM address output bit 3 SD_A2 99 output 8 SDRAM address output bit 2 SD_DQM3 100 output 8 reserved (do not connect) V

DDP

101 supply − pad ring supply voltage (3.3 V) SD_DQM2 102 output 8 reserved (do not connect) SD_DQ31 103 input/output 8 reserved (do not connect) SD_DQ16 104 input/output 8 reserved (do not connect) V

SSP

105 ground − pad ground SD_DQ30 106 input/output 8 reserved (do not connect) SD_DQ17 107 input/output 8 reserved (do not connect) SD_DQ29 108 input/output 8 reserved (do not connect) V

DDP

109 supply − pad ring supply voltage (3.3 V) SD_DQ18 110 input/output 8 reserved (do not connect) SD_DQ28 111 input/output 8 reserved (do not connect) SD_DQ19 112 input/output 8 reserved (do not connect) SD_DQ27 113 input/output 8 reserved (do not connect) V

SSP

114 ground − pad ground SD_DQ20 115 input/output 8 reserved (do not connect) SD_DQ26 116 input/output 8 reserved (do not connect)

(1)

(mA)

DESCRIPTION

2004 Jan 26 10

Philips Semiconductors Product speciﬁcation

MPEG-2 video and MPEG-audio/AC-3

SAA6752HS

audio encoder with multiplexer

max

SYMBOL PIN INPUT/OUTPUT

SD_DQ21 117 input/output 8 reserved (do not connect) SD_DQ25 118 input/output 8 reserved (do not connect) V

DDP

119 supply − pad ring supply voltage (3.3 V) SD_DQ22 120 input/output 8 reserved (do not connect) SD_DQ24 121 input/output 8 reserved (do not connect) SD_DQ23 122 input/output 8 reserved (do not connect) EXTCLK 123 input − 27 MHz external clock input with internal pull-up resistor V V

SSP SSA

124 ground − pad ground

125 ground − oscillator analog ground XTALI 126 analog input − crystal oscillator input (27 MHz); note 2 XTALO 127 analog output − crystal oscillator output (27 MHz) V

DDA

SSCO

DDCO

DDP

128 supply − oscillator analog supply voltage (2.5 V)

129 ground − core ground

130 ground − core ground

131 supply − core supply voltage (2.5 V)

132 supply − core supply voltage (2.5 V)

133 supply − pad ring supply voltage (3.3 V) TDI 134 input − boundary scan test data input; pin must ﬂoat or set to HIGH

TMS 135 input − boundary scan test mode select; pin must ﬂoat or set to HIGH

TCK 136 input − boundary scan test clock; pin must be set to LOW during

TDO 137 3-state output 4 boundary scan test data output; pin not active during normal

SSP

138 ground − pad ground TRST 139 input − test reset input (active LOW), for boundary scan test (with

CLKOUT 140 output 4 27 MHz system clock output TEST0 141 input/output 4 reserved (do not connect) TEST1 142 input/output 4 reserved (do not connect) V

DDP

143 supply − pad ring supply voltage (3.3 V) TEST2 144 input/output 4 reserved (do not connect) SDA 145 input/open-drain

output

SCL 146 input/open-drain

output RESET 147 input − reset input (active LOW); with internal pull-up resistor V

SSP

148 ground − pad ground

RTS 149 output 4 reserved (do not connect); Universal Asynchronous

(1)

(mA)

DESCRIPTION

during normal operating; with internal pull-up resistor; note 3

normal operating; with internal pull-up resistor; note 3

operating; with 3-state output; note 3

internal pull-up resistor); notes 3 and 4

− I2C-bus serial data input/output

− I2C-bus serial clock input/output

Receiver/Transmitter (UART) request to send output (active LOW)

2004 Jan 26 11

Philips Semiconductors Product speciﬁcation

MPEG-2 video and MPEG-audio/AC-3

SAA6752HS

audio encoder with multiplexer

max

SYMBOL PIN INPUT/OUTPUT

CTS 150 input − reserved (recommended connect to pin V

RXD 151 input − reserved (recommended connect to pin V

TXD 152 output 4 reserved (do not connect); UART transmit data V

DDP

153 supply − pad ring supply voltage (3.3 V) SM_LB 154 input/output 4 reserved (do not connect) SM_UB 155 input/output 4 reserved (do not connect) H_IRF 156 3-state output 4 host interrupt ﬂag output; with internal pull-up resistor

SSP

157 ground − pad ground SM_OE 158 output 4 reserved (do not connect); static memory output enable output

SM_A9 159 output 4 reserved (do not connect); static memory address output bit 9 SM_A10 160 output 4 reserved (do not connect); static memory address output bit 10 V

DDP

161 supply − pad ring supply voltage (3.3 V) SM_A8 162 output 4 reserved (do not connect); static memory address output bit 8 SM_A11 163 output 4 reserved (do not connect); static memory address output bit 11 SM_A7 164 output 4 reserved (do not connect); static memory address output bit 7 SM_A12 165 output 4 reserved (do not connect); static memory address output bit 12 V

SSP

166 ground − pad ground SM_A6 167 output 4 reserved (do not connect); static memory address output bit 6 SM_A13 168 output 4 reserved (do not connect); static memory address output bit 13 SM_A5 169 output 4 reserved (do not connect); static memory address output bit 5 SM_A14 170 output 4 reserved (do not connect); static memory address output bit 14 V

DDP

171 supply − pad ring supply voltage (3.3 V) SM_WE 172 output 4 reserved (do not connect); static memory write enable output

SM_D7 173 input/output 4 reserved (do not connect); static memory data input/output

SM_D8 174 input/output 4 reserved (do not connect); static memory data input/output

SM_D6 175 input/output 4 reserved (do not connect); static memory data input/output

SSP

176 ground − pad ground SM_D9 177 input/output 4 reserved (do not connect); static memory data input/output

SM_D5 178 input/output 4 reserved (do not connect); static memory data input/output

SM_D10 179 input/output 4 reserved (do not connect); static memory data input/output

(1)

(mA)

DESCRIPTION

); UART clear to

DDP

send input; external static memory select input (active LOW); with internal pull-up resistor

); UART receive

DDP

data; internal boot select input; with internal pull-up resistor

(active LOW)

bit 7 with internal pull-down resistor

bit 8 with internal pull-down resistor

bit 6 with internal pull-down resistor

bit 9 with internal pull-down resistor

bit 5 with internal pull-down resistor

bit 10 with internal pull-down resistor

2004 Jan 26 12

Philips Semiconductors Product speciﬁcation

MPEG-2 video and MPEG-audio/AC-3

SAA6752HS

audio encoder with multiplexer

max

SYMBOL PIN INPUT/OUTPUT

SM_D4 180 input/output 4 reserved (do not connect); static memory data input/output

SSCO

DDCO

DDP

181 ground − internal pre-driver and substrate ground

182 ground − core ground

183 supply − core supply voltage (2.5 V)

184 supply − internal pre-driver supply voltage (2.5 V)

185 supply − pad ring supply voltage (3.3 V) SM_D11 186 input/output 4 reserved (do not connect); static memory data input/output

SM_D3 187 input/output 4 reserved (do not connect); static memory data input/output

SM_D12 188 input/output 4 reserved (do not connect); static memory data input/output

SM_D2 189 input/output 4 reserved (do not connect); static memory data input/output

SSP

190 ground − pad ground SM_D13 191 input/output 4 reserved (do not connect); static memory data input/output

SM_D1 192 input/output 4 reserved (do not connect); static memory data input/output

SM_D14 193 input/output 4 reserved (do not connect); static memory data input/output

SM_D0 194 input/output 4 reserved (do not connect); static memory data input/output

DDP

195 supply − pad ring supply voltage (3.3 V) SM_D15 196 input/output 4 reserved (do not connect); static memory data input/output

SM_CS3 197 output 4 reserved (do not connect); static memory chip select output for

SM_A4 198 output 4 reserved (do not connect); static memory address output bit 4 SM_A3 199 output 4 reserved (do not connect); static memory address output bit 3 V

SSP

200 ground − pad ground SM_A2 201 output 4 reserved (do not connect); static memory address output bit 2 SM_A15 202 output 4 reserved (do not connect); static memory address output bit 15 SM_A1 203 output 4 reserved (do not connect); static memory address output bit 1 SM_A16 204 output 4 reserved (do not connect); static memory address output bit 16 V

DDP

205 supply − pad ring supply voltage (3.3 V) SM_A0 206 output 4 reserved (do not connect); static memory address output bit 0

SM_A17 207 output 4 reserved (donot connect);static memory address output bit 17

SM_CS0 208 output 4 reserved (do not connect)

(1)

(mA)

DESCRIPTION

bit 4 with internal pull-down resistor

bit 11 with internal pull-down resistor

bit 3 with internal pull-down resistor

bit 12 with internal pull-down resistor

bit 2 with internal pull-down resistor

bit 13 with internal pull-down resistor

bit 1 with internal pull-down resistor

bit 14 with internal pull-down resistor

bit 0 (LSB) with internal pull-down resistor

bit 15 (MSB) with internal pull-down resistor

external ROM or RAM (active LOW)

(LSB)

(MSB)

2004 Jan 26 13

Philips Semiconductors Product speciﬁcation

MPEG-2 video and MPEG-audio/AC-3

SAA6752HS

audio encoder with multiplexer

Notes

1. All input pins, input/output pins (in input mode), output pins (in 3-state mode) and open-drain output pins are limited to 3.3 V.

2. If used with external clock source the input voltage has to be limited to 2.5 V.

3. In accordance with the

4. Special function of pin TRST: a) For board designs without boundary scan implementation, pinTRST must be connected to ground. b) PinTRST provides easy initialization of the internal BST circuit. By applying a LOW level it can be used to force

the internal Test Access Port (TAP) controller to the Test-Logic-Reset state (normal operating) immediately.

“IEEE 1149.1”

handbook, halfpage

standard.

208

157

156

SAA6752HS

Fig.2 Pin configuration.

104

105

MHC129

2004 Jan 26 14

Philips Semiconductors Product speciﬁcation

MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer

7 FUNCTIONAL DESCRIPTION

7.1 System operation

7.1.1 GENERAL

The SAA6752HS has a multi-processor architecture. The different processing and control modules are not lockedto each otherbut run independentlywithin the limits of the global scheduling. The data transfer between the processing units is carried out via FIFO memories or the external SDRAM. The device is configured and the operation modes are selected via the I2C-bus.

7.1.2 OPERATING MODES

There are five operating modes:

1. Idle. This mode is set after applying a hard reset (i.e. on power-up). In this mode the SAA6752HS can be initialized by the host to the required configuration. Video and audio processing is disabled. A hard reset always resets the SAA6752HS configuration parameters back to the default states.

SAA6752HS

2. Stop. In Stop mode, the video and audio input processing is enabled but the multiplexer output remains disabled. It is possible to read status information on the input video and audio signals via the I2C-bus. The SAA6752HS initialization settings cannot be modified, except to some specific dynamic encoding parameters (i.e. bit rate setting).

3. Encode. In this mode, the multiplexer output is enabled. Like Stop mode, only dynamic encoding parameters can be modified in this mode.

4. Paused. This mode allows the SAA6752HS to make seamless transitions. Restarting from Paused mode will generate a stream output with sequential time stamps and MPEG buffer model content.

5. Power-down. In this mode, the internal clock is disabled, sending the SAA6752HS into a (non-functional) power saving state. A hard reset will re-initialize the SAA6752HS.

handbook, full pagewidth

Power-

down

HARD RESET

SLEEP

HARD RESET

power

applied

RECONFIGURE

Idle

ENABLE

Stop Encode Paused

START

Fig.3 Mode transition diagram.

STOP

START

PAUSE

MHC130

2004 Jan 26 15

Philips Semiconductors Product speciﬁcation

MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer

7.1.3 MODE TRANSITION COMMANDS There are seven mode transition commands:

1. SOFT RESET. Like a hard reset, a soft reset can be applied in any mode, setting the SAA6752HS back to Idle mode and resetting all configuration parameters back to the default settings.

2. RECONFIGURE. This command sets the SAA6752HS back to Idle mode without resetting the configuration parameters back to the default settings.

3. ENABLE.This transition setsStopmode, enabling the video and audio input processing.

4. START. This transition sets Encode mode, enabling the multiplexer stream output. Note that if the SAA6752HS is commanded to start from the Idle mode, then the internal transition isvia the Stop mode.

5. STOP. This command will disable the multiplexer stream output, setting the SAA6752HS to Stop mode. Thecurrent GOP and/oraudio frame iscompleted and an end of sequence bit appended to the stream.

6. PAUSE. A PAUSE transitionwill cause themultiplexer to complete the current GOP and/or audio frame but no end of sequence bit is appended. The current MPEG buffer model contents are saved to provide a seamless transition on START.

7. SLEEP. This mode disables the internal clock.

8. FORCED RECONFIGURE. A STOP command whilst in the Encode mode will not work in case the video or audio input signalis interrupted,because for stopping, the SAA6752HS tries to finish the current GOP. The forced reconfigure command allows a mode transition back to the Idle state, without losing the actual configuration settings. The forced reconfiguration performs a soft reset and the automatic internal reprogramming of the I2C-bus registers. The forced reconfiguration will take about 200 ms; during the forcedreconfiguration all registervalues will changeto their default values before they are reprogrammed. Please note that outputs, which can be switched to high-impedance or to input mode, will not be active during the forced reconfiguration.

The SAA6752HS is not able to process any other commands during mode transitions. In this event, a get running mode request will return a busy flag. The completion of a mode transition can also be flagged as an event using the host interrupt pin.

SAA6752HS

7.2 Digital video input

7.2.1 GENERAL The video front-end processes an

compliant video stream for conversion to 4 :2:0 format (MP@ML). It includes synchronization, digital video signal processingthroughseveralfilters,subsampling,sliced/raw VBI data handling, and SDRAM address generation.

The video interface is designed for use with Philips SAA7114 digital multi-standard decoder or similar video decoders. The input interface accepts a digital video input streamaccording to 50 Hz and 720 pixels by 576 lines as well as 525 lines at 60 Hz and 720 pixels by 480 lines are covered. The video synchronization may either follow recommendation or can also be supplied by external signals (HSYNC, VSYNC and FID). The formatter module performs a colour conversion from 4 :2:2to4:2:0 format. Optionally, also SIF progressive downscaling and 2/3D1, 1/2D1 downscaling may be activated.

The SAA6752HS supports non-standard features of the SAA711x series of video input processors, such as hard-wired external synchronization signals (2 and 3-wire sync), special VCR playback signal streams (IEC 756 subset for VCR playback and still pictures), extraction of sliced data from the input video stream.

7.2.2 VIDEO FRONT-END CONFIGURATION OPTIONS The following configuration options can be selected from

the host:

• VIDEOINPUTPORT SELECTION. Two input clockpins are selectable.

• VIDEOINPUTFORMAT. 525 or625-lineformatscan be selected.

• VIDEO SYNC FORMAT. Various combinations and polarities of HSYNC, VSYNC and Field Information (FID) can be selected as the source of sync signal processing.

• VIDEO FILTER SETTINGS. Noise pre-filter and horizontal filters can be enabled and, if the default coefficients are not suitable for an application, new coefficients can be set.

• VIDEO FORMAT CONVERSION. Selection of conversion from D1 to 1/2D1, 2/3D1 or SIF progressive downscaling.

• VBI DATA EXTRACTION. VBI data extraction of WSS or CC data can be enabled.

“ITU-R-BT.601”

“ITU-R BT.601/605”

.625 lines standard at

“ITU-R-BT.656”

2004 Jan 26 16

Philips Semiconductors Product speciﬁcation

MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer

7.2.3 VIDEO ENCODER STATUS INFORMATION The following configuration option can be selected from

the host:

• VBI DATA: WSS and CC data can be read back via the I2C-bus.

7.2.4 DATA INPUT FORMAT

7.2.4.1 Interface deﬁnition

The data input interface uses 13 pins, all of which are inputs (see Table 1). Pins YUV0 to YUV7 carry video and synchronization data and 3 pins are reserved for control purposes. Two separate clock inputs allow two different signal sources to be used. The input clock can be asynchronous to the SAA6752HS system clock.

Table 1 List of pins data input port

PIN DESCRIPTION

YUV0 to YUV7 video input signal

(synchronous to VCLK)

FID odd/evenﬁeld identiﬁcation

signal; note 1

HSYNC horizontal synchronization

signal; note 1

VSYNC vertical synchronization

signal; note 1

VCLK1 or VCLK2 video clock signal (from

source 1 or 2)

Note

1. In ITU-T 656 mode sync signals are embedded in the

video data input stream. The external sync signals are not used.

SAA6752HS

recognized by a sync decoder. This checks the incoming field (FID), vertical sync and horizontal sync. It is possible to select either ‘internal synchronization’ (which means thatSAV/EAV codes inthe ITU 601/656 videostreamsare used) or externally applied hardware synchronization signals (which are given by the video input processor). In the latter case, 3 pin or 2 pin (V-sync and H-sync only) synchronization can be used.

Using 2 pin synchronization, the FID information is given by the timing of the transition of the V-sync. If a Vertical Blanking Interval (VBI) starts during H-sync, the next field will be the top field, otherwise it will be the bottom field.

A sync filter is used to inhibit sync signal triggering if an incorrect number of pixels or lines has been input. It also checks for the correct consecutive fields. The filter works on three different levels. An H-sync is only accepted after a predefined number of video cycles, a V-sync is only accepted after a programmed number of lines and a field is only accepted if top field follows bottom field or vice versa.

7.2.5.3 Horizontal and vertical shift

This function is intended for correction in synchronization of external sync signals if incorrectly timed. The amount of shift is programmable via the I2C-bus.

7.2.5.4 SAV/EAV decoder

A SAV/EAV decoder extracts the F, V and H bits from the video timing reference code. The decoder evaluates the protection bits tobe able tocorrect one bit errors withinthe codeword.If multiple bit errorsaredetected,theprotection bits are ignored and the field (F), vertical sync (V) and horizontal sync (H) bits are directly extracted from the code.

7.2.5 VIDEO SIGNAL PROCESSING

7.2.5.1 Acquisition of video data

Data is latched with the incoming video clock to provide robust data capture. Video clock and data is unlocked to the internal system clock therefore a clock domain bridge is used. This is performed by oversampling of video clock and data with 108 MHz.

7.2.5.2 Sync decoding and ﬁltering

To allow selection of the right portion of the video input stream, synchronization signals from the stream are

2004 Jan 26 17

7.2.5.5 Video format conversion

The SAA6752HS converts the input video input signal to the formats defined in Table 2 controlled by the I2C-bus command. A 4 : 2 : 2 to 4 : 2 : 0 colour conversion is performed as this is a pre-requisite of MPEG MP@ML encoding.

Philips Semiconductors Product speciﬁcation

MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer

Table 2 Format conversion

MODE

D1 720 2/3D1 480 1/2D1 352; note 1 SIF 352; notes 1 and 2

Notes

1. The 8 pixels at the right edge of the scaled picture are

not encoded.

2. Top field only.

7.2.6 VIDEO FILTERING

7.2.6.1 Adaptive mean ﬁlter

The SAA6752HS uses an adaptive mean filter. There are three different filter modes that can be selected: median, averaging or no filter.

The median algorithm provides better noise performance and is well suited to suppress single noise spikes without degrading the signal edges. The averaging algorithm is a standard low-pass filter so has greater impact on signal edges.

The default threshold and gaincoefficients ofthis filtercan beoverwrittenvia the I2C-bustoallow user optimizationfor different applications.

7.2.6.2 Horizontal pre-ﬁlter/decimation ﬁlter

There is ahorizontal filterfor Y and C andthis canoperate as a pre-filter or decimation filter. It is a symmetrical FIR filter with up to 8 coefficients programmable via the I2C-bus.

7.2.6.3 Vertical chrominance ﬁltering

For 4 :2:2to4:2:0 conversion, vertical filtering and subsampling of the chrominance is performed. The sequenceofcoefficients is mirrored intopandbottomfield. This generates the right phases of the chrominance samples between the luminance samples (a non co-sited sampling scheme).

PICTURE FORMAT

(PIXEL/LINES)

SAA6752HS

7.2.7 VBI DATA EXTRACTION The SAA6752HS supports the extraction of WSS and CC

data using two independent VBI data extractor modules. The data is available via the I2C-bus.

The following VBI data formats are supported: Closed Caption (CC525 and CC625) and Wide Screen Signalling (WSS525 and WSS625). For CC525, CC625 and WSS625 the sliceddata from a video inputprocessor (e.g. SAA7114, SAA7115 or SAA7118) are extracted from the digital video input signal and can be read via the I2C-bus. For WSS525 an internal data slicer is available which slices the oversampled raw data, which are delivered by the video input processor. The extracted WSS525 signal can be read via the I2C-bus.

Optionally the automatic insertion of extracted Closed Caption data into the user data area of a video stream is possible (for details see Section 7.3.8).

7.3 Video compression

7.3.1 GENERAL Compression of video data is performed by the video

compressor block; see Fig.4. The input to this block is the uncompressed video information pre-processed by the video front-end and stored in external SDRAM memory. The output is a compressed video stream, compliant to MPEG-2Video ElementaryStream (VES) upto slice level. Controlling information (for example, quantizer step size) as well as the bit stream for higher layers of the VES is generated by the embedded MIPS processor of the SAA6752HS.

The video compressor contains several subblocks. The MacroBlock Processor (MBP) performs generation of video ES on macroblock level. Controlling parameters for this task and MB headers as well as slice headers are generated by the core control subblock. Bitstream formatting and concatenation of MBP bitstream and header information is done by the subblocks pre-packer and packer.

2004 Jan 26 18

Philips Semiconductors Product speciﬁcation

MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer

7.3.2 VIDEO ENCODER CONFIGURATION OPTIONS

The following configuration options can be selected from the host:

• VIDEO COMPRESSION SETTINGS. I, IP and IPB encoding with various GOP structures can be selected.

• ENCODER BIT RATE. The bit rate for variable bit rate or constant bit rate modescan beprogrammed usingbit rate and quantization control parameters. These parameterscan be adjustedwhilst encoding, notjustset at initialization.

• ENCODER PERFORMANCE TUNING. The ability for the user to tune encoding performance is provided by allowing control of adaptive quantizationdepth. Alsothe SAA6752HS allows download of new quantizer matrix contents.

7.3.3 VIDEO ENCODER STATUS INFORMATION

The following status information is available to the host:

• CURRENT ENCODER BIT RATE. The actual encoded bit rate, as number of bytes per GOP, is available allowing the use of constrained variable bit rate algorithms to fine tune the encoding efficiency.

7.3.4 GOP STRUCTURE

The programmable GOP structure features a reference frame distance (M) up to 3, and a GOP length (N) of up to 19.Supported structures arerealclosed GOP(M,N) and backward predicted closed GOP(M,N). For the use of B-frames in D1 and 2/3D1 mode a 64 Mbit SDRAM is needed.

In D1 mode, B-frames will be unidirectional. Backward predicted closed GOPs may have the first one (M = 2) or two (M = 3) B-frames referenced inside the GOP dependent on the I2C-bus register settings. This is intended for editable applications as GOPs are independent of each other. Non-editable GOPs allow the first one (M = 1) or two (M = 2) B-frames to be referenced to the P-frame in the previous GOP. This is a non-editable formatbut has optimum encodingefficiency.This structure is sometimes calledan openGOP. The first one (M = 1) or two (M = 2) B-frames in the first GOP of a sequence are always forced backwards predicted.

SAA6752HS

Table 3 GOP

GOP

LENGTH (N)

1I 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19

Notes

1. Undefined.

2. This GOP structure is defined as a Real Closed GOP (RCG).

3. This GOP structure is defined as a Backward Predicted Closed GOP (BPCG) or Non-Editable GOP (NEG), selectable via the I2C-bus.

REFERENCE FRAME DISTANCE (M)

01 2 3

(1) (1) (1)

(1)

IPP IBP

(1)

IPPP BIBP

(1)

IPPPP IBPBP

(1)

IPP...PP BIBPBP

(1)

IPP...PP IBP...BP

(1)

IPP...PP BIBP...BP

(1)

IPP...PP IBP...BP

(1)

IPP...PP BIBP...BP

(1)

IPP...PP IBP...BP

(1)

IPP...PP BIBP...BP

(1)

IPP...PP IBP...BP

(1)

IPP...PP BIBP...BP

(1)

IPP...PP IBP...BP

(1)

IPP...PP BIBP...BP

(1)

IPP...PP IBP...BP

(1)

IPP...PP BIBP...BP

(1)

IPP...PP IBP...BP

(1) (1)

(2) (1)

(3)

IBBP

(2) (1)

(3)

BBIBBP

(2)

IBBPBBP

(3) (1)

(2)

BBI...BBP

(3)

IBBP...BBP

(2) (1)

(3)

BBI...BBP

(2)

IBBP...BBP

(3) (1)

(2)

BBI...BBP

(3)

IBBP...BBP

(2) (1)

(3)

BBI...BBP

(2)

IBBP...BBP

(2)

(3)

(2)

(3)

(2)

(3)

(2)

(3)

(2)

2004 Jan 26 19

Philips Semiconductors Product speciﬁcation

MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer

7.3.5 BIT RATE CONTROL The SAA6752HS supports two modes of video bit rate

control: variable bit rate and constant bit rate. The Variable Bit Rate (VBR) mode is intended for burst

data transfer applications, where the bit rate is allowed to vary but the image quality should be constant. In this mode,acombination of three parameterscanbeset:Rvbr, Qmin_VBR and Qmax_VBR. While aimingat thetarget bit rate Rvbr, only quantizer scale values within the range between Qmin_VBR and Qmax_VBR are applied. Broadeningthis range leadsto greater variationsinpicture quality but better adherence to Rmax. Constriction of this range forces a better constancy in picture quality at the expense of meeting the target bit rate. Note that optimal control results require reasonable combinations of Rmax, Qmin_VBR and Qmax_VBR. Furthermore, the maximum bit rateRmax can beset.If Rmax isreachedin VBR mode, the CBR algorithmtakes over the control byincreasing the quantizer scale values temporarily (over Qmax_VBR) to guarantee that Rmax is never exceeded. Hence, the closer Rmax and Rvbr are chosen, the more the control in VBR mode turns to CBR mode behaviour.

SAA6752HS

7.3.7 QUANTIZER MATRIX TABLE DOWNLOAD

The MPEG standard default quantizer matrices can be overwritten to allow picture encoding optimization.

7.3.8 USER DATA INSERTION

User data insertion of up to 64 bytes is supported on GOP and picture level.

Different modes can be selected via I2C-bus.

7.3.8.1 External user data insertion (permanently

repeated)

User data is downloaded via the I2C-bus to subaddresses 73H/76H and the number of inserted user data bytes is set via subaddresses 74H/75H. In Encode mode the downloaded user data will be inserted permanently into the user data area of the video stream.

It is possible to download a new set of user data during Encodemode. The newdata will berepeatedly inserted as soon as the download is finished. It is possible to stop the user data insertion with a special command.

The Constant Bit Rate (CBR) mode is intended for applications, where a fixed channel rate is provided (e.g. transmission systems). A tight control of the quantizer scale is applied to make optimal use of the given bandwidth. The parameter Rmax specifies the required constant bit rate.

Independent of thebit rate mode(CBR or VBR),a B-frame weighting factor (the weighting factor is applied to the quantization scale) can be applied to further reduce the bit rate of B-frames. In IP-only GOP structures, every second P-frame is weighted by this factor generating ‘virtual B-frames’ to simulate a bit rate distribution similar to IPB sequences. This feature can further improve the perceptual rate-distortion ratio by taking advantage of the inertia of the human visual system.

7.3.6 ADAPTIVE QUANTIZATION Adaptive quantization is an algorithm that uses internal

generated statistics to fine tune the quantizer scale used for encoding a specific macroblock. For example, the controller adapts the quantization scalewith respectto the local complexity distribution within a frame, resulting in a perceptually smoother picture quality. The amount of fine tuning can be adjusted by control of the adaptive quantization depth.

7.3.8.2 External user data insertion (each downloaded

byte inserted only once)

In this mode each downloaded user data byte is inserted only once into the user data area. If no new user data is downloaded between two GOP or pictures then no user data will be inserted. This mode can be used to transmit more than 64 bytes of user data from the encoder to the decoder, e.g. 1000 bytes distributed on 15 packets of 64 bytes and one packet of 40 bytes. The host has to control the insertion and repetition of user data. A host interrupt 'mode transition completed' is signalled, if not masked and the bit 9 of the exception status word is set when the user data have been read by the video encoder. Then new user data can be downloaded via I2C-bus.

2004 Jan 26 20

Philips Semiconductors Product speciﬁcation

MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer

7.3.8.3 Internal Closed Caption user data insertion compliant to ATSC/NTSC standard

Automatic insertion of Closed Caption data into the user data 2 area on picture header level compliant to the ATSC and EIA-708 standard can be selected via the I2C-bus.

Closed Caption data, which is delivered from the video input processor (e.g. SAA7114) and captured in the video front-end will be inserted into the user data 2 area (picture header level) of the video stream. Preconditions are appropriate settings of the video input processor and the VBI data extractor in the video front-end. The Closed Caption user data will be written for both fields. If no valid Closed Caption data for field 2 is available these data will be marked as invalid in the stream. At SIF mode only field 1 Closed Captions can be inserted from the video input signal and dummy values (80H 80H) will be inserted for field 2.

If extended data services (XDS data, line 21 field 2) are inserted, the insertion will be transparent. No modification of the CGMS-A copy information will be done.

In accordance to EIA-708 the Closed Caption data will appear in the stream in transport order. If B-frames are present the user data isre-ordered inthe sameway as the video frames.

AdvancedTV Closed Captioning(ATVCC)channel packet data (cc_type 10 or 11) is not supported, because the inputsignal of theencoderis an analogvideo signal, which cancarry only NTSC ClosedCaptions,but not ATV Closed Captions.

No additional user data on picture header level can be inserted if internal Closed Caption user data insertion compliant to the ATSC/NTSC standard is active.

SAA6752HS

Closed Caption data, which is delivered from the video input processor (e.g. SAA7114) and captured in the video front-end will be inserted into the user data 1 area (GOP header level) of the video stream. Preconditions are appropriate settings of the video input processor and the VBI data extractor in the video front-end. The Closed Caption user data will be written for both fields. If no valid Closed Caption data for field 2 is available these data will be marked as invalid in the stream.

If extended data services (XDS data, line 21 field 2) are inserted, the insertion will be transparent. No modification of the CGMS-A copy information will be done.

The Closed Caption data will be inserted for each field of the GOP in display order. At SIF mode only field 1 Closed Captions can be inserted from the video input signal and dummy values (80H 80H) will be inserted for field 2.

The user data is delayed by one GOP period. The first GOP in the stream carries dummy data marked as invalid.

No additional user data on GOP header level can be inserted if internal Closed Caption user data insertion compliant to the DVD standard is active.

The amount of user data depends on the GOP size: 5 bytes header and 3 bytes/field are required. With the maximum GOP size of 19 this results in 5+19× 2 × 3 = 119 bytes, which is more than the available array of 64 bytes for GOP user data. Therefore the64 byte array forpictureuser data isalsoused for GOP userdata, ifGOP sizes largerthan 9 are selected. Thenall 128 bytes, which are available for user data insertion on GOP and picture header levelwill beused forthe insertion of CC data on GOP level. In this case no additional user data insertion on picture header level is possible.

7.3.8.4 Internal Closed Caption user data insertion compliant to DVD standard

Automatic insertion of Closed Caption data into the user data area on GOP header level compliant to the DVD standard can be selected via I2C-bus.

2004 Jan 26 21

7.3.9 MOTION ADAPTIVE NOISE REDUCTION The gain and adaptivity can be controlled to optimize

encoding efficiency in case of noisy input sequences, i.e. off-air reception.

Philips Semiconductors Product speciﬁcation

MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer

7.3.10 COMPRESSION BLOCK PARTITIONING

Thevideo compression block,shown in Fig.4,containsthe following sub-modules:

• MacroBlock Processor (MBP). Reads uncompressed

videodata from SDRAMandgenerates the compressed bitstream on MB level (withoutMB headers).Addresses for frame buffer (previous frame) access are generated by the MBP.

• Core control. Performs MB and slice header

generation, base address generation for the current MB (uncompressed), motion vector candidate generation, and computation of encoding statistics required by the CPU for bit rate controlling.

handbook, full pagewidth

to/from SDRAM-IF to SDRAM-IF

SAA6752HS

• Pre-packer (part ofpacking unit). Since the MBPoutput words are not necessarily fully used (i.e. some output words may contain unused bits) the pre-packer packs the output of the MBP in such a way that all words contain valid bits. This reduces the amount of memory required for storing the MB data.

• Packer (part of packing unit). Merges header and MB headers.

from video

front-end

VIDEO COMPRESSION BLOCK

PACKING UNIT

MBP/CPM

PRE-

PACKER

CORE CONTROL

GENERIC INTERFACE

to/from PCI-bus

MEMORY

Fig.4 Video compressor block diagram.

PACKER

MHC131

2004 Jan 26 22

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