Philips saa4955tj DATASHEETS

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DATA SH EET

SAA4955TJ

2.9-Mbit field memory

Product speciﬁcation Supersedes data of 1997 Sep 25 File under Integrated Circuits, IC02

1999 Apr 29

Philips Semiconductors Product speciﬁcation

2.9-Mbit ﬁeld memory SAA4955TJ

FEATURES

• 2949264-bit field memory

• 245772 × 12-bit organization

• 3.3 V power supply

• Inputs fully TTL compatible when using an extra 5 V

power supply

• High speed read and write operations

• FIFO operations:

– full word continuous read and write – independent read and write pointers (asynchronous

read and write access)

– resettable read and write pointers

• Optional random access by block function (40 words per block) enabled during pointer reset operation

• Quasi static (internal self-refresh and clocking pauses of infinite length)

• Write mask function

• Cascade operation possible

• 16 Mbit CMOS DRAM process technology

• 40-pin SOJ Package.

GENERAL DESCRIPTION

PALplus, PIP and 3D comb filter. The maximum storage depth is 245772 words × 12 bits. A FIFO operation with full word continuous read and write could be used as a data delay, for example. A FIFO operation with asynchronous read and write could be used as a data rate multiplier. Here the data is written once, then read as many times as required without being overwritten by new data. In addition to the FIFO operations, a random block access mode is accessible during the pointer reset operation. When this mode is enabled, reading and/or writing may begin at, or proceed from, the start address of any of the 6144 blocks. Each block is 40 words in length. Two or more SAA4955TJs can be cascaded to provide greater storage depth or a longer delay, without the need for additional circuitry.

The SAA4955TJ contains separate 12-bit wide serial ports for reading and writing. The ports are controlled and clocked separately, so asynchronous read and write operations are supported. Independent read and write clock rates are possible. Addressing is controlled by read and write address pointers. Before a controlled write operation can begin, the write pointer must be set to zero or to the beginning of a valid address block. Likewise, the read pointer must be set to zero or to the beginning of a valid address block before a controlled read operation can begin.

The SAA4955TJ is a 2949264-bit field memory designed for advanced TV applications such as 100/120 Hz TV,

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

cy(SWCK)

cy(SRCK)

ACC

, V

DD(P)

DD(tot)

WRITE cycle time (SWCK) see Fig.3 26 − − ns READ cycle time (SRCK) see Fig.10 26 − − ns READ access time after SRCK see Fig.10 − − 21 ns supply voltage (pins 19 and 22) 3.0 3.3 3.6 V

DD(O)

supply voltage (pins 20 and 21) 3.0 3.3 5.5 V total supply current

DD(tot)=IDD+IDD(O)+IDD(P)

)

minimum read/write cycle; outputs open

− 22 70 mA

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

SAA4955TJ SOJ40 plastic small outline package; 40 leads (J-bent); body width 10.16 mm SOT449-1

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Philips Semiconductors Product speciﬁcation

2.9-Mbit ﬁeld memory SAA4955TJ

BLOCK DIAGRAM

handbook, full pagewidth

IE internal

+3.3 V

V V

100 nF

DD(P) DD(P)

DD(O)

D0 internal

19 20 21 22

D0 to D11

14 to 3 18 17 16 15

DATA INPUT AND

WRITE MASK

BUFFER (×13)

12 + 1

WRITE MINI CACHE

12-WORD (×12)

READ MINI CACHE

12-WORD (×12)

IE WE RSTW SWCK

mini cache write control + cache transfer

cache transfer

INPUT BUFFER

SERIAL WRITE REGISTER

PARALLEL WRITE REGISTER

(×3)

20-WORD (×13)

20 × (12 + 1)

20-WORD (×13)

20 × (12 + 1)

MEMORY ARRAY

245760-WORD (×12)

IE internal

SERIAL WRITE CONTROLLER

write

control

write acknowledge

MEMORY

ARBITRATION

LOGIC

REFRESH ADDRESS

load write block address

CLOCK

OSCILLATOR

refresh clock

internal

WRITE ADDRESS

COUNTER

READ ADDRESS

COUNTER

GND

Pins 20 and21 (V

5.5 V instead of 3.3V. Pins 19 and 22 (V

GND

) should be connected to the supply voltage of the driving circuit that generates the input voltages. This could be, for instance,

DD(P)

SAA4955TJ

DATA MUX

DATA OUTPUT

BUFFER (×12)

27 to 38 23

and V

PARALLEL READ REGISTER

SERIAL READ REGISTER

mini cache read control

OE internal

DD(O)

INPUT BUFFER

OEQ0 to Q11

) require a 3.3 V supply.

Fig.1 Block diagram.

20 × 12

20-WORD (×12)

20 × 12

20-WORD (×12)

(×4)

24 25 26

SRCK

RSTR

read

control

SERIAL READ CONTROLLER

read acknowledge

internal

load read block address

MGK676

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Philips Semiconductors Product speciﬁcation

2.9-Mbit ﬁeld memory SAA4955TJ

PINNING

SYMBOL PIN I/O DESCRIPTION

GND

GND 2 ground general purpose ground D11 3 digital input data input 11 D10 4 digital input data input 10 D9 5 digital input data input 9 D8 6 digital input data input 8 D7 7 digital input data input 7 D6 8 digital input data input 6 D5 9 digital input data input 5 D4 10 digital input data input 4 D3 11 digital input data input 3 D2 12 digital input data input 2 D1 13 digital input data input 1 D0 14 digital input data input 0 SWCK 15 digital input serial write clock RSTW 16 digital input write reset clock WE 17 digital input write enable IE 18 digital input input enable V

DD(P)

DD(O)

OE 23 digital input output enable RE 24 digital input read enable RSTR 25 digital input reset read SRCK 26 digital input serial read clock Q0 27 digital output data output 0 Q1 28 digital output data output 1 Q2 29 digital output data output 2 Q3 30 digital output data output 3 Q4 31 digital output data output 4 Q5 32 digital output data output 5 Q6 33 digital output data output 6 Q7 34 digital output data output 7 Q8 35 digital output data output 8 Q9 36 digital output data output 9 Q10 37 digital output data output 10 Q11 38 digital output data output 11 GND

GND

1 ground ground for protection circuits

19 supply +3.3 V general purpose supply voltage (see ﬁgure note in Fig.1) 20 supply +3.3 to 5.5 V supply voltage for protection circuits (see ﬁgure note in Fig.1) 21 supply +3.3 to 5.5 V supply voltage for protection circuits 22 supply +3.3 V supply voltage for output circuits

39 ground ground for output circuits 40 ground ground for protection circuits

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Philips Semiconductors Product speciﬁcation

2.9-Mbit ﬁeld memory SAA4955TJ

handbook, halfpage

GND

SWCK RSTW

DD(P)

D11 D10

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

10 11 12 13 14 15 16 17 18

19 20

1 2 3 4 5 6 7 8 9

SAA4955TJ

MGK675

GND

Q11

Q10

27 26

SRCK

RSTR

OE V

DD(O)

DD(P)

Fig.2 Pin configuration.

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Philips Semiconductors Product speciﬁcation

2.9-Mbit ﬁeld memory SAA4955TJ

FUNCTIONAL DESCRIPTION Write operation

Write operations are controlled by the SWCK, RSTW, WE and IE signals. A write operation starts with a reset write address pointer (RSTW) operation, followed by a sequence SWCK clock cycles during which time WE and IE must be held HIGH. Write operations between two successive reset write operations must contain at least 40 SWCK write clock cycles while WE is HIGH. To transfer data temporarily stored in the serial write registers to the memory array, a reset write operation is required after the last write operation.

RESET WRITE: RSTW The first positive transition of SWCK after RSTW goes

from LOW to HIGH resets the write address pointer to the lowest address (−12 decimal), regardless of the state of WE (see Figs 3 and 4). RSTW set-up (t (t

) times are referenced to the rising edge of SWCK

h(RSTW)

su(RSTW)

) and hold

(see Fig.3). The reset write operation may also be asynchronously related to the SWCK signal if WE is LOW.

RSTW needs to stay LOW for a single SWCK cycle before another reset write operation can take place. If RSTW is HIGH for 1024 SWCK write clock cycles while WE is HIGH, the SAA4955TJ will enter a built-in test mode and will not be in regular operation.

ANDOM WRITE BLOCK ACCESS MODE

at the 17th positive transition of SWCK. A write latency period of 18 additional SWCK clock cycles is required before write access to the new block address is possible. During this time, data is transferred from the serial write and parallel write registers into the memory array and the write pointer is set to the new block address.

Block address values between 0 and 6143 are valid. Values outside this range must be avoided because invalid block addresses can result in abnormal operation or a lock-up condition. Recovery from lock-up requires a standard reset write operation.

WE must remain LOW from the 3rd positive transition of SWCK to the 17th write latency SWCK clock cycle if the block address is applied to pin D0. If the block address is applied to pin IE, WE must be HIGH on the 5th positive transition of SWCK, may be HIGH or LOW on the 6th transition, and must be LOW from the 7th transition to the 17th write latency SWCK clock cycle.

At the 18th write latency SWCK clock cycle, IE and WE may be switched HIGH to prepare for writing new data at the next positive transition of SWCK. The complete write block access entry sequence is finished after the 18th write latency cycle.

The LOW-to-HIGH transition on RSTW required at the beginning of the sequence should not be repeated. Additional LOW-to-HIGH transitions on RSTW would disable write block address mode and reset the write pointer.

The SAA4955TJ will enter random write block access mode if the following signal sequence is applied to control inputs IE and WE during the first four SWCK write clock cycles after a reset write (see Figs 5 and 6):

At the 1st and 2nd positive transitions of SWCK, IE must be LOW and WE must be HIGH

At the 3rd and 4th positive transitions of SWCK, IE must be HIGH and WE must be LOW

At the 5th positive transition of SWCK, the state of WE determines which input pin is used for the block address. If WE is LOW the Most Significant Bit (MSB) of the block address must be applied to the D0 input pin. If WE is HIGH, the Most Significant Bit (MSB) of the block address is applied to pin IE.

During the first four clock cycles, control signals WE and IE will function as defined for normal operation. The remaining 12 bits of the 13-bit write block address must be applied, in turn, to the selected input pin (D0 or IE) at the following 12 positive transitions of SWCK. The Least Significant Bit (LSB) of the write block address is applied

1999 Apr 29 6

DDRESS ORGANIZATION

Two different types of memory are used in the data address area: a mini cache for the first 12 data words after a reset write or a reset read, and a DRAM cell memory array with a 245760 word capacity. Each word is 12 bits long. The mini cache is needed to store data immediately after a reset operation since a latency period is required before read or write access to the memory array is possible. Latency periods are needed for read or write operations in random read or write block access modes because data is read from, or written to, the memory array. The data in the mini cache can only be accessed directly after a standard reset operation. It cannot be accessed in random read or write block access modes.

The address area reserved for the mini cache, accessible after a standard reset operation, is from decimal−12 to −1. The memory array starts at decimal 0 and ends at 245759. Decimal address 0 is identical to block address 0000H. Because a single block address is defined for every 40 words in the memory array, block address 0001H

Philips Semiconductors Product speciﬁcation

2.9-Mbit ﬁeld memory SAA4955TJ

corresponds to decimal address 40. The highest block address is 17FFH. This block has a decimal start address of 245720 and an end address 245759.

If a read or write reset operation is not performed, the next read or write pointer address after 245759 will be address 0 due to pointer wraparound. Note that reset read and reset write operations should occur in a single sequence. If one pointer wraps around while the other is reset, either 12 words will be lost or 12 words of undefined data will be read.

ATA INPUTS:D0TO D11 AND WRITE CLOCK: SWCK

D A positive transition on the SWCK write clock latches the

data on inputs D0 to D11, provided WE was HIGH at the previous positive transition of SWCK. The data input set-up (t

) and hold (t

su(D)

) times are referenced to the

h(D)

positive transition of SWCK (see Fig.4). The latched data will only be written into memory if IE was HIGH at the previous positive transition of SWCK.

RITE ENABLE:WE

Pin WE is used to enable or disable a data write operation. The WE signal controls data inputs D0 to D11. In addition, the internal write address pointer is incremented if WE is HIGH at the positive transition of the SWCK write clock. WE set-up (t

su(WE)

) and hold (t

) times are referenced

h(WE)

to the positive edge of SWCK (see Fig.7).

NPUT ENABLE:IE

Pin IE is used to enable or disable a data write operation from the D0 to D11 data inputs into memory. The latched data will only be written into memory if the IE and WE signals were HIGH during the previous positive transition of SWCK. A LOW level on IE will prevent the data being written into memory and existing data will not be overwritten (write mask function; see Fig.9). The IE set-up (t

) and hold (t

su(IE)

) times are referenced to the positive

h(IE)

edge of SWCK (see Fig.8).

Read operation

Read operations are controlled by the SRCK, RSTR, RE and OE signals. A read operation starts with a reset read address pointer (RSTR) operation, followed by a sequence of SRCK clock cycles during which time RE and OE must be held HIGH. Read operations between two successive reset read operations must contain at least 20 SRCK read clock cycles while RE is HIGH.

ESET READ: RSTR

The first positive transition of SRCK after RSTR goes from LOW to HIGH resets the read address pointer to the lowest address (−12 decimal; see Figs 10 and 11). If RE is LOW, however, the reset read operation to the lowest address will be delayed until the first positive transition of SRCK after RE goes HIGH. RSTR set-up (t (t

) times are referenced to the rising edge of SRCK

h(RSTR)

su(RSTR)

) and hold

(see Fig.10). The reset read operation may also be asynchronously related to the SRCK signal if RE is LOW.

RSTR needs to stay LOW for a single SRCK cycle before another reset read operation can take place.

ANDOM READ BLOCK ACCESS MODE

R The SAA4955TJ will enter random read block access

mode if the following signal sequence is applied to control inputs RE and OE during the first four SRCK read clock cycles after a reset read (see Fig.12):

At the 1st and 2nd positive transitions of SRCK, OE must be LOW and RE must be HIGH

At the 3rd and 4th positive transitions of SRCK, OE must be HIGH and RE must be LOW.

During this time, control signals RE and OE will function as defined for normal operation. The Most Significant Bit (MSB) of the block read address is applied to the OE input pin at the 5th positive transition of SRCK. The remaining 12 bits of the 13-bit read block address must be applied, in turn, to OE at the following 12 positive transitions of SRCK. The Least Significant Bit (LSB) of the block address is applied at the 17th positive transition of SRCK. A read latency period of 20 additional SRCK clock cycles is required before read access to the new block address is possible. During this period, data is transferred from the memory array to the serial read and parallel read registers and the read pointer is set to the new block address.

The data output pins are not controlled by the OE pin and are forced into high impedance mode from the 3rd to the 17th positive transition of SRCK. OE should be held LOW during the read latency period. RE must remain LOW from the 3rd positive transition of SRCK to the 20th read latency SRCK clock cycle.

1999 Apr 29 7

After the 20th read latency SRCK clock cycle, RE and OE may be switched HIGH to prepare for reading new data

Philips Semiconductors Product speciﬁcation

2.9-Mbit ﬁeld memory SAA4955TJ

from the new address block at the next positive transition of SRCK. The complete read block access entry sequence is finished after the 20th read latency cycle.

The LOW-to-HIGH transition on RSTR required at the beginning of the sequence should not be repeated. Additional LOW-to-HIGH transitions on RSTR would disable read block address mode and reset the read pointer.

ATA OUTPUTS:Q0TO Q11 AND READ CLOCK: SRCK

D The new data is shifted out of the data output registers on

the rising edge of the SRCK read clock provided RE and OE are HIGH. Data output pins are low impedance if OE is HIGH. If OE is LOW, the data outputs are high impedance and the data output bus may be used by other devices. Data output hold (t

) and access (t

h(Q)

) times are

ACC

referenced to the positive transition of SRCK. The output data becomes valid after access time interval t

ACC

(see

Fig.11). Data output pins Q0 to Q11 are TTL compatible with the

restriction that when the outputs are high impedance, they must not be forced higher than V

+ 0.5 V or 5.0 V

DD(O)

absolute. The output data has the same polarity as the incoming data at inputs D0 to D11.

EAD ENABLE:RE

R RE is used to increment the read pointer. Therefore, RE

needs to be HIGH at the positive transition of SRCK. When RE is LOW, the read pointer is not incremented. RE set-up (t

) and hold (t

su(RE)

) times are referenced to the

h(RE)

positive edge of SRCK (see Fig.13).

UTPUT ENABLE:OE

O OE is used to enable or disable data outputs Q0 to Q11.

The data outputs are enabled (low impedance) if OE is HIGH. OE LOW disables the data output pins (high impedance). Incrementing of the read pointer does not depend on the status of OE. OE set-up (t (t

) times are referenced to the positive edge of SRCK

h(OE)

su(OE)

) and hold

(see Fig.14).

Power-up and initialization

Reliable operation is not guaranteed until at least 100 µs after power-up, the time needed to stabilize V

within the

recommended operating range. After the 100 µs power-up interval has elapsed, the following initialization sequence must be performed: a minimum of 12 dummy read operations (SRCK cycles) followed by a reset read operation (RSTR), and a minimum of 12 dummy write

operations (SWCK) followed by a reset write operation (RSTW). Read and write initialization may be performed simultaneously.

If initialization starts earlier than the recommended 100 µs after power-up, the initialization sequence described above must be repeated, starting with an additional reset read operation and an additional reset write operation after the 100 µs start-up time.

Old and new data access

A minimum delay of 40 SWCK clock cycles is needed before newly written data can be read back from memory (see Fig.15). If a reset read operation (RSTR) occurs in a read cycle before a reset write operation (RSTW) in a write cycle accessing the same memory location, then old data will be read.

Old data will be read provided a data read cycle begins within 20 pointer positions of the start of a write cycle. This means that if a reset read operation begins within 20 SWCK clock cycles after a reset write operation, the internal buffering of the SAA4955TJ will ensure that old data will be read out (see Fig.16).

New data will be read if the read pointer is delayed by 40 pointer positions or more after the write pointer. Old data is still read out if the write pointer is less than or equal to 20 pointer positions ahead of the read pointer (internal buffering). A write pointer to read pointer delay of more than 20 but less than 40 pointer positions should be avoided. In this case, the old or the new data may be read, or a combination of both.

In random read and write block access modes, the minimum write-to-read new data delay of 40 SWCK clock cycles must be inserted for each block.

Memory arbitration logic and self-refresh

Since the data in the memory array is stored in DRAM cells, it needs to be refreshed periodically. Refresh is performed automatically under the control of internal memory arbitration logic which is clocked by a free running clock oscillator. The memory arbitration logic controls memory access for read, write and refresh operations. It uses the contents of the write, read and refresh address counters to access the memory array to load data from the parallel write register, store data in the parallel read register, or to refresh stored data. The values in these counters correspond to block addresses.

1999 Apr 29 8

Philips Semiconductors Product speciﬁcation

2.9-Mbit ﬁeld memory SAA4955TJ

Cascade operation

If a longer delay is needed, the total storage depth can be increased beyond 2949264 bits by cascading several SAA4955TJs. For details see the interconnection and

continuously for 1024 SWCK clock cycles, the SAA4955TJ will enter test mode. It will exit test mode if WE is LOW for a single SWCK cycle or if RSTW is LOW for 2 SWCK clock cycles.

timing diagrams (Figs 17 and 18).

Test mode operation

The SAA4955TJ incorporates a test mode not intended for customer use. If WE and RSTW are held HIGH

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

, V

DD(P)

DD(tot)

∆V voltage difference between GND,

tot

stg

amb

supply voltages −0.5 +5 V

DD(O)

supply voltage for protection circuits −0.5 +5.5 V input voltage V

output voltage V

=5V −0.5 +5.5 V

DD(P)

DD=VDD(O)=VDD(P)

=5V −0.5 +5 V

DD(P)

DD=VDD(O)=VDD(P)

= 3.3 V −0.5 +3.8 V

total supply current − 200 mA

−0.5 +0.5 V

GND

and GND

short circuit output current − 50 mA total power dissipation − 750 mW storage temperature −20 +150 °C junction temperature 0 125 °C ambient temperature 0 70 °C electrostatic handling note 1 −150 +200 V

note 2 −2000 +2000 V

Notes

1. Machine model: equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor (‘0 Ω’ is actually

0.75 µH+10Ω).

2. Human body model: equivalent to discharging a 100 pF capacitor through a 1500 Ω series resistor.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

th(j-a)

thermal resistance from junction to ambient in free air 60 K/W

1999 Apr 29 9

+ 19 hidden pages