Philips SAA4700 Datasheet

INTEGRATED CIRCUITS

DATA SH EET

SAA4700

VPS dataline processor

Preliminary speciﬁcation File under Integrated Circuits, IC02

March 1991

Philips Semiconductors Preliminary speciﬁcation

VPS dataline processor SAA4700

FEATURES

• Adaptive sync slicer with buffered composite sync output VCS

• Adaptive data slicer

• Data rate clock regenerator

• Field selection and line 16

decoding

• Startcode and biphase check

• Data valid output

• Storage of data line information in a

40 bit register bank

• I2C-bus transmission

GENERAL DESCRIPTION

The SAA4700 is a bipolar integrated circuit designed for use in dataline receivers and incorporates a dataline slicer and decoder. The slicer extracts the dataline signal from the video signal and regenerates the data clock. It also provides signals for the decoder in order to decode the binary data that is transmitted in line 16 of every first field of the composite video signal (video programming signal and video recording programming by Teletext, VPS and VPT systems). The decoded information out of words 5 and 11 to 14 is accessed via the built-in I

C-bus interface. This information then can be used for programming a video cassette recorder in order to start and stop a recording of a television program at the correct aligned time, regardless of a delay or extension in the transmission time of the required program.

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

supply voltage (pins 15 and

4.5 5 5.5 V

16)

i CVBS

total supply current − 18 23 mA CVBS input signal

sync-to-white (peak-to-peak value) 0.5 1 1.4 V

amb

operating ambient

0 −+70 °C

temperature

ORDERING AND PACKAGE INFORMATION

EXTENDED TYPE

NUMBER

PINS PIN POSITION MATERIAL CODE

PACKAGE

SAA4700 18 DIL plastic SOT102

Note

1. SOT102-1; 1996 December 4.

(1)

March 1991 2

Philips Semiconductors Preliminary speciﬁcation

VPS dataline processor SAA4700

handbook, full pagewidth

4.7 nF

CVBS

470 pF

1 nF

4.7 kΩ

75 kΩ

(2%)

to V

4.7 nF

22 nF

SYNC

SEPARATOR

SAA4700

DATA

SLICER

REGENERATOR

PLL WITH

5 MHz VCO AND

PHASE DETECTOR

CSO

0.1 µF

5 6 11 12 7

FIELD SELECTOR

LINE 16 DECODER

line 16

data

CLOCK

VCS

14 3 4 15 16 10

(test line 16)

INPUT

CONTROLLER

TIME BASE

DAV

OUTPUT

CONTROLLER

data

REFERENCE

POWER-ON RESET

I2C-BUS

CONTROL

40-BIT DATA

40-BIT

DATA LATCH

MULTIPLEXER

VOLTAGES

AD = LOW

external

reset

SCL

SDA

n.c.

8.2 kΩ

FUNCTIONAL DESCRIPTION Dataline 16

The information in dataline 16 consists of fifteen 8-bit words; the total information content is shown in Table 1; and the organization of transmitted bytes is shown in Table 2.

Out of the fifteen possible 8-bit words the SAA4700 extracts words 5 and 11 to 14. The contents of these words can be read via the built-in I

C-bus interface. The circuit is fully transparent, thus each bit is transferred without modification with only the sequence of words being changed. Words 11 to 14

clock pulse

Fig.1 Block diagram and test circuit.

are transmitted first followed by word 5.

By evaluating the sliced sync signal the circuit can identify the beginning of dataline 16 in the first field. The dataline decoder stage releases the start code detector. When a correct start code is detected (for timing of start code detection see Fig.3) words 5 and 11 to 14 are decoded, checked for biphase errors and stored in a register bank. If no biphase error has occurred, the contents of the register bank are transferred to a second register bank by the data valid control signal. If the system has been addressed, this transfer will be

0.1 µF

+5 V

MEH095

delayed until the next start or stop condition of the I2C-bus has been received.

The last bit of correct information on the dataline remains available until it is read via the I2C-bus. Once the stored information has been read it is considered to be no longer valid and the internal new data flag is reset. Subsequently, if the circuit is addressed, the only VPS data that will be sent back is ”FFF to F”. The same conditions apply after power-up when no data can be read out. New data is available after reception of another error-free dataline 16.

March 1991 3

Philips Semiconductors Preliminary speciﬁcation

VPS dataline processor SAA4700

PINNING

SYMBOL PIN DESCRIPTION

CVBS 1 video signal input (CVBS from TV) SYNC 2 sync amplitude input (CVBS from TV) GND1 3 analog ground (0 V) GND2 4 digital ground (0 V) C

black

5 capacitor for black level CSO 6 composite sync output AD 7 address set input

SCL 8 I SDA 9 I

C-bus clock line

C-bus data line RS 10 reset input active LOW TP 11 test point for line 16 decoder DAV 12 data available output active LOW

oscillator resistor for frequency

osc

adjustment CP 14 test point clock pulse V

15 +5 V supply voltage (digital part) 16 +5 V supply voltage (analog part) 17 capacitor of phase detector

n.c. 18 not connected

PIN CONFIGURATION

handbook, halfpage

CVBS SYNC GND1 GND2

black

CSO

SCL

SDA

1 2 3 4 5 6 7 8 9

Fig.2 Pin configuration

SAA4700

MBH796

n.c. C

osc

DAV

External reset

The circuit provides an internal power-on reset. When using this facility pin 10 should be connected to VP or, if external reset (RESET = LOW) is to be used pin 10 should be prepared by connecting pin 10 via a 10 kΩ pull-up resistor to VP.

Reset forces the following:

-I2C-bus not to acknowledge

- DAV output to go HIGH (pin 12)

-I2C-bus transfer register to “FFF”

CVBS input

The CVBS signal is applied to the sync separator (pin 2) via a decoupling capacitor and to the data slicer (pin 1) via an RC high-pass filter.

To enable proper storage of the sync value in the decoupling capacitor, the sync generator output resistance should not exceed 1 kΩ.

Black level

The capacitor connected to pin 5 stores the black level value for the adaptive sync slicer.

Composite sync output (CSO)

A composite sync output signal for customer application is provided (pin 6).

DAV output

The data available output pin 12 is set LOW after an error free dataline 16 is received. DAV returnes to HIGH after the beginning of the next first field. If

no valid data is available

DAV remains HIGH. A short duration pulse of 1 µs (Fig.5) is inserted at the beginning of dataline 16; it will ensure that a HIGH-to-LOW transmission occurs which can then be used for triggering.

5 MHz VCO and phase detector

The resistor connected between pin 13 and V

determines the current

into the voltage controlled oscillator. The RC network connected to pin 17 acts as a low-pass filter for the phase detector.

Power supply

To prevent crosscoupling the circuit is provided with separate ground and supply pins for analog and digital parts (pins 3, 4, 15 and 16).

March 1991 4

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