Philips SAA3500H Technical data

INTEGRATED CIRCUITS

DATA SH EET

SAA3500H

Digital audio broadcast channel decoder

Preliminary speciﬁcation File under Integrated Circuits, IC01

2000 Jun 14

Philips Semiconductors Preliminary speciﬁcation

Digital audio broadcast channel decoder SAA3500H

1 FEATURES 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 QUICK REFERENCE DATA 5 ORDERING INFORMATION 6 BLOCK DIAGRAM 7 PINNING 8 FUNCTIONAL DESCRIPTION 9 INTERFACE DESCRIPTION

9.1 Input interface

9.2 Memory interface

9.3 Parallel output interface

9.4 Serial output interface

9.5 Simple full capacity output

9.6 RDI output

9.7 Microcontroller interface

9.7.1 I2C-bus mode

9.7.2 L3-bus mode

9.7.3 Microcontroller interface registers 10 LIMITING VALUES

11 THERMAL CHARACTERISTICS 12 DC CHARACTERISTICS 13 AC CHARACTERISTICS 14 APPLICATION INFORMATION

14.1 Clock oscillator

14.2 Reset input

14.3 Boundary scan test interface 15 PACKAGE OUTLINE 16 SOLDERING

16.1 Introduction to soldering surface mount packages

16.2 Reflow soldering

16.3 Wave soldering

16.4 Manual soldering

16.5 Suitability of surface mount IC packages for wave and reflow soldering methods

17 DATA SHEET STATUS 18 DEFINITIONS 19 DISCLAIMERS 20 PURCHASE OF PHILIPS I2C COMPONENTS

2000 Jun 14 2

Philips Semiconductors Preliminary speciﬁcation

Digital audio broadcast channel decoder SAA3500H

1 FEATURES

• DigitalAudioBroadcast(DAB)full-capacitydemodulator and decoder

• Supports DAB transmission modes I, II, III and IV

• Integrated Analog-to-Digital Converter (ADC) for

IF input

• Digital mixer with on-chip digital Automatic Frequency Control (AFC) and Automatic Gain Control (AGC)

• Detectors for null symbol, DAB mode and transmitter identification

• On-chip or external synchronization algorithms and control loops

• On-chip timing PLL and DCXO

• Dynamic DAB multiplex reconfiguration supported

• Equal and unequal error protection for up to

64 sub-channels

• Fast information channel buffering

• Simple full capacity output

• Receiver data interface

• Serial output for three sub-channels

• I2C-bus or L3-bus control interface.

2 APPLICATIONS

• Mobile receivers (FM/DAB car radios)

• Personal Computer add-ons

• Test and measurement equipment

• Portable radios.

3 GENERAL DESCRIPTION

The Philips SAA3500H is a Digital Audio Broadcast (DAB) channel decoder according to the ETSI specification ETS 300 401.The SAA3500H is a successor tothePhilips FADIC and SIVIC chip set and provides an IF ADC, digital mixer, full DAB ensemble demodulation and decoding as well as time and frequency synchronization functions. Because of the full-speed Viterbi decoding capacity and a high-speed receiver data output interface, DAB data reception is not limited by the SAA3500H channel decoder.

4 QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V V I

clk

T T

DD i(max)

amb stg

supply voltage 3.0 3.3 3.6 V maximum input voltage −0.5 − VDD+ 0.5 V DC supply current −− 180 mA clock frequency − 24576 − kHz ambient temperature −40 +25 +85 °C storage temperature −65 − +150 °C

5 ORDERING INFORMATION

PACKAGE

TYPE NUMBER

NAME DESCRIPTION VERSION

SAA3500H QFP100 plastic quad flat package; 100 leads (lead length 1.95 mm);

body 14 × 20 × 2.7 mm; high stand-off height

SOT317-1

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Philips Semiconductors Preliminary speciﬁcation

Digital audio broadcast channel decoder SAA3500H

6 BLOCK DIAGRAM

ADE

ADC

OUT[7:0]

OCLK

OIQ

OCIR

OEN

AIF

99 1

39 to 32 27

29 30

AD CONVERTER

(8 BIT)

CHANNEL IMPULSE

RESPONSE

PROCESSOR

AUTOMATIC FREQUENCY

CONTROL PROCESSOR

SYMBOL SELECT

CAPACITY UNIT

BYP

AGC

INP[9:0] IQS

217

sync

SELECT

21 20 25 24 19 41 4 5 to 8

DIGITAL MIXER

AND FILTERS

FAST FOURIER

TRANSFORMATION

DIFFERENTIAL

DEMODULATOR

FREQUENCY & TIME

DE-INTERLEAVER

SLI

metrics

ADCLK

NULL DETECTOR,

OSCI

MCLK

TIMEBASE,

BOUNDARY SCAN TEST

OSCO

DCXO

SAA3500H

62 to 68, 81 to 91

23 22

97 95

96 93

71 to 78

69 61

FSO FSI

TMS TCK TDI TDO

TRST

A17 A[17:0]

D[7:0] RD

UNEQUAL/EQUAL

ERROR PROTECTION

CONTROL

MCI

MICROCONTROLLER

INTERFACE

CFIC

RESET RDE

52 54 53

CMODE

CCLK

CDATA SOD[1:3] REF

inhibit

FIC

VITERBI

DECODER

BUFFER

49 to

Fig.1 Block diagram.

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SERIAL OUTPUT

46 to 44

SFCOSOV[1:3]SOC

58 57

RDC

ERROR FLAG

DETECT/COUNT

RDO

Philips Semiconductors Preliminary speciﬁcation

Digital audio broadcast channel decoder SAA3500H

7 PINNING

SYMBOL PIN TYPE DESCRIPTION

ADC 1 input analog-to-digital converter DC input AIF 2 input analog-to-digital converter IF input V

SSA

ADE 99 input analog-to-digital converter enable (active LOW) V

DDA

INP[0:9] 8 to 17 input 2048 kHz IF or baseband digital parallel input data (8 or 10 bits) ADCLK 19 output analog-to-digital clock output 8192 kHz if IQS 20 input clock signal indicating I or Q baseband data if

BYP 21 input IF input stage bypass (active LOW) FSI 22 input frame sync input (LOW indicates DAB null symbol detection) FSO 23 output null detector/frame sync output (LOW indicates DAB null symbol position) SLI 24 output AGC synchronization lock indicator (HIGH if synchronized) AGC 25 output AGC level comparator output (HIGH if input sample > reference level, else LOW) OSCI 4 input oscillator or system clock input, 24576 kHz OSCO 5 output oscillator output MCLK 41 output master clock output, 24576 kHz V

TEST 92 input connect to ground for proper operation OUT[0:7] 32 to 39 output baseband or channel impulse response output OCLK 27 output output data clock (negative edge indicates new data) OIQ 29 output output I or Q select signal if OCIR 30 input output select: baseband if OCIR = HIGH, CIR if OCIR = LOW OEN 31 input output enable (active LOW) CFIC 51 output microcontroller interface signal indicating Fast Information Channel (FIC) processing CMODE 52 input microcontroller interface mode input (only L3-bus) CDATA 53 I/O microcontroller interface serial data I CCLK 54 input microcontroller interface clock input I RESET 55 input chip reset input (active LOW) A[17:11] 62 to 68 output address outputs external RAM A[10:0] 81 to 91 output address outputs external RAM WR 61 output write data to RAM (active LOW) RD 69 output read data from RAM (active LOW) A17 70 output address bit 17 inverted for second RAM (128k × 8) D[0:7] 71 to 78 I/O data input/output external RAM

3 ground analog supply ground

100 supply analog voltage supply (+3.3 V)

signal for swapping I and Q data bytes if BYP = HIGH

7, 18,

supply digital supply ground

26, 40,

60, 80

and 94

6, 28,

supply digital voltage supply (+3.3 V)

42 and

BYP = HIGH, 4096 kHz if BYP = LOW

BYP = LOW;

OCIR = HIGH, or frame trigger if OCIR = LOW

C-bus or L3-bus (5 V tolerant)

C-bus or L3-bus

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Philips Semiconductors Preliminary speciﬁcation

Digital audio broadcast channel decoder SAA3500H

SYMBOL PIN TYPE DESCRIPTION

SOV3 44 output serial output valid data 3 SOV2 45 output serial output valid data 2 SOV1 46 output serial output valid data 1 SOD3 47 output serial output data 3 SOD2 48 output serial output data 2 SOD1 49 output serial output data 1 (from channel decoder) SOC 50 output serial output clock (384 kHz continuous) REF 43 output receiver error ﬂag [from Viterbi decoder, for Simple Full Capacity Output (SFCO)] SFCO 56 output simple full capacity output (direct from Viterbi decoder) RDC 57 output receiver data clock (6144 kHz continuous) or SFCO clock (burst) RDE 58 input RDI output enable (active LOW) RDO 59 output receiver data interface bi-phase output TDO 93 output boundary scan test serial output TCK 95 input boundary scan test clock input TDI 96 input boundary scan test serial input TMS 97 input boundary scan test mode select input TRST 98 input boundary scan test reset input

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Philips Semiconductors Preliminary speciﬁcation

Digital audio broadcast channel decoder SAA3500H

DDA

TRST

TMS

TDI

TCK

VSSTDO

ADC

AIF

SSA

OSCI

OSCO

INP0 INP1 INP2 INP3 INP4 INP5 INP6 INP7 INP8 INP9

ADCLK

IQS

BYP

FSI

FSO

SLI

AGC

OCLK

OIQ

OCIR

ADE 99989796959493929190898887868584838281

100

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

TESTA0A1A2A3A4A5A6A7A8A9

SAA3500H

A10

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 5130

D0 D1 D2 D3 D4 D5 D6 D7 A17 RD A11 A12 A13 A14 A15 A16 A17 WR V

RDO RDE RDC SFCO RESET CCLK CDATA CMODE CFIC

31323334353637383940414243444546474849

OEN

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

Fig.2 Pin configuration.

2000 Jun 14 7

MXXxxx

MCLK

REF

SOV3

SOV2

SOV1

SOD3

SOD2

SOD1

SOC

Philips Semiconductors Preliminary speciﬁcation

Digital audio broadcast channel decoder SAA3500H

8 FUNCTIONAL DESCRIPTION

The 2.048 MHz IF signal is digitized by an 8-bit flash Analog-to-Digital Converter (ADC), which samples at

8.192 MHz. The required input level is limited to a peak-to-peak voltage of 2 V. Due to a fast sample-and-hold circuit sub-sampling is possible, so that all IF frequencies of N × 8.192 ±2.048 MHz can be used. If a higher resolution ADC is wanted, anexternal ADCcan be connected.

The digital mixer accepts a 2.048 MHzIF signal atits input and converts it to baseband with In-phase (I) and Quadrature-phase (Q) components. The mixer frequency is adjusted on a DAB frame basis with 1 Hz resolution to prevent performance degradation. The mixer output signals are digitally filtered and subjected to internal Automatic Gain Control (AGC) before entering the subsequent Fast Fourier Transform (FFT) stage.

The output of the digital AGC detectors indicates for each input sample whether the level is below or above the reference input level. By means of external filtering and gain control, the signal can be used to adjust the input signal level of the analog-to-digital converter (external AGC).

The on-chip null detector operates on the digital baseband signal and indicates the coarse position of the DAB null symbol (FSO = LOW), which is used for time base initialization. The spacing of detected null symbols is used to detect the DAB transmission mode.

The time base counts samples on a symbol and a frame basis in order to generate the internal control windows for the FFT and to generate a frame sync signal (FSO) during thenullsymbol.Initializationofthe time base is determined by the null detector signal (FSI) and the selected DAB mode. After time base initialization the SAA3500H will be in symbol processing mode and the null detector will be deactivated.

The OFDM symbol demodulator applies a real-time FFT and differential demodulation to the baseband signal. The output is quantized to 4-bit metrics for the Viterbi decoder. The position of the FFT window is adjusted on a DAB frame basis in order to avoid Inter-Symbol Interference (ISI).

TheFFTresultof the reference symbol is processed bythe synchronization core, which performs two functions: estimation of the frequency error of the baseband signal, which is needed to adjust the digital mixer (AFC), and calculation of the Channel Impulse Response (CIR) to be used for positioning of the FFT window and the system clock.All timing and frequency controlloopsare realized in the synchronization core and can be influenced from the control interface.

The Viterbi decoder is preceded by frequency and time de-interleavingof the incoming metricsinexternal RAM, to distribute burst errors caused by channel fading. Variable rate decoding is done with 3.072 Mb/s decision speed. Output bits are re-encoded and compared to corresponding input bits in order to generate an error flag signal.

Sub-channel selection is done on a Capacity Unit (CU) basis. All standardized Unequal Error Protection (UEP) puncturing schemes for audio and Equal Error Protection (EEP) schemes for data are provided. Up to 64 sub-channelscanbeselectedseparately,whichmeans virtually unlimited DAB decoding capabilities.

The output interface provides a full-speed standardized Receiver Data Interface (RDI) for all sub-channel data. This allows to extend every DAB receiver with external decoders for all kind of services. A dedicated interface is provided for the Philips SAA2502H audio source decoder, which completes the DAB receiver.

The system clock of 24.576 MHz, can be generated by an integrated DCXO, which is internally locked to the DAB signal. The clockis available on the MCLKpin to provide a synchronous clock to the MPEG decoder and microcontroller.

The I2C-bus or L3-bus configurable control interface provides access to Automatic Frequency Control (AFC), Channel Impulse Response (CIR), Fast Information Channel (FIC) and sub-channel selection controls.

2000 Jun 14 8

Philips Semiconductors Preliminary speciﬁcation

Digital audio broadcast channel decoder SAA3500H

9 INTERFACE DESCRIPTION

9.1 Input interface

The input interface can be used in 3 different modes, depending on the bypass (BYP) and IQ Select (IQS) pins. Digital input data should be in two’s complement format (optionally: offset binary) and synchronized with the ADCLK output signal. Input data are read on the rising edge of ADCLK.

Table 1 Input modes

BYP IQS DESCRIPTION

0 clk digital baseband input sampled at 2048 kHz and with I and Q data multiplexed 1 0 digital IF input sampled at 8192 kHz, internal I/Q demodulator 1 1 digital IF input sampled at 8192 kHz, internal I/Q demodulator with I and Q swapped

In case of baseband input the IQ select signal shall indicate whether the current sample is either I or Q data (INP[9:0]).

ADCLK INP[9:0] IQS

4096 kHz

10 bits 2048 kHz

Fig.3 Baseband input signals (BYP = LOW).

Digital IF input is, typically, at a frequency of 2048 kHz. It is possible to apply sub-sampling on a N × 8.192 ±2.048 MHz (N = 1, 2, 3,...,19) IF signal, but care should be taken with the jitter of the crystal clock, which is proportional to N.

ADCLK

INP[9:0]

8192 kHz

10 bits

Fig.4 IF input signals [BYP = HIGH, IQS = LOW (no swap) or HIGH (swap)].

To use the on-chip null detector, pins

FSI and FSO shall simply be connected to each other.

When using an external null detector, the FSI input shall indicate the position of the null symbol in the baseband signal (FSI = LOW). The negative edge may have a maximum delay of 512 samples with respect to an ideal null detector. The delay compensation can be set via the I2C/L3 interface (register ATCWinControl). The FSI input provides edge jitter suppression of up to 40 samples starting from the first negative edge. Once the SAA3500H is in symbol processing mode, the FSI signal is ignored. During the null detection state, the Sync Lock Indicator (SLI) will be continuously LOW.

9.2 Memory interface

An external SRAM memory of either 128 or 256 kbytes is required to store the metrics from the data de-interleaver for half (432 CUs) or full (864 CUs) decoding capacity, respectively. The upper address line A17 is available both true and inverted (A17) to allow memory extension without an address decoder. 3.3 V RAMs should be used with either an 8 or (2 ×) 4-bit data bus and an access time of ≤80 ns. Input data are read on the rising edge of RD, output data shall be latched on the rising edge of WR.

2000 Jun 14 9

Philips Semiconductors Preliminary speciﬁcation

Digital audio broadcast channel decoder SAA3500H

A[17:0]

D[7:0]

Fig.5 RAM access.

9.3 Parallel output interface

The digital parallel output interface can be used in 3 different modes depending on the OCIR and OEN select pins. Output data shall be latched on the falling edge of OCLK.

Table 2 Parallel output modes X = don’t care.

OCIR OEN DESCRIPTION

0 0 channel impulse response sampled at 64 kHz, OIQ = frame trigger 1 0 baseband sampled at 2048 kHz and with I and Q data multiplexed X 1 OUT[7:0], OIQ and OCLK disabled

By means of an external digital-to-analog converter, either the CIR or I/Q data can be displayed on an oscilloscope. Digitaloutput data isclockedout on thefallingedge of theOCLKoutput signal. Incaseof baseband outputtheOIQ signal indicates, if the current sample is either I or Q data.

OCLK

OUT[7:0]

OIQ

QIQIQ

4096 kHz

signed

2048 kHz

Fig.6 Baseband output signals (OCIR = HIGH, OEN = LOW).

OCLK

OUT[7:0]

OIQ

64 kHz

unsigned

trigger

Fig.7 CIR output signals (OCIR = LOW, OEN = LOW).

2000 Jun 14 10

+ 22 hidden pages

Philips SAA3500H Technical data

CONTENTS

1 FEATURES

2 APPLICATIONS

3 GENERAL DESCRIPTION

4 QUICK REFERENCE DATA

5 ORDERING INFORMATION

6 BLOCK DIAGRAM

7 PINNING

8 FUNCTIONAL DESCRIPTION

9 INTERFACE DESCRIPTION

9.1 Input interface

9.2 Memory interface

9.3 Parallel output interface