11THERMAL CHARACTERISTICS
12DC CHARACTERISTICS
13AC CHARACTERISTICS
14APPLICATION INFORMATION
14.1Clock oscillator
14.2Reset input
14.3Boundary scan test interface
15PACKAGE OUTLINE
16SOLDERING
16.1Introduction to soldering surface mount
packages
16.2Reflow soldering
16.3Wave soldering
16.4Manual soldering
16.5Suitability of surface mount IC packages for
wave and reflow soldering methods
17DATA SHEET STATUS
18DEFINITIONS
19DISCLAIMERS
20PURCHASE OF PHILIPS I2C COMPONENTS
2000 Jun 142
Philips SemiconductorsPreliminary specification
Digital audio broadcast channel decoderSAA3500H
1FEATURES
• DigitalAudioBroadcast(DAB)full-capacitydemodulator
and decoder
• Supports DAB transmission modes I, II, III and IV
• Integrated Analog-to-Digital Converter (ADC) for
IF input
• Digital mixer with on-chip digital Automatic Frequency
Control (AFC) and Automatic Gain Control (AGC)
• Detectors for null symbol, DAB mode and transmitter
identification
• On-chip or external synchronization algorithms and
control loops
• On-chip timing PLL and DCXO
• Dynamic DAB multiplex reconfiguration supported
• Equal and unequal error protection for up to
64 sub-channels
• Fast information channel buffering
• Simple full capacity output
• Receiver data interface
• Serial output for three sub-channels
• I2C-bus or L3-bus control interface.
2APPLICATIONS
• Mobile receivers (FM/DAB car radios)
• Personal Computer add-ons
• Test and measurement equipment
• Portable radios.
3GENERAL DESCRIPTION
The Philips SAA3500H is a Digital Audio Broadcast (DAB)
channel decoder according to the ETSI specification
ETS 300 401.The SAA3500H is a successor tothePhilips
FADIC and SIVIC chip set and provides an IF ADC, digital
mixer, full DAB ensemble demodulation and decoding as
well as time and frequency synchronization functions.
Because of the full-speed Viterbi decoding capacity and a
high-speed receiver data output interface, DAB data
reception is not limited by the SAA3500H channel
decoder.
4QUICK REFERENCE DATA
SYMBOLPARAMETERMIN.TYP.MAX.UNIT
V
V
I
DD
f
clk
T
T
DD
i(max)
amb
stg
supply voltage3.03.33.6V
maximum input voltage−0.5−VDD+ 0.5V
DC supply current−−180mA
clock frequency−24576−kHz
ambient temperature−40+25+85°C
storage temperature−65−+150°C
ADC1inputanalog-to-digital converter DC input
AIF2inputanalog-to-digital converter IF input
V
SSA
ADE99inputanalog-to-digital converter enable (active LOW)
V
DDA
INP[0:9]8 to 17 input2048 kHz IF or baseband digital parallel input data (8 or 10 bits)
ADCLK19output analog-to-digital clock output 8192 kHz if
IQS20inputclock signal indicating I or Q baseband data if
BYP21inputIF input stage bypass (active LOW)
FSI22inputframe sync input (LOW indicates DAB null symbol detection)
FSO23outputnull detector/frame sync output (LOW indicates DAB null symbol position)
SLI24output AGC synchronization lock indicator (HIGH if synchronized)
AGC25output AGC level comparator output (HIGH if input sample > reference level, else LOW)
OSCI4inputoscillator or system clock input, 24576 kHz
OSCO5output oscillator output
MCLK41outputmaster clock output, 24576 kHz
V
SS
V
DD
TEST92inputconnect to ground for proper operation
OUT[0:7]32 to 39 outputbaseband or channel impulse response output
OCLK27output output data clock (negative edge indicates new data)
OIQ29outputoutput I or Q select signal if
OCIR30inputoutput select: baseband if OCIR = HIGH, CIR if OCIR = LOW
OEN31inputoutput enable (active LOW)
CFIC51outputmicrocontroller interface signal indicating Fast Information Channel (FIC) processing
CMODE52inputmicrocontroller interface mode input (only L3-bus)
CDATA53I/Omicrocontroller interface serial data I
CCLK54inputmicrocontroller interface clock input I
RESET55inputchip reset input (active LOW)
A[17:11]62 to 68 outputaddress outputs external RAM
A[10:0]81 to 91 output address outputs external RAM
WR61output write data to RAM (active LOW)
RD69outputread data from RAM (active LOW)
A1770output address bit 17 inverted for second RAM (128k × 8)
D[0:7]71 to 78 I/Odata input/output external RAM
3ground analog supply ground
100supply analog voltage supply (+3.3 V)
signal for swapping I and Q data bytes if BYP = HIGH
7, 18,
supply digital supply ground
26, 40,
60, 80
and 94
6, 28,
supply digital voltage supply (+3.3 V)
42 and
79
BYP = HIGH, 4096 kHz if BYP = LOW
BYP = LOW;
OCIR = HIGH, or frame trigger if OCIR = LOW
2
C-bus or L3-bus (5 V tolerant)
2
C-bus or L3-bus
2000 Jun 145
Philips SemiconductorsPreliminary specification
Digital audio broadcast channel decoderSAA3500H
SYMBOLPINTYPEDESCRIPTION
SOV344outputserial output valid data 3
SOV245outputserial output valid data 2
SOV146outputserial output valid data 1
SOD347output serial output data 3
SOD248output serial output data 2
SOD149output serial output data 1 (from channel decoder)
SOC50output serial output clock (384 kHz continuous)
REF43output receiver error flag [from Viterbi decoder, for Simple Full Capacity Output (SFCO)]
SFCO56outputsimple full capacity output (direct from Viterbi decoder)
RDC57output receiver data clock (6144 kHz continuous) or SFCO clock (burst)
RDE58inputRDI output enable (active LOW)
RDO59outputreceiver data interface bi-phase output
TDO93outputboundary scan test serial output
TCK95inputboundary scan test clock input
TDI96inputboundary scan test serial input
TMS97inputboundary scan test mode select input
TRST98inputboundary scan test reset input
The 2.048 MHz IF signal is digitized by an 8-bit flash
Analog-to-Digital Converter (ADC), which samples at
8.192 MHz. The required input level is limited to a
peak-to-peak voltage of 2 V. Due to a fast
sample-and-hold circuit sub-sampling is possible, so that
all IF frequencies of N × 8.192 ±2.048 MHz can be used.
If a higher resolution ADC is wanted, anexternal ADCcan
be connected.
The digital mixer accepts a 2.048 MHzIF signal atits input
and converts it to baseband with In-phase (I) and
Quadrature-phase (Q) components. The mixer frequency
is adjusted on a DAB frame basis with 1 Hz resolution to
prevent performance degradation. The mixer output
signals are digitally filtered and subjected to internal
Automatic Gain Control (AGC) before entering the
subsequent Fast Fourier Transform (FFT) stage.
The output of the digital AGC detectors indicates for each
input sample whether the level is below or above the
reference input level. By means of external filtering and
gain control, the signal can be used to adjust the input
signal level of the analog-to-digital converter (external
AGC).
The on-chip null detector operates on the digital baseband
signal and indicates the coarse position of the DAB null
symbol (FSO = LOW), which is used for time base
initialization. The spacing of detected null symbols is used
to detect the DAB transmission mode.
The time base counts samples on a symbol and a frame
basis in order to generate the internal control windows for
the FFT and to generate a frame sync signal (FSO) during
thenullsymbol.Initializationofthe time base is determined
by the null detector signal (FSI) and the selected DAB
mode. After time base initialization the SAA3500H will be
in symbol processing mode and the null detector will be
deactivated.
The OFDM symbol demodulator applies a real-time FFT
and differential demodulation to the baseband signal. The
output is quantized to 4-bit metrics for the Viterbi decoder.
The position of the FFT window is adjusted on a DAB
frame basis in order to avoid Inter-Symbol Interference
(ISI).
TheFFTresultof the reference symbol is processed bythe
synchronization core, which performs two functions:
estimation of the frequency error of the baseband signal,
which is needed to adjust the digital mixer (AFC), and
calculation of the Channel Impulse Response (CIR) to be
used for positioning of the FFT window and the system
clock.All timing and frequency controlloopsare realized in
the synchronization core and can be influenced from the
control interface.
The Viterbi decoder is preceded by frequency and time
de-interleavingof the incoming metricsinexternal RAM, to
distribute burst errors caused by channel fading. Variable
rate decoding is done with 3.072 Mb/s decision speed.
Output bits are re-encoded and compared to
corresponding input bits in order to generate an error flag
signal.
Sub-channel selection is done on a Capacity Unit (CU)
basis. All standardized Unequal Error Protection (UEP)
puncturing schemes for audio and Equal Error Protection
(EEP) schemes for data are provided. Up to
64 sub-channelscanbeselectedseparately,whichmeans
virtually unlimited DAB decoding capabilities.
The output interface provides a full-speed standardized
Receiver Data Interface (RDI) for all sub-channel data.
This allows to extend every DAB receiver with external
decoders for all kind of services. A dedicated interface is
provided for the Philips SAA2502H audio source decoder,
which completes the DAB receiver.
The system clock of 24.576 MHz, can be generated by an
integrated DCXO, which is internally locked to the DAB
signal. The clockis available on the MCLKpin to provide a
synchronous clock to the MPEG decoder and
microcontroller.
The I2C-bus or L3-bus configurable control interface
provides access to Automatic Frequency Control (AFC),
Channel Impulse Response (CIR), Fast Information
Channel (FIC) and sub-channel selection controls.
2000 Jun 148
Philips SemiconductorsPreliminary specification
Digital audio broadcast channel decoderSAA3500H
9INTERFACE DESCRIPTION
9.1Input interface
The input interface can be used in 3 different modes, depending on the bypass (BYP) and IQ Select (IQS) pins. Digital
input data should be in two’s complement format (optionally: offset binary) and synchronized with the ADCLK output
signal. Input data are read on the rising edge of ADCLK.
Table 1 Input modes
BYPIQSDESCRIPTION
0clkdigital baseband input sampled at 2048 kHz and with I and Q data multiplexed
10digital IF input sampled at 8192 kHz, internal I/Q demodulator
11digital IF input sampled at 8192 kHz, internal I/Q demodulator with I and Q swapped
In case of baseband input the IQ select signal shall indicate whether the current sample is either I or Q data (INP[9:0]).
ADCLK
INP[9:0]
IQS
Q
I
0
1
Q
I
1
Q
2
2
4096 kHz
10 bits
2048 kHz
Fig.3 Baseband input signals (BYP = LOW).
Digital IF input is, typically, at a frequency of 2048 kHz. It is possible to apply sub-sampling on a N × 8.192 ±2.048 MHz
(N = 1, 2, 3,...,19) IF signal, but care should be taken with the jitter of the crystal clock, which is proportional to N.
ADCLK
INP[9:0]
8192 kHz
10 bits
Fig.4 IF input signals [BYP = HIGH, IQS = LOW (no swap) or HIGH (swap)].
To use the on-chip null detector, pins
FSI and FSO shall simply be connected to each other.
When using an external null detector, the FSI input shall indicate the position of the null symbol in the baseband signal
(FSI = LOW). The negative edge may have a maximum delay of 512 samples with respect to an ideal null detector. The
delay compensation can be set via the I2C/L3 interface (register ATCWinControl). The FSI input provides edge jitter
suppression of up to 40 samples starting from the first negative edge. Once the SAA3500H is in symbol processing
mode, the FSI signal is ignored. During the null detection state, the Sync Lock Indicator (SLI) will be continuously LOW.
9.2Memory interface
An external SRAM memory of either 128 or 256 kbytes is required to store the metrics from the data de-interleaver for
half (432 CUs) or full (864 CUs) decoding capacity, respectively. The upper address line A17 is available both true and
inverted (A17) to allow memory extension without an address decoder. 3.3 V RAMs should be used with either an 8 or
(2 ×) 4-bit data bus and an access time of ≤80 ns. Input data are read on the rising edge of RD, output data shall be
latched on the rising edge of WR.
2000 Jun 149
Philips SemiconductorsPreliminary specification
Digital audio broadcast channel decoderSAA3500H
A[17:0]
D[7:0]
RD
WR
Fig.5 RAM access.
9.3Parallel output interface
The digital parallel output interface can be used in 3 different modes depending on the OCIR and OEN select pins.
Output data shall be latched on the falling edge of OCLK.
Table 2 Parallel output modes
X = don’t care.
OCIR OENDESCRIPTION
00channel impulse response sampled at 64 kHz, OIQ = frame trigger
10baseband sampled at 2048 kHz and with I and Q data multiplexed
X1OUT[7:0], OIQ and OCLK disabled
By means of an external digital-to-analog converter, either the CIR or I/Q data can be displayed on an oscilloscope.
Digitaloutput data isclockedout on thefallingedge of theOCLKoutput signal. Incaseof baseband outputtheOIQ signal
indicates, if the current sample is either I or Q data.