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INTEGRATED CIRCUITS
SA5225
Fiber optic postamplifier
Product specification |
1998 Oct 07 |
Replaces datasheet NE/SA5225 of 1997 Jun 05
IC19 Data Handbook
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Philips Semiconductors |
Product specification |
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Fiber optic postamplifier |
SA5225 |
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DESCRIPTION
The SA5225 is a high-gain limiting amplifier that is designed to process signals from fiber optic preamplifiers. Capable of operating at 125Mb/s, the chip has input signal level-detection with a user-adjustable threshold. The DATA and LEVEL-DETECT outputs are differential for optimum noise margin and ease of use. Also available is the SA5224 which is optimized for FDDI applications.
FEATURES
•Wideband operation: 1.0kHz to 120MHz typical
•Applicable in 155Mb/s OC3/SONET receivers
•Operation with single +5V or ±5.2V supply
•Differential 10k ECL outputs
•Programmable input signal level-detection
•Fully differential for excellent PSRR to 1GHz
PIN DESCRIPTION
D Package
CAZN |
1 |
16 |
VSET |
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CAZP |
2 |
15 |
VREF |
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GNDA |
3 |
14 |
VCCE |
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DIN |
4 |
13 |
DOUT |
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5 |
12 |
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DOUT |
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DIN |
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VCCA |
6 |
11 |
GNDE |
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CF |
7 |
10 |
ST |
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JAM |
8 |
9 |
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ST |
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SD00374 |
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Figure 1. Pin Configuration
APPLICATIONS
•Data communication in noisy industrial environments
•LANs
ORDERING INFORMATION
DESCRIPTION |
TEMPERATURE RANGE |
ORDER CODE |
DWG # |
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16-Pin Plastic Small Outline (SO) Package |
±40 to +85°C |
SA5225D |
SOT109-1 |
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BLOCK DIAGRAM
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VCCA |
CAZP |
CAZN |
VCCE |
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(6) |
(2) |
(1) |
(16) |
DIN (4) |
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LIMITING |
ECL |
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DIN (5) |
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AMPLIFIER |
BUFFER |
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JAM |
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BUFFER |
VREF(15) |
REFERENCE |
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LEVEL |
SD |
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DETECTOR |
BUFFER |
VSET(16) |
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(3) |
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(7) |
(11) |
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GNDA |
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CF |
GNDE |
(13) DOUT
(12) DOUT
(8)JAM
(9)ST
(10)ST
SD00375
Figure 2. Block Diagram
1998 Oct 07 |
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853-1595 20141 |
Philips Semiconductors |
Product specification |
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Fiber optic postamplifier |
SA5225 |
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PIN DESCRIPTIONS
PIN NO. |
NAME |
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FUNCTION |
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1 |
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CAZN |
Auto-zero capacitor pin. Connecting a capacitor between this pin and CAZP will cancel the offset voltage of the |
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limiting amplifier. |
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2 |
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CAZP |
Auto-zero capacitor pin. Connecting a capacitor between this pin and CAZN will cancel the offset voltage of the |
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limiting amplifier. |
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3 |
GNDA |
Analog GND pin. Connect to ground for +5V upshifted ECL operation. Connect to ±5.2V for standard ECL |
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operation. Must be at same potential as GNDE (Pin 11). |
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4 |
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DIN |
Differential input. DC bias level is set internally at approximately 2.9V. Complimentary to |
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(Pin 5). |
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DIN |
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5 |
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Differential input. DC bias level is set internally at approximately 2.9V. Complimentary to DIN (Pin 4). |
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DIN |
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6 |
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VCCA |
Analog power supply pin. Connect to a +5V supply for upshifted ECL operation. Connect to ground for standard |
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ECL operation. Must be at same potential as VCCE (Pin 14). |
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7 |
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CF |
Filter capacitor for level detector. Capacitor should be connected between this pin and VCCA. |
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8 |
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JAM |
This ECL-compatible input controls the output buffers |
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and DOUT (Pins 12 and 13). When an ECL LOW signal |
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DOUT |
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is applied, the outputs will follow the input signal. When an ECL HIGH signal is applied, the DOUT and |
DOUT |
pins |
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will latch into LOW and HIGH states, respectively. When left unconnected, this pin is actively pulled-low (JAM OFF). |
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9 |
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Input signal level-detect |
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This ECL output is high when the input signal is below the user programmable |
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ST |
STATUS. |
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threshold level. |
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10 |
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ST |
ECL compliment of |
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(Pin 9). |
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ST |
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11 |
GNDE |
Digital GND pin. Connect to ground for +5V upshifted ECL operation. Connect to a negative supply for normal ECL |
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operation. Must be at the same potential as GNDA (Pin 3). |
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12 |
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ECL-compatible output. Nominal level is VCCE±1.3V. When JAM is HIGH, this pin will be forced into an ECL HIGH |
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DOUT |
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condition. Complimentary to DOUT (Pin 13). |
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13 |
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DOUT |
ECL-compatible output. Nominal level is VCCE±1.3V. When JAM is HIGH, this pin will be forced into an ECL LOW |
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condition. Complimentary to |
DOUT |
(Pin 12). |
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14 |
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VCCE |
Digital power supply pin. Connect to a +5V supply for upshifted ECL operation. Connect to ground during normal |
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ECL operation. Must be at the same potential as VCCA (Pin 6). |
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15 |
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VREF |
Reference voltage for threshold level voltage divider. Nominal value is approximately 2.64V. |
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16 |
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VSET |
Input threshold level setting circuit. This input can come from a voltage divider between VREF and GNDA. |
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ABSOLUTE MAXIMUM RATINGS
SYMBOL |
PARAMETER |
RATING |
UNITS |
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VCC |
Power supply (VCC - GND) |
6 |
V |
TA |
Operating ambient |
±40 to +85 |
°C |
TJ |
Operating junction |
±55 to +150 |
°C |
TSTG |
Storage |
±65 to +150 |
°C |
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Power dissipation, T = 25°C (still air)1 |
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PD |
A |
1100 |
mW |
16-pin Plastic SO |
NOTE:
1. Maximum dissipation is determined by the ambient temperature and the thermal resistance, θJA: 16-pin SO: θJA = 110°C/W
RECOMMENDED OPERATING CONDITIONS
SYMBOL |
PARAMETER |
RATING |
UNITS |
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VCC |
Supply voltage |
4.5 to 5.5 |
V |
TA |
Ambient temperature ranges |
±40 to +85 |
°C |
TJ |
Junction temperature ranges |
±40 to +110 |
°C |
1998 Oct 07 |
3 |
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