Product specification
Supersedes data of 1998 Jul 21
IC17 Data Handbook
2000 Oct 23
Philips SemiconductorsProduct specification
SA1630IF quadrature transceiver
DESCRIPTION
The SA1630 is a 70–400 MHz I/Q transceiver for wireless LAN.
The Receive Path contains a digitally gain controlled linear IF
amplifier, a pair of quadrature down conversion mixers and a pair of
baseband amplifiers. The transmit path contains a pair of quadrature
up conversion mixers that transposes a quadrature baseband input
signal up to IF frequency. An external VCO signal is divided
internally and provides quadrature local oscillator signals for the
mixers. Another divider chain, reference divider and phase detector
are provided to avoid the need for an external synthesizer. To keep
power consumption to a minimum the transmit, receive and local
oscillator functions can be powered down under digital control.
FEA TURES
•Low supply voltage operation of 2.7 V for main chip and
2.9 V for charge pump.
•Low current consumption: 33.5 mA in RX, 26.5 mA in TX, typical
at 3 V.
•Flexible power up/down options.
•Optional 2.5 V regulated reference voltage available during
transmit.
•Input IF frequency range of 70–400 MHz.
BE Package
IF IN
IF INX
V
CC
GNDRX
V
CC
PLL_ON
Rx_ON
GNDHDR
GC0
GC1
GC2
GC3
GC4
GC5
GNDRx
Rx
1
2
3
Rx
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19
GNDRxRxRx
GNDRXTxTx
45464748
•Internal IF PLL for synthesizing the local IF oscillator signal.
•Bandwidth of baseband Tx inputs is 20 MHz and that of baseband
Rx outputs is 8.5 MHz.
•Designed for IEEE 802.11 wireless LAN using Direct Sequence
Spread Spectrum modulation.
•Control registers power up in a default state.
•Only a standard reference input frequency required, choice of 8,
11, 22 or 44 MHz.
•Digital gain control of 70 dB in steps of 2 dB.
•Rx Baseband amplifiers are capable of driving 1 kW ||15 pF
•Rx Baseband o/p’s clamp symmetrically, above 1 Vp–p in order to
prevent dc bias shift under overdrive conditions.
•Package: LQFP48, PCMCIA compatible
APPLICATIONS
•IF circuitry for IEEE 802.11 DSSS wireless LAN.
•Applications for high speed wireless data.
IFOUT
IFOUTX
424344
20 21 22 23 24
GNDTxRx
GNDTxRx
CC
V TxRx
3940413738
REF
REF
V 2.5
I
36
35
34
33
32
31
30
29
28
27
26
25
GNDCP
CP
V CP
CC
DATA
CLOCK
STROBE
LOCK
LO_INX
LO_IN
GNDRx
CLK IN
CLK
INX
GND_BB
GND_BB
CC
V _BB
Q_RxOUT
I_Tx_IN
I_RXOUT
Q_Tx IN
I_Tx_INX
CC
Q_Tx INX
V _DIG
Tx_ON
GNDDIG
SR01549
Figure 1.Pin Configuration
ORDERING INFORMATION
DESCRIPTIONTEMPERATURE RANGEORDER CODEDWG #
48–Pin Plastic Low Profile Quad Flat package–40 to +85 °CSA1630BESOT313–2
2000 Oct 23853–2049 24857
2
Philips SemiconductorsProduct specification
SA1630IF quadrature transceiver
(46)
(45)
(10)
(11)
(12)
(4)
PLL–ON
R
Tx
Tx
IFOUT
Tx
IFOUTX
LO IN
LO INX
XON
MODE
ON
CONTROL
÷
2
(5)
(23)
(43)
(42)
(7)
GC0
(8)
GC1
(9)
GC2
Rx
IFIN
Rx
IFINX
GC3
GC4
GC5
(28)
(29)
(38)
2.5V REGULATOR
BUFFERS
V
2.5
REF
(1,3)
VCCR
(39)
VCCTXR
X
X
GND_BB
VCC_BB
I_Tx
IN
I_Tx
INX
Q_Tx
IN
Q_Tx
INX
I_Rx
Q_Rx
OUT
OUT
1
1
(13, 14)
(15)
(18)
(19)
(20)
(21)
(17)
(16)
(34)
(35)
(37)
(30)
(36)
V
CCCP
CP
I
REF
LOCK
GNDCP
CHARGE
8, 11, 22, 44
÷
CLK
IN
DAC
PUMP
N
÷
PHASE
DETECTOR
TEST REGISTER
INX
V
CCDIG
GND DIGCLK
Figure 2.Block Diagram
SYNTH
REGISTER
SERIAL
INPUT
DATA CLOCK STROBE
(2, 27, 44, 47, 48)(31)(32)(33)(24)(22)(25)(26)
GND RX
GND HDR
GNDTXR
(6)
X
(40, 41)
SR01551
2000 Oct 23
3
Philips SemiconductorsProduct specification
SA1630IF quadrature transceiver
PIN DESCRIPTIONS
Pin No.Pin NameDescription
1, 3VCCRxSupply Pin for Rx section (IF circuits)
2, 27,
44,47,
13, 14GND_BBGround pin for Rx baseband circuits
40,41GNDTxRxGround pins used by Tx circuits
GNDRxGround pins for Rx section (IF circuits)
48
4PLL_ONOne of the three digital CMOS logic control inputs to the mode control section
5Rx_ONOne of the three digital CMOS logic control inputs to the mode control section
6GNDHDRSubstrate ground
7GCOControl bit 0 for IF VGA gain control, CMOS input
8GC1Control bit 1 for IF VGA gain control, CMOS input
9GC2Control bit 2 for IF VGA gain control, CMOS input
10GC3Control bit 3 for IF VGA gain control, CMOS input
11GC4Control bit 4 for IF VGA gain control, CMOS input
12GC5Control bit 5 for IF VGA gain control, CMOS input
15VCC_BBSupply Pin for Rx Baseband circuits
16Q_RXOUTQuadrature–phase Rx baseband output, single–ended
17I_RxOUTIn–phase Rx baseband output, single–ended
18I_Tx INIn–phase differential Tx baseband input, positive
19I_Tx INXIn–phase dif ferential Tx baseband input, negative
20Q_Tx INQuadrature differential Tx baseband input, positive
21Q_Tx INXQuadrature differential Tx baseband input, negative
22VCC_DIGSupply for digital circuits
23Tx_ONOne of the Three digital CMOS logic control inputs to the mode control section
24GNDDIGDigital ground
25CLK INXDif ferential reference input for synthesizer, negative
26CLK INDifferential reference input for synthesizer, positive
28LO_INDifferential LO input,positive
29LO INXDifferential LO input, negative
30LOCKTest control output and synthesizer lock indicator
31STROBESerial bus strobe input
32CLOCKSerial bus clock input
33DATASerial bus data input
34VCCCPSupply for charge pump circuits
35CPCharge pump output
36GNDCPGround for charge pump circuits
37I
REF
38V
39VCCTxRxSupply pin used by Tx circuits
42TxIFOUTXDifferential transmitter IF output (open collector), positive
43TxIFOUTDifferential transmitter IF output (open collector), negative
45RxIF INXDifferential receiver IF input, negative
46RxIF INDifferential receiver IF input, positive
2.5Reference voltage of 2.5V available for external use
REF
Charge pump reference current
2000 Oct 23
4
Philips SemiconductorsProduct specification
SA1630IF quadrature transceiver
ABSOLUTE MAXIMUM RATINGS
SYMBOLPARAMETERRATINGUNITS
V
CCXX
V
IN
∆VGAny GND pin to any other GND pin0V
P
D
T
JMAX
P
MAX
T
stg
RECOMMENDED OPERATING CONDITIONS
SYMBOLPARAMETERRATINGUNITS
V
CCXXXX
VCCCPCharge pump supply voltage2.7 to 3.6V
T
amb
NOTES:
1. There are no ESD protection diodes between pins 42, 43 and V
reduced. Proper ESD handling precautions should be followed.
MODE CONTROL
NO:PLL_ONRX_ONTX_ONSTATE DESCRIPTIONMODE2.5 V REF
10XXSLEEP modeSLEEPOff
2101Synthesizer ON, Rx STDBY, Tx OFFWAITOff
3111Synthesizer ON, Rx STDBY, Tx ONTRANSMITOn
4110Synthesizer ON, Rx ON, Tx OFFRECEIVEOff
5100Synthesizer ON, Rx OFF, Tx ONTRANSMITOff
‘0’ – Logic LOW
‘1’ – Logic HIGH
‘X’ – Don’t Care
Supply voltages–0.3 to +6.0V
Voltage applied to any other pin–0.3 to V
Power dissipation, TA = 25°C (still air)300mW
Maximum operating junction temperature150°C
Maximum power input/output+20dBm
Storage temperature range–65 to +150°C
Supply voltages:2.7 to 3.6V
Operating ambient temperature range–40 to +85°C
to allow higher AC peak voltage. The ESD protection level has thus been
CC
+0.3V
CCXX
1. Sleep mode (PLL OFF, Rx OFF, Tx OFF)
In this mode everything is switched off except the 3–wire digital bus.
As long as the digital supply is still on, the programmed values are
active and the 3–wire bus will continue to be programmable.
2. Wait Mode (Tx Off, Rx Standby)
PLL is on. Receiver is in the reduced current standby mode and the
transmitter is completely switched off. This mode maybe useful if the
PLL is to be kept on and is waiting for a quick turn–on to either
transmit or receive modes, especially when Rx outputs are AC
coupled.
3. Transmit mode (Rx standby)
The PLL and transmitter are on. The receive section is in a reduced
current mode wherein most of the Rx circuitry is powered down
except for the bias and baseband circuits needed to hold the
baseband output voltages in the active state. This mode is useful if
the Rx baseband outputs are AC coupled via a large capacitor and
the application demands quick turn–on for the Rx, from Tx.
4. Receive Mode (Tx Off)
The Transmitter is completely shut–off. The PLL and receiver
sections are operating.
5. Transmit Mode (Rx OFF)
PLL and Transmit sections are on. However, the Receiver is
completely shut–down. This mode is useful if the Rx baseband
outputs are DC coupled to the external world.