Philips PTPM749A, PTPM749DB Datasheet

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TPM749

Microcontroller with TrackPoint microcode from IBM

Product specification 1996 May 01

INTEGRATED CIRCUITS

Data Handbook IC20

Philips Semiconductors Product specification

TPM749Microcontroller with TrackPoint microcode from IBM

1996 May 01 853-1831 16753

DESCRIPTION

The Philips Semiconductors TPM749 is a small package, low cost, ROM-coded 80C51 with IBM’s TrackPoint pointing algorithms and control code. TrackPoint is the result of years of human factors research and innovation at IBM. The result is a “velocity sensitive” pointing solution more efficient and easier to use than “position sensitive” devices such as the mouse, the trackball, or the touchpad.

IBM has licensed Philips Semiconductors to sell microcontrollers with TrackPoint code. By purchasing a TPM from Philips, the purchaser becomes a sub-licensee of Philips. The selling price of Philips’ TPM includes the royalties for IBM’s intellectual property, which Philips in turn pays to IBM. Customers for TPMs do not need to sign any licensing agreement with either IBM or Philips. This code is the intellectual property of IBM, which is covered by numerous patents, and must be treated accordingly.

The TPM is fabricated with Philips high-density CMOS technology. Philips epitaxial substrate minimizes CMOS latch-up sensitivity.

The TPM contains a 2k × 8 ROM, a 64 × 8 RAM, 21 I/O lines, a 16-bit auto-reload counter/timer, a fixed-priority level interrupt structure, an on-chip oscillator, a five channel multiplexed 8-bit A/D converter, and an 8-bit PWM output.

The TPM supports two power reduction modes of operation referred to as the idle mode and the power-down mode.

FEATURES

•80C51 based architecture

•Small package sizes

– 28-pin Shrink Small Outline Package (SSOP) – 28-pin PLCC

•Low power consumption:

– Normal operation: less than 11mA @ 5V, 12MHz – Idle mode – Power-down mode

•2k × 8 ROM

•64 × 8 RAM

•16-bit auto reloadable counter/timer

•5-channel 8-bit A/D converter

•8-bit PWM output/timer

•10-bit fixed-rate timer

•CMOS and TTL compatible

PIN CONFIGURATION

1 2

4 5

6 7 8

9 10 11 12

P3.4/A4

P3.3/A3

P3.2/A2/A10

P3.1/A1/A9 P3.0/A0/A8

P0.2

RST

X2 X1

P0.0/ASEL

P1.4/ADC4/D4

P1.5/INT0/D5

P1.6/INT1

/D6

P1.7/T0/D7

P0.3

P0.4/PWM OUT

P3.7/A7

P3.6/A6

P3.5/A5

SHRINK

SMALL

OUTLINE

PACKAGE

PLASTIC

LEADED

CHIP

CARRIER

4 1 26

12 18

P0.1/OE

P1.0/ADC0/D0 P1.1/ADC1/D1

P1.3/ADC3/D3 P1.2/ADC2/D2

Pin Function

1 P3.4/A4 2 P3.3/A3 3 P3.2/A2/A10 4 P3.1/A1/A9 5 P3.0/A0/A8 6 P0.2 7 P0.1/OE 8 P0.0/ASEL

9 RST 10 X2 11 X1 12 V

13 P1.0/ADC0/D0 14 P1.1/ADC1/D1

Pin Function

15 P1.2/ADC2/D2 16 P1.3/ADC3/D3 17 P1.4/ADC4/D4 18 AV

19 AV

20 P1.5/INT0/D5 21 P1.6/INT1

/D6 22 P1.7/T0/D7 23 P0.3 24 P0.4/PWM OUT 25 P3.7/A7 26 P3.6/A6 27 P3.5/A5 28 V

SU00692A

ORDERING INFORMATION

ORDERING CODE TEMPERATURE RANGE AND PACKAGE DRAWING NUMBER

PTPM749 A 0 to +70°C, Plastic Leaded Chip Carrier SOT261-3

PTPM749 DB 0 to +70°C, Shrink Small Ouline Package SOT341-1

For compatible pointing device, contact:

COMPANY

CONTACT TELEPHONE

Bokam Engineering Ms. Jane Kamenster (714)513-2200 CTS Corporation Mr. Dave Poole (219)589-7169

IBM is a registered trademark, and TrackPoint is a trademark of IBM Corporation.

Philips Semiconductors Product specification

TPM749Microcontroller with TrackPoint microcode from IBM

1996 May 01

PIN DESCRIPTION

MNEMONIC PIN NO. TYPE NAME AND FUNCTION

12 I Circuit Ground Potential.

28 I Supply voltage during normal, idle, and power-down operation.

P0.0–P0.4 8–6

23, 24

I/O Port 0: Port 0 is a 5-bit bidirectional port. Port 0.0–P0.2 are open drain. Port 0.0–P0.2 pins that have

1s written to them float, and in that state can be used as high-impedance inputs. P0.3–P0.4 are bidirectional I/O port pins with internal pull-ups. These pins are driven low if the port register bit is written with a 0. The state of the pin can always be read from the port register by the program. Port 0.3 and 0.4 have internal pull-ups that function identically to port 3. Pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs.

While P0.0 anbd P0.1 differ from “standard TTL” characteristics, they are close enough for the pins to still be used as general-purpose I/O.

6 I VPP (P0.2) – Programming voltage input. 7 I OE (P0.1) – Input which specifies verify mode (output enable).

OE = 1 output enabled (verify mode).

8 I ASEL (P0.0) – Input which indicates which bits of the EPROM address are applied to port 3.

ASEL = 0 low address byte available on port 3. ASEL = 1 high address byte available on port 3 (only the three least significant bits are used).

P1.0–P1.7 13–17,

20–22

I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to

them are pulled high by the internal pull-ups and can be used as inputs. P0.3–P0.4 pins are bidirectional I/O port pins with internal pull-ups. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: I

). Port 1 also

serves the special function features of the SC80C51 family as listed below: 20 I INT0 (P1.5): External interrupt. 21 I INT1 (P1.6): External interrupt. 22 I T0 (P1.7): Timer 0 external input.

13–17 I ADC0 (P1.0)–ADC4 (P1.4): Port 1 also functions as the inputs to the five channel multiplexed A/D

converter. These pins can be used as outputs only if the A/D function has been disabled. These pins

can be used as digital inputs while the A/D converter is enabled.

Port 1 serves to output the addressed EPROM contents in the verify mode and accepts as inputs the

value to program into the selected address during the program mode.

P3.0–P3.7 5–1,

27–25

I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to

them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are

externally being pulled low will source current because of the pull-ups. (See DC Electrical

Characteristics: IIL). Port 3 also functions as the address input for the EPROM memory location to be

programmed (or verified). The 11-bit address is multiplexed into this port as specified by P0.0/ASEL.

RST 9 I Reset: A high on this pin for two machine cycles while the oscillator is running resets the device. An

internal diffused resistor to V

permits a power-on RESET using only an external capacitor to VCC. After the device is reset, a 10-bit serial sequence, sent LSB first, applied to RESET, places the device in the programming state allowing programming address, data and V

to be applied for programming

or verification purposes. The RESET serial sequence must be synchronized with the X1 input.

X1 11 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. X1

also serves as the clock to strobe in a serial bit stream into RESET to place the device in the programming state.

X2 10 O Crystal 2: Output from the inverting oscillator amplifier. AV

19 I Analog supply voltage and reference input.

18 I Analog supply and reference ground.

NOTE:

1. AV

(reference ground) must be connected to 0V (ground). AVCC (reference input) cannot differ from VCC by more than ±0.2V, and must be

in the range 4.5V to 5.5V.

Philips Semiconductors Product specification

TPM749Microcontroller with TrackPoint microcode from IBM

1996 May 01

SCHEMATIC OF TrackPoint SYSTEM WITH PHILIPS TPM749

281913

21222326252410

RST

VCC

AVCC

ADC0

ADC4

P1.6

P1.7

P0.3

P3.6

P3.7

P0.4

P3.3

P3.5

P3.2

P3.4

2273

FTRANS

BUTTON3 *

INVERTX *

NOTMOU

P0.0

P0.17P3.0

P3.1

10K

6.04K

R10

6.04K

CLK

DATA

MCLK

MDATA

GND

PTPM749

PLCC28

P1.5

10uF

TO EXTERNAL

MOUSE

SYSTEM

BOARD

VSS

AVSS

12.0MHz

33pFC133pF

MIDDLE

LEFT

RIGHT

BUTTON ASSEMBLY

0.1uF

2.2uF

LMC6482

650K *

33pF

LMC6482

650K *

33pF

VP0610T

332

10K

GND

10K

54121311

976

DATA

CLK

RST

VCC

DS1267-10

R11

10K

Y+

Y–

X+

X–

PS1

PSTICK

STICK ASSEMBLY

1. CONNECT BUTTON 3 SIGNAL TO GND IF MIDDLE BUTTON USED.

2. CONNECT INVERTX SIGNAL TO GND IF BOKAM SENSOR USED.

3. Q1 MAY BE REPLACED WITH A JUMPER IF POWER DRAW IS NOT A CONCERN.

C5, C6 MAY THEN BE INCREASED TO A MAXIMUM OF 3900pF.

4. R9, R10 MAY BE INCREASED IF CABLE TO SYSTEM BOARD IS SHORT.

5. +5V, GND CONNECTIONS TO SYSTEM SUPPLY SHOULD BE FROM A SINGLE POINT CONNECTION.

6. THIS CIRCUIT CAN ONLY BE USED WHEN OVERALL STICK RESISTANCE HAS PRODUCTION VARIATIONS WITHIN 5%.

SU00694

MANUFACTURER:

Q1 – SILICONIX

U3 – DALLAS SEMICONDUCTOR

Philips Semiconductors Product specification

TPM749Microcontroller with TrackPoint microcode from IBM

1996 May 01

OSCILLATOR CHARACTERISTICS

X1 and X2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator.

To drive the device from an external clock source, X1 should be driven while X2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed.

IDLE MODE

The TPM includes the 80C51 power-down and idle mode features. In idle mode, the CPU puts itself to sleep while all of the on-chip peripherals except the A/D and PWM stay active. The functions that continue to run while in the idle mode are Timer 0, Timer I, and the interrupts. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. Upon powering-up the circuit, or exiting from idle mode, sufficient time must be allowed for stabilization of the internal analog reference voltages before an A/D conversion is started.

POWER-DOWN MODE

In the power-down mode, the oscillator is stopped and the instruction to invoke power-down is the last instruction executed. Only the contents of the on-chip RAM are preserved. A hardware reset is the only way to terminate the power-down mode. The control bits for the reduced power modes are in the special function register PCON.

Table 1. External Pin Status During Idle and

Power-Down Modes

MODE Port 0* Port 1 Port 2

Idle Data Data Data Power-down Data Data Data

* Except for PWM output (P0.4).

I/O Ports

The I/O pins provided by the TPM consist of port 0, port 1, and port 3.

Port 0

Port 0 is a 5-bit bidirectional I/O port and includes alternate functions on some pins of this port. Pins P0.3 and P0.4 are provided with internal pullups while the remaining pins (P0.0, P0.1, and P0.2) have open drain output structures. The alternate function for port P0.4 is PWM output.

If the alternate function PWM is not being used, then this pin may be used as an I/O port.

Port 1

Port 1 is an 8-bit bidirectional I/O port whose structure is identical to the 80C51, but also includes alternate input functions on all pins. The alternate pin functions for port 1 are:

P1.0-P1.4 - ADC0-ADC4 - A/D converter analog inputs P1.5 INT0

- external interrupt 0 input

P1.6 INT1

- external interrupt 1 input

P1.7 - T0 - timer 0 external input If the alternate functions INT0

, INT1, or T0 are not being used, these pins may be used as standard I/O ports. It is necessary to connect AV

and AVSS to VCC and VSS, respectively, in order to use P1.5, P1.6, and P1.7 pins as standard I/O pins. When the A/D converter is enabled, the analog channel connected to the A/D may not be used as a digital input; however, the remaining analog inputs may be used as digital inputs. They may not be used as digital outputs. While the A/D is enabled, the analog inputs are floating.

Port 3

Port 3 is an 8-bit bidirectional I/O port whose structure is identical to the 80C51. Note that the alternate functions associated with port 3 of the 80C51 have been moved to port 1 of the TPM (as applicable). See Figure 1 for port bit configurations.

P1.X

LATCH

D Q

CL Q

READ

LATCH

INT. BUS

WRITE TO

LATCH

READ

ALTERNATE INPUT

FUNCTION

P1.X

INTERNAL

PULL-UP

ALTERNATE

OUTPUT

FUNCTION

P0.X

LATCH

D Q

CL Q

READ

LATCH

INT. BUS

WRITE TO

LATCH

READ

ALTERNATE INPUT

FUNCTION

P0.X

ALTERNATE

OUTPUT

FUNCTION

SU00306

Figure 1. Port Bit Latches and I/O Buffers

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