Philips PTN1111BD Datasheet
INTEGRATED CIRCUITS
PTN1111
1:10 PECL clock distribution device
Product data
2001 Jun 19
Philips Semiconductors Product data
PTN1 11 11:10 PECL clock distribution device
FEA TURES
•80 ps part-to-part skew
•20 ps output-to-output skew
•Differential design
•PECL inputs and outputs
•V
reference output voltage available
BB
•75 kΩ input pulldown resistors
•Low voltage V
range of 2.375 V to +3.8 V
CC
•High signaling rate capability (above 1 GHz)
•Pin and function compatible to MC100EP111, MC100LVEP111
•Available in LQFP32 package
DESCRIPTION
The PTN1111 is a low-skew, 1:10 PECL clock distribution device.
One selected clock signal out of two selectable inputs is fanned out
to 10 identical, precision time-aligned differential outputs.
The PTN1111 is provided with a V
single-ended PECL input and with complementary clock inputs to
allow for differential PECL input.
The main purpose and benefit of the PTN1111 is low skew: between
individual outputs of a single PTN1111 (within-part skew or
output-to-output skew) as well as measured from part-to-part.
Within-part skew is realized by careful attention to internal layout
and design of the PTN1111, whereas part-to-part skew is achieved
by control and monitoring of relevant process parameters.
The PTN1111 can be used for high-performance, high-speed clock
distribution in systems which utilize PECL as the primary signaling
standard. Designers can take advantage of the device’s performance
to distribute clocks across a board or backplane, at an extremely high
degree of time alignment, thereby affording system processors to
achieve maximum utilization of the clock cycle.
reference voltage to allow for
BB
PIN CONFIGURATION
CCO
Q2
Q2
V
27
26
25
24
Q3
23
Q3
22
Q4
21
Q4
20
Q5
19
Q5
18
Q6
17
Q6
14
15
16
Q7
Q7
CCO
V
ST00011
V
CLK_SEL
CLK0
CLK0
V
CLK1
CLK1
V
CCO
V
32
1
CC
2
3
4
5
BB
6
7
8
EE
9
CCO
V
Q0
31
10
Q9
Q1
Q0
30
29
PTN1111
11
12
Q9
Q8
Q1
28
13
Q8
PIN DESCRIPTION
PIN NUMBER SYMBOL NAME AND FUNCTION
1 V
CC
2 CLK_SEL Clock select input
3, 4 CLK0, CLK0 Differential PECL clock input pair
5 V
BB
6, 7 CLK1, CLK1 Differential PECL clock input pair
8 V
9, 16, 25, 32 V
10–15, 17–24,
EE
CCO
Q0:9, Q0:9 Differential PECL output pairs
26–31
Power supply voltage
Voltage reference output
Ground
Output driver power supply
voltages
LOGIC DIAGRAM
CLK0
CLK0
CLK1
CLK1
CLK_SEL
0
1
10
V
BB
Q0:9
ST00012
Q0:9
ORDERING INFORMA TION
TYPE NUMBER
PTN1111BD LQFP32 Plastic low profile quad flat package; 32 leads; body 7 x 7 x 1.4 mm SOT358-1
2001 Jun 19 853-2262 26560
PACKAGE
NAME DESCRIPTION VERSION
2
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