Philips PMWD18UN Technical data

PMWD18UN

	PMWD18UN
M3D647	Dual N-channel μTrenchMOS™ ultra low level FET
	Rev. 02 — 23 February 2004	Product data

1.Product profile

1.1Description

Dual common drain N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOS™ technology.

1.2	Features
	■ Surface mounted package	■ Low profile
	■ Very low threshold	■ Fast switching.
1.3	Applications
	■ Portable appliances	■ PCMCIA cards
	■ Battery management	■ Load switching.
1.4	Quick reference data
	■ VDS ≤ 30 V	■ ID ≤ 7.8 A
	■ Ptot ≤ 2.3 W	■ RDSon ≤ 21.5 mΩ.

2.	Pinning information
Table 1: Pinning - SOT530-1 (TSSOP8), simplified outline and symbol
Pin	Description	Simplified outline		Symbol
1,8	drain (d)
2,3	source1 (s1)	8	5	d	d
4	gate1 (g1)
5	gate2 (g2)
6,7	source2 (s2)			g1 s1 g2	s2
					mbl600
		1	4
		Top view	MBK885

SOT530-1 (TSSOP8)

Philips Semiconductors			PMWD18UN
		Dual N-channel μTrenchMOS™ ultra low level FET
3. Ordering information
Table 2: Ordering information
Type number	Package
	Name	Description		Version
PMWD18UN	TSSOP8	Plastic thin shrink small outline package; 8 leads		SOT530-1

4. Limiting values

Table 3: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol		Parameter	Conditions					Min	Max	Unit
VDS		drain-source voltage (DC)	25 °C ≤ Tj ≤ 150 °C					-	30	V
VDGR		drain-gate voltage (DC)	25 °C ≤ Tj ≤ 150 °C; RGS = 20 kΩ					-	30	V
VGS		gate-source voltage						-	±12	V
ID		drain current (DC)	Tsp = 25			°C; VGS = 4.5 V; Figure 2 and 3	[1]	-	7.8	A
			T	sp	= 100 °C; V = 4.5 V; Figure 2		[1]	-	5	A
						GS
IDM		peak drain current	Tsp = 25			°C; pulsed; tp ≤ 10 μs; Figure 3	[1]	-	32	A
Ptot		total power dissipation	Tsp = 25			°C; Figure 1	[1]	-	2.3	W
Tstg		storage temperature						−55	+150	°C
Tj		junction temperature						−55	+150	°C
Source-drain diode
I	S	source (diode forward) current (DC)	T	sp	= 25	°C	[1]	-	1.9	A
ISM		peak source (diode forward) current	Tsp = 25			°C; pulsed; tp ≤ 10 μs	[1]	-	7.6	A

[1]Single device conducting

9397 750 12706

© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product data

Rev. 02 — 23 February 2004

2 of 12

Philips Semiconductors	PMWD18UN
	Dual N-channel μTrenchMOS™ ultra low level FET

120							03aa17
Pder
(%)
	80
	40
	0
		0		50	100	150	200
							Tsp (°C)
P		=	Ptot
	der		---------------------- × 100%
			P	°C )
			tot (25

Fig 1. Normalized total power dissipation as a function of solder point temperature.

120				03aa25
Ider
(%)
80
40
0
0	50	100	150	200
				Tsp (°C)
VGS ³ 4.5 V

I der	I D
	= ------------------- × 100%
	I D(25	°C )

Fig 2. Normalized continuous drain current as a function of solder point temperature.

102			003aaa258
ID			tp = 10 μs
(A)	Limit RDSon = VDS / ID
10			100 μs
			1 ms
			10 ms
1
	DC		100 ms
10-1			1 s
10-2
10-1	1	10	102
			VDS (V)

Tsp = 25 °C; IDM is single pulse

Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.

9397 750 12706

© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product data

Rev. 02 — 23 February 2004

3 of 12

Philips Semiconductors		PMWD18UN
		Dual N-channel μTrenchMOS™ ultra low level FET
5. Thermal characteristics
Table 4:	Thermal characteristics
Symbol	Parameter	Conditions	Min	Typ	Max	Unit
Rth(j-sp)	thermal resistance from junction to solder point	Figure 4	-	-	55	K/W
Rth(j-a)	thermal resistance from junction to ambient	mounted on a printed-circuit board;	-	100	-	K/W
		minimum footprint

5.1 Transient thermal impedance

102									003aaa259
Zth(j-sp)
(K/W)	δ = 0.5
10	0.2
	0.1
	0.05
	0.02
1									tp
						P
								δ = T
		single pulse
						tp	T		t
10-1
10-4		10-3	10-2	10-1	1	10	t	(s)	102
							p

Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration.

9397 750 12706

© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product data

Rev. 02 — 23 February 2004

4 of 12