Datasheet PMWD18UN Datasheet (Philips)

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PMWD18UN

M3D647

1. Product profile

1.1 Description

1.2 Features

1.3 Applications

Dual N-channel µTrenchMOS™ ultra low level FET

Rev. 02 — 23 February 2004 Product data

Dual common drain N-channel enhancement mode field-effect transistor in a plastic
package using TrenchMOS™ technology.

■ Surface mounted package ■ Low profile

■ Very low threshold ■ Fast switching.

■ Portable appliances ■ PCMCIA cards

■ Battery management ■ Load switching.

1.4 Quick reference data

■ VDS≤ 30 V ■ ID≤ 7.8 A

■ P

≤ 2.3 W ■ R

tot

DSon

2. Pinning information

Table 1: Pinning - SOT530-1 (TSSOP8), simplified outline and symbol

Pin Description Simplified outline Symbol

1,8 drain (d)
2,3 source1 (s1)
4 gate1 (g1)
5 gate2 (g2)
6,7 source2 (s2)

85

14

Top view

SOT530-1 (TSSOP8)

MBK885

≤ 21.5 mΩ.

d

g1s1g

d

s

2

2

mbl600

Philips Semiconductors

PMWD18UN

Dual N-channel µTrenchMOS™ ultra low level FET

3. Ordering information

Table 2: Ordering information

Type number Package

Name Description Version

PMWD18UN TSSOP8 Plastic thin shrink small outline package; 8 leads SOT530-1

4. Limiting values

Table 3: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

V

DS

V

DGR

V

GS

I

D

I

DM

P

tot

T

stg

T

j

Source-drain diode

I

S

I

SM

drain-source voltage (DC) 25 °C ≤ Tj≤ 150 °C - 30 V
drain-gate voltage (DC) 25 °C ≤ Tj≤ 150 °C; RGS=20kΩ -30V
gate-source voltage - ±12 V
drain current (DC) Tsp=25°C; VGS= 4.5 V; Figure 2 and 3

= 100 °C; VGS= 4.5 V; Figure 2

T

sp

peak drain current Tsp=25°C; pulsed; tp≤ 10 µs; Figure 3
total power dissipation Tsp=25°C; Figure 1

[1]

- 7.8 A

[1]

-5A

[1]

-32A

[1]

- 2.3 W
storage temperature −55 +150 °C
junction temperature −55 +150 °C

source (diode forward) current (DC) Tsp=25°C
peak source (diode forward) current Tsp=25°C; pulsed; tp≤ 10 µs

[1]

- 1.9 A

[1]

- 7.6 A

[1] Single device conducting

9397 750 12706

Product data Rev. 02 — 23 February 2004 2 of 12

© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Philips Semiconductors

PMWD18UN

Dual N-channel µTrenchMOS™ ultra low level FET

120

P

der

(%)

80

40

0

0 50 100 150 200

P

tot

P

der

-----------------------

P

tot 25 C°()

100%×=

03aa17

Tsp (°C)

Fig 1. Normalized total power dissipation as a

function of solder point temperature.

120

I

der

(%)

80

40

0

0 50 100 150 200

03aa25

Tsp (°C)

VGS≥ 4.5 V

I

I

der

D

-------------------

I

°

D25C

()

100%×=

Fig 2. Normalized continuous drain current as a

function of solder point temperature.

10

I

D

(A)

10

1

10

10

2

Limit R

-1

-2

-1

10

DSon

= V

DS

/ I

D

DC

1 10 10

tp = 10 µs

100 µs

1 ms
10 ms

100 ms

1 s

VDS (V)

003aaa258

Tsp=25°C; IDMis single pulse

Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.

2

9397 750 12706

© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product data Rev. 02 — 23 February 2004 3 of 12

Philips Semiconductors

PMWD18UN

Dual N-channel µTrenchMOS™ ultra low level FET

5. Thermal characteristics

Table 4: Thermal characteristics

Symbol Parameter Conditions Min Typ Max Unit

R

th(j-sp)

R

th(j-a)

thermal resistance from junction to solder point Figure 4 --55K/W
thermal resistance from junction to ambient mounted on a printed-circuit board;

- 100 - K/W

minimum footprint

5.1 Transient thermal impedance

2

10

Z

th(j-sp)

(K/W)

10

1

10

= 0.5

δ

0.2

0.1

0.05

0.02

P

single pulse

-1

-4

10

-3

10

-2

10

-1

10

1 10 10

δ =

t

p

T

tp (s)

Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration.

003aaa259

t

p

T

t

2

9397 750 12706

© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product data Rev. 02 — 23 February 2004 4 of 12

Philips Semiconductors

PMWD18UN

Dual N-channel µTrenchMOS™ ultra low level FET

6. Characteristics

Table 5: Characteristics

Tj=25°C unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Static characteristics

V

(BR)DSS

V

GS(th)

I

DSS

I

GSS

R

DSon

Dynamic characteristics

Q

g(tot)

Q

gs

Q

gd

C

iss

C

oss

C

rss

t

d(on)

t

r

t

d(off)

t

f

Source-drain diode

V

SD

t

rr

Q

r

drain-source breakdown voltage ID= 250 µA; VGS=0V

=25°C 30--V

T

j

= −55 °C 27--V

T

j

gate-source threshold voltage ID= 1 mA; VDS=V

Figure 9 0.45 0.7 - V

GS;

drain-source leakage current VDS=30V; VGS=0V

=25°C --1µA

T

j

= 150 °C - - 100 µA

T

j

gate-source leakage current VGS= ±10 V; VDS= 0 V - - 100 nA
drain-source on-state resistance VGS= 4.5 V; ID=5A;Figure 7 and 8

=25°C - 18 21.5 mΩ

T

j

= 150 °C - 31 37 mΩ

T

j

= 1.8 V; ID= 4.5 A; Figure 7 and 8 - 2435mΩ

V

GS

= 2.5 V; ID=5A;Figure 7 and 8 - 20 23.5 mΩ

V

GS

total gate charge ID= 4 A; VDD=16V; VGS= 4.5 V; Figure 13 - 24.7 - nC
gate-source charge - 2.2 - nC
gate-drain (Miller) charge - 6.4 - nC
input capacitance VGS=0V; VDS= 16 V; f = 1 MHz; Figure 11 -1526-pF
output capacitance - 210 - pF
reverse transfer capacitance - 160 - pF
turn-on delay time VDD=10V; ID= 1 A; VGS= 4.5 V; RG=6Ω -15-ns
rise time -21-ns
turn-off delay time - 57 - ns
fall time -26-ns

source-drain (diode forward) voltage IS= 5 A; VGS=0V;Figure 12 - 0.87 1.2 V
reverse recovery time IS= 5 A; dIS/dt = −100 A/µs; VR=30V;

=0V

V

recovered charge - 21 - nC

GS

-55-ns

9397 750 12706

Product data Rev. 02 — 23 February 2004 5 of 12

© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Philips Semiconductors

PMWD18UN

Dual N-channel µTrenchMOS™ ultra low level FET

1.2 V

1.1 V
1 V

V

003aaa260

(V)

DS

003aaa262

1.3 V

10

I

D

(A)

8

6

4

2

0

0 0.5 1 1.5 2

=25°C and 150 °C; VDS≥ ID× R

j

Tj = 150 °C

Fig 6. Transfer characteristics: drain current as a

function of gate-source voltage; typical values.

2

a

1.5

5

1.8 V

4

3

2

1

0

4.5 V

0 0.2 0.4 0.6 0.8 1

VGS = 1.3 V

(A)

I

D

Tj=25°CT

Fig 5. Output characteristics: drain current as a

function of drain-source voltage; typical values.

R

(mΩ)

160

DSon

120

1.1 V

1.2 V

003aaa261

25 °C

VGS (V)

DSon

03aa27

80

40

0

012345

VGS = 1.8 V

2.5 V

4.5 V

ID (A)

Tj=25°C

Fig 7. Drain-source on-state resistance as a function

of drain current; typical values.

9397 750 12706

Fig 8. Normalized drain source on-state resistance

1

0.5

0

-60 0 60 120 180

R

DSon

=

a

----------------------------- -

R

DSon 25°C()

Tj (°C)

factor as a function of junction temperature.

© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product data Rev. 02 — 23 February 2004 6 of 12

Philips Semiconductors

0

1

2

3

4

5

0 0.2 0.4 0.6 0.8 1

25 °C

Tj = 150 °C

PMWD18UN

Dual N-channel µTrenchMOS™ ultra low level FET

1

V

GS(th)

(V)

0.8
typ

0.6

min

0.4

0.2

0

-60 0 60 120 180

ID= 1 mA; VDS=V

GS

03aj65

Tj (°C)

Fig 9. Gate-source threshold voltage as a function of

junction temperature.

10

C

(pF)

4

003aaa263

-3

10

I

D

(A)

-4

10

min typ

-5

10

-6

10

0 0.2 0.4 0.6 0.8 1

03aj64

VGS (V)

Tj=25°C; VDS=5V

Fig 10. Sub-threshold drain current as a function of

gate-source voltage.

003aaa264

I

S

(A)

C

3

10

2

10

10

10 1 10 10

iss

C
C

VDS (V)

oss

rss

2

VSD (V)

VGS= 0 V; f = 1 MHz Tj=25°C and 150 °C; VGS=0V

Fig 11. Input, output and reverse transfer capacitances

as a function of drain-source voltage; typical
values.

Fig 12. Source (diode forward) current as a function of

source-drain (diode forward) voltage; typical
values.

9397 750 12706

Product data Rev. 02 — 23 February 2004 7 of 12

© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Philips Semiconductors

PMWD18UN

Dual N-channel µTrenchMOS™ ultra low level FET

5

V

GS

(V)

4

3

2

1

0

0 102030

003aaa265

QG (nC)

ID= 4 A; VDD=16V

Fig 13. Gate-source voltage as a function of gate charge; typical values.

9397 750 12706

© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product data Rev. 02 — 23 February 2004 8 of 12

Philips Semiconductors

7. Package outline

PMWD18UN

Dual N-channel µTrenchMOS™ ultra low level FET

TSSOP8: plastic thin shrink small outline package; 8 leads; body width 4.4 mm

E

H

E

L

8

y

Z

pin 1 index

D

c

5

A

2

A

1

SOT530-1

A

X

v M

A

(A3)

L

p

A

θ

14

e

DIMENSIONS (mm are the original dimensions)

A

A

UNIT

max.

mm

1.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE

VERSION

SOT530-1 MO-153

1

0.15

0.05

A2A3b

0.95

0.25

0.85

IEC JEDEC JEITA

p

0.30

0.19

w M

b

p

(1)E(2)

ceD

0.20

3.1

0.13

2.9

REFERENCES

Fig 14. SOT530-1 (TSSOP8).

4.5

4.3

2.5 5 mm0

scale

0.65

6.5

6.3

detail X

LH

E

L

0.7

0.5

p

wyv

0.1 0.10.10.94

EUROPEAN

PROJECTION

(1)

Z

0.70

0.35

ISSUE DATE

θ

8°
0°

00-02-24
03-02-18

9397 750 12706

© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product data Rev. 02 — 23 February 2004 9 of 12

Philips Semiconductors

8. Revision history

Table 6: Revision history

Rev Date CPCN Description

02 20040223 - Product data (9397 750 12706)

Modifications:

• Correction to I

• Correction to P

• Correction to R

• Figure 3 and Figure 4 updated.

• Section 3 “Ordering information” added

01 20030204 - Product data (9397 750 10832)

data in Section 1.4 “Quick reference data”

D

, ID, IDM, IS and ISM data in Table 3 “Limiting values”

tot

data in Table 4 “Thermal characteristics”

th(j-sp)

PMWD18UN

Dual N-channel µTrenchMOS™ ultra low level FET

9397 750 12706

Product data Rev. 02 — 23 February 2004 10 of 12

© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Philips Semiconductors

Philips Semiconductors

9. Data sheet status

PMWD18UN

PMWD18UN

Dual N-channel µTrenchMOS™ ultra low level FET

Dual N-channel µTrenchMOS™ ultra low level FET

Level Data sheet status

I Objective data Development This data sheet contains data from the objective specification for product development. Philips

II Preliminary data Qualification This data sheet contains datafromthe preliminary specification. Supplementary data willbepublished

III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the

[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

[1]

Product status

10. Definitions

Short-form specification — The data in a short-form specification is

extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.

Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.

Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.

[2][3]

Definition

Semiconductors reserves the right to change the specification in any manner without notice.

at a later date.PhilipsSemiconductors reserves the right tochangethe specification without notice, in
order to improve the design and supply the best possible product.

right to make changes at anytimeinorderto improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).

customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, andmakes no representationsor warranties thattheseproducts are
free frompatent,copyright, or mask workrightinfringement,unless otherwise
specified.

12. Trademarks

11. Disclaimers

TrenchMOS —is a trademark of Koninklijke Philips Electronics N.V.

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors

Contact information

For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: [e-mail]. Fax: [phone]

© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

9397 750 12706

9397 750 12706

Product data Rev. 02 — 23 February 2004 11 of 12

Product data Rev. 02 — 23 February 2004 11 of 12

© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Philips Semiconductors

Contents

1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.4 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1

2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2

5 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4

5.1 Transient thermal impedance . . . . . . . . . . . . . . 4

6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5

7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9

8 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10

9 Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 11

10 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

11 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

12 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

PMWD18UN

Dual N-channel µTrenchMOS™ ultra low level FET

© Koninklijke Philips Electronics N.V. 2004.
Printed in The Netherlands

All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.

The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.

Date of release: 23 February 2004 Document order number: 9397 750 12706