Philips PMWD18UN Technical data

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PMWD18UN

M3D647

1. Product profile

1.1 Description

1.2 Features

1.3 Applications

Dual N-channel µTrenchMOS™ ultra low level FET

Rev. 02 — 23 February 2004 Product data

Dual common drain N-channel enhancement mode field-effect transistor in a plastic
package using TrenchMOS™ technology.

■ Surface mounted package ■ Low profile

■ Very low threshold ■ Fast switching.

■ Portable appliances ■ PCMCIA cards

■ Battery management ■ Load switching.

1.4 Quick reference data

■ VDS≤ 30 V ■ ID≤ 7.8 A

■ P

≤ 2.3 W ■ R

tot

DSon

2. Pinning information

Table 1: Pinning - SOT530-1 (TSSOP8), simplified outline and symbol

Pin Description Simplified outline Symbol

1,8 drain (d)
2,3 source1 (s1)
4 gate1 (g1)
5 gate2 (g2)
6,7 source2 (s2)

85

14

Top view

SOT530-1 (TSSOP8)

MBK885

≤ 21.5 mΩ.

d

g1s1g

d

s

2

2

mbl600

Philips Semiconductors

PMWD18UN

Dual N-channel µTrenchMOS™ ultra low level FET

3. Ordering information

Table 2: Ordering information

Type number Package

Name Description Version

PMWD18UN TSSOP8 Plastic thin shrink small outline package; 8 leads SOT530-1

4. Limiting values

Table 3: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

V

DS

V

DGR

V

GS

I

D

I

DM

P

tot

T

stg

T

j

Source-drain diode

I

S

I

SM

drain-source voltage (DC) 25 °C ≤ Tj≤ 150 °C - 30 V
drain-gate voltage (DC) 25 °C ≤ Tj≤ 150 °C; RGS=20kΩ -30V
gate-source voltage - ±12 V
drain current (DC) Tsp=25°C; VGS= 4.5 V; Figure 2 and 3

= 100 °C; VGS= 4.5 V; Figure 2

T

sp

peak drain current Tsp=25°C; pulsed; tp≤ 10 µs; Figure 3
total power dissipation Tsp=25°C; Figure 1

[1]

- 7.8 A

[1]

-5A

[1]

-32A

[1]

- 2.3 W
storage temperature −55 +150 °C
junction temperature −55 +150 °C

source (diode forward) current (DC) Tsp=25°C
peak source (diode forward) current Tsp=25°C; pulsed; tp≤ 10 µs

[1]

- 1.9 A

[1]

- 7.6 A

[1] Single device conducting

9397 750 12706

Product data Rev. 02 — 23 February 2004 2 of 12

© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Philips Semiconductors

PMWD18UN

Dual N-channel µTrenchMOS™ ultra low level FET

120

P

der

(%)

80

40

0

0 50 100 150 200

P

tot

P

der

-----------------------

P

tot 25 C°()

100%×=

03aa17

Tsp (°C)

Fig 1. Normalized total power dissipation as a

function of solder point temperature.

120

I

der

(%)

80

40

0

0 50 100 150 200

03aa25

Tsp (°C)

VGS≥ 4.5 V

I

I

der

D

-------------------

I

°

D25C

()

100%×=

Fig 2. Normalized continuous drain current as a

function of solder point temperature.

10

I

D

(A)

10

1

10

10

2

Limit R

-1

-2

-1

10

DSon

= V

DS

/ I

D

DC

1 10 10

tp = 10 µs

100 µs

1 ms
10 ms

100 ms

1 s

VDS (V)

003aaa258

Tsp=25°C; IDMis single pulse

Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.

2

9397 750 12706

© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product data Rev. 02 — 23 February 2004 3 of 12

Philips Semiconductors

PMWD18UN

Dual N-channel µTrenchMOS™ ultra low level FET

5. Thermal characteristics

Table 4: Thermal characteristics

Symbol Parameter Conditions Min Typ Max Unit

R

th(j-sp)

R

th(j-a)

thermal resistance from junction to solder point Figure 4 --55K/W
thermal resistance from junction to ambient mounted on a printed-circuit board;

- 100 - K/W

minimum footprint

5.1 Transient thermal impedance

2

10

Z

th(j-sp)

(K/W)

10

1

10

= 0.5

δ

0.2

0.1

0.05

0.02

P

single pulse

-1

-4

10

-3

10

-2

10

-1

10

1 10 10

δ =

t

p

T

tp (s)

Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration.

003aaa259

t

p

T

t

2

9397 750 12706

© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product data Rev. 02 — 23 February 2004 4 of 12