Philips PMGD8000LN Technical data
MBD128
1. Description
2. Features
PMGD8000LN
Dual µTrenchMOS™ logic level FET
Rev. 01 — 27 February 2003 Product data
Dual N-channel enhancement mode field-effect transistor in a plastic package using
TrenchMOS™ technology.
Product availability:
PMGD8000LN in SOT363 (SC-88).
■ TrenchMOS™ technology
■ Very fast switching
■ Logic level compatible
■ Subminiature surface mount package.
3. Applications
■ Battery management
■ High-speed switch
■ Low power DC-to-DC converter.
4. Pinning information
Table 1: Pinning - SOT363 (SC-88), simplified outline and symbol
Pin Description Simplified outline Symbol
1 source (s1)
2 gate (g1)
3 drain (d2)
4 source (s2)
5 gate (g2)
6 drain (d1)
654
123
Top view
SOT363 (SC-88)
MSA370
d
1
s
1
g1s
d
2
2
g
MSD901
2
Philips Semiconductors
PMGD8000LN
Dual µTrenchMOS™ logic level FET
5. Quick reference data
Table 2: Quick reference data
Symbol Parameter Conditions Typ Max Unit
V
I
D
P
T
R
DS
tot
j
DSon
drain-source voltage (DC) 25 °C ≤Tj150 °C - 30 V
drain current (DC) T
total power dissipation T
=25°C; VGS= 4 V - 125 mA
amb
=25°C - 0.2 W
amb
junction temperature - 150 °C
drain-source on-state resistance VGS=4V; ID=10mA 1.8 8 Ω
= 2.5 V; ID= 1 mA 2.9 13 Ω
V
GS
6. Limiting values
Table 3: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DS
V
GS
I
D
I
DM
P
tot
T
stg
T
j
Source-drain diode
I
S
drain-source voltage (DC) 25 °C ≤ Tj150 °C - 30 V
gate-source voltage (DC) - ±15 V
drain current (DC) T
peak drain current T
total power dissipation T
=25°C; VGS=4V;Figure 2 and 3 - 125 mA
amb
=70°C; VGS=4V;Figure 2 - 100 mA
T
amb
=25°C; pulsed; tp≤ 10 µs; Figure 3 - 250 mA
amb
=25°C; Figure 1 - 0.2 W
amb
storage temperature −55 +150 °C
junction temperature −55 +150 °C
source (diode forward) current (DC) T
=25°C - 125 mA
amb
9397 750 10939
Product data Rev. 01 — 27 February 2003 2 of 12
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Philips Semiconductors
PMGD8000LN
Dual µTrenchMOS™ logic level FET
T
amb
03aa11
(°C)
120
P
der
(%)
80
40
0
0 50 100 150 200
P
P
der
tot
----------------------
P
tot 25 C°()
100%×= I
Fig 1. Normalized total power dissipation as a
function of ambient temperature.
1
T
amb
03aa19
(°C)
120
I
der
(%)
80
40
0
0 50 100 150 200
I
D
der
------------------ -
I
D25C°()
100%×=
Fig 2. Normalized continuous drain current as a
function of ambient temperature.
03ah13
I
(A)
T
D
10
10
10
amb
Limit R
-1
-2
-3
1 10 10
DSon
= V
DS
/ I
D
DC
tp = 10 µs
1 ms
10 ms
100 ms
VDS (V)
=25°C; IDMis single pulse; VGS=4V.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
2
9397 750 10939
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data Rev. 01 — 27 February 2003 3 of 12
Philips Semiconductors
PMGD8000LN
Dual µTrenchMOS™ logic level FET
7. Thermal characteristics
Table 4: Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
R
th(j-a)
thermal resistance from junction to ambient minimum footprint; mounted on a PCB;
vertical in still air
7.1 Transient thermal impedance
- - 625 K/W
3
10
Z
th(j-a)
(K/W)
T
10
10
amb
2
-4
10
=25°C
= 0.5
δ
0.2
0.1
0.05
0.02
single pulse
-3
10
-2
10
-1
10
1 10 10
Fig 4. Transient thermal impedance from junction to ambient as a function of pulse duration.
tp (s)
03ah12
2
9397 750 10939
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data Rev. 01 — 27 February 2003 4 of 12
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