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PM3310

Philips PM3310 Service and user manual

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Page 1

Digital storage oscilloscope PM3310

Service manual

9499 445 00711 811215

PHILIPS

Page 2

Operating Manual PM3310

Ordering number: 9499 440 21601

  • Tab 1. Operating Manual
  • Tab 2. Bedienungs Anleitung
  • Tab 3. Notice d'Emploi

PM3325 I.E.C. Bus Operating Manual

Service Manual PM3310

  • Tab 4. Service Manual
  • Tab 5. Modifications
  • Tab 6. Circuit Descriptions
  • Tab 7. Dismantling the Instrument
  • Tab 8. Checking and Adjusting
  • Tab 9. Corrective Maintenance
  • Tab 10. Introduction to Microprocessors
  • Tab 11. Explanation of used Symbols
  • Tab 12. Parts Lists

Additional Diagrams

Page 3

4

GENERAL INFORMATION

4.1. INTRODUCTION

The PM 3310 Digital Storage Oscilloscope is a portable, two-channel 60 MHz measuring instrument featuring micro-processor controlled electronic circuits.

A compact ergonomic design facilitates the extensive measuring capabilities of the instrument. The versatile circuit arrangement combined with the software of the micro-processor gives a wide range of facilities, including:

  • Brilliant display.
  • Pre-trigger view.
  • Storage of two channels with four different "event" signals per channel.
  • IEC-bus optional (with the aid of PM 3325).
  • Plotter output.
  • Trigger delay.
  • Memory back-up (batteries not included).

Furthermore, a large 8 cm x 10 cm screen with illuminated graticule lines provides for easier viewing, a 10 kV accelerating potential giving a high-intensity trace with a well-defined spot.

The oscilloscope is provided with numerous integrated circuits, which ensure stable operation and reduce the number of adjusting points.

The supply voltage can be set to one of two ranges: 100 ... 120 V ± 10 % or 220 ... 240 V ± 10 %. As a result of the features listed above, the oscilloscope is suitable for a wide range of applications, for example the measurement and observation of:

  • Rise-time (gives brilliant display intensity).
  • Fast signals with a very low repetition rate.
  • Very low frequency signals (up to 1 hour per division).

Fig. 1.1. 60 MHz Digital storage oscilloscope PM 3310

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4.2. CHARACTERISTICS

This instrument has been designed and tested in accordance with IEC Publication 348 for Class 1 instruments and has been supplied in a safe condition. The present Instruction Manual contains information and warnings that shall be followed by the purchaser to ensure safe operation and to retain the instrument in a safe condition.

  • This specification is valid after the instrument has warmed up for 30 minutes (reference temperature 23 °C).
  • Properties expressed in numerical values with tolerance stated, are guaranteed by the manufacturer. Numerical values without tolerances are typical and represent the characteristics of an average instrument.
  • Inaccuracies (absolute or in %) relate to the indicated reference value.
signation Specification Additional information
C.R.T.
Cathode ray tube D14 - 292 GH/39
Accelerating voltage 10 kV
Screen size 8 × 10 cm Metal backed
Phosphor type P31 (GH)
Graticule Internal With centimeter divisions and 2 mm
subdivisions along the central vertica
axis shorter 2 mm divisions along the
second, fourth, sixth and eight hori-
zontal axis.
Graticule illumination Clearly visible under normal
light conditions and
continuously variable
Trace rotation Front panel screwdriver
adjustment
Focus Adjusted automatically
Input vertical
Frequency range d.c. 0 60 MHz
a.c. 10 Hz 60 MHz
Rise-time < 6 ns
Pulse aberrations ± 3 % Measured in Y-expand with a
test pulse of 8 div; rise-time
1 ns; frequency 1 MHz (except
first 0.2 cm measured from
mid pulse)
Vertical deflection
Defl. coeff. 10 mV/div 50 V/div 12 Calibrated positions in
1-2-5 sequence
Error limit ± 3 % ±5 % in Y - expand
Continuous control range 1:>2.5
Input impedance 1 MΩ // 25 pF
Coupling a.c 0 - d.c.
Max, perm, input voltage ± 400 V d.c. + a.c. peak
Input selection A only
B only
Add
A and B 		Channel B can be inverted
Page 5
C.M.R.R. 100 : 1 At 2 MHz max. common
mode signal 8 div.
Dynamic range 2x voltage range
DC offset ± 4x voltage range
Max. sample rate 50 MHz
Visible signal delay > 10 ns See also "delay"
Time-base
Time coefficients
Repetitive only 5 ns 0.2 µs/div
Direct 0.5 μs 0.2 s/div
Roll 0.5 s 60 min/div
Coefficient error < 2 % 4% combined with delay in
Resolution 25 samples/div "REPETITIVE ONLY"
Triggering
Source А
В
EXT
EXT: IO
Line
Sensitivity
Internal 0.3 div at 60 MHz
0.15 div at 40 MHz
External 0.3 V at 60 MHz
at 40 MHz
F 0.15 V
3 V
1.5 V 		at 40 MHz
Slope +/
Modes Auto 20 Hz 60 MHz
d.c. dc 60 MHz
a.c. 10 Hz 60 MHz
TV-frame (1/1 picture) Acc. to CCIR (625 lines)
Level
Auto Proportional to peak-to-peak value of trigger signal
a.c./d.c. ± 3 div
Delay
Range −9 +9999 div
0 100 div 		0.2 s 0.5 µs/div
0.2 µs 5 ns/div
Accuracy ±2 mm or 0.01 % 0.2 s 0.5 μs/div
±2 div + visible delay 0.2 μs 5 – ns/div
Input impedance 1 MΩ // 25 pF
Max, input voltage ± 400 V dc + ac peak
Page 6

Memory

1.1

Number of memories 4 1 accumulator memor
Resolution horizontal 1:250 In single trace mode
Resolution vertical 1:250
Operation modes
Single Refreshment of accumulator mem.
takes place, when trigger level is
reached and time set with trigger
delay has been passed. Signal is
stored according to position of
trigger delay. During waiting
time accumulator, is displayed
and LED "NOT TRIG'D" lights
up. 		0.5 μs 0.2 s/div
Recurrent Signal in accumulator memory
is displayed on the screen.
After the time set with the
trigger delay the memory is over-
written by new information. 		5 ns 0.2 s/div
Roll Signal is built-up point by
point at the right-hand side of
the screen and moves to the
left. When accumulator is
completely filled, information
is placed in register 3, next
in 2, then in 1 and next in 		0.5 s 60 min/div

accumulator After this rollmode stops, indicated by flashing "RUN" light.

4 times single with "SAVE" in

Multiple

Display modes

X-Y selection

Memory Covers 2 div. screen height Channel display combinations Accumulator Depends on input selection Register Information as stored in accumulator can be selected for storage in each of the three register memories and is displayed if display button is depressed. ±8 div Vertical position range Vertical expand 5 x 1:>2.5 Horizontal expand

memories

Deflection in X-direction can be derived from time base or from memory contents derived from A-innut

Memory covers 10 cm screen height. Indicated via LED in

Total information held in STORE 1, 2 or 3 can be

display section.

Continuous

inverted

0.5 us 0.2 s/div

memory and

Page 7

Memory modes

Clear

Save (3x)

Write

Lock Pushbutton

1 V / full scale

1 V / full scale

Dot join

Plot output Horizontal Vertical

Pen lift

Plot time Plot sequer

Interfaces

IEC-Bus

IEC-Bus

Local/Rem

X-Y Display

Y f(t) Y f(x) Bandwidth Accuracy Phase diffe

Position

Calibration

Frequency Voltage

Power supp

Line voltag Line freque

Power cons

Accumulator memory is

Contents of accumulator memory are stored in selected

Input signal can be written in accumulator memory

Memory system is closed

Changes normal display mode (dot-join) into display

cleared

register

of only dots.

TTL comp.
''0'' = unblanked (pen down)
''1'' = blanked (pen up) 		open collector output
max. load 0,5V at 500 mA cont.
approx. 100 s.
се B plot after A plot
Optional by means of a plug-in p.c. board
Settings and output controllable from bus-line controller
ote With IEC connector.
y
From time-base
From YA input Dot join is not in operation
See YA
< 5 % Tube included
rence Distance between signal derived from A and signal derived from B is 1/25 div.
0 of stored A signal will be at centre of screen
output
2.5 kHz
3 V
6 mA
lγ
е 100 120 V ± 10 %
220 240 V ± 10 %
ency 50 400 Hz ± 10 %
umption <65 W
Page 8
Dallery
Function For memory back-up only
Түре 2 pen light batteries of 1.5 V For instance
2 x 1.5 V Lithium SAFT
Insulation The insulation of the power
supply fulfils the safety
requirements of IEC 348 cl. I
for metal-encased instruments 		2 x 1.5 V Duracell
Environmental characteristics

Note: The characteristics are valid only if the instrument is checked in accordance with the official checking procedure. Details on these procedures and failure criteria are supplied on request by the PHILIPS-organisation in your country, or by N.V. PHILIPS' GLOEILAMPENFABRIEKEN, TEST AND MEASURING DEPARTMENT, EINDHOVEN, THE NETHERLANDS.

Ambient temperature + 5 °C +40 °C
10 °C +40 °C
55 °C +75 °C 		Rated range of use
Operating temperature range
Storage temperature in accor-
dance with MIL 28800 and a
maximum at 24 hours on
high and low temperature
Altitude
Operating 5000 m (15000 ft) In accordance with
Non-operating 15000 m (50000 ft) 🛛 IEC 68-2-13 test M
Humidity Acc. IEC 68 Db Instrument withstands 95 %
RH over a temperature cycle
of 25 o C to 40 o C
(non-operating)
Shock 30 m/s 2 Operating; half sine-wave
shock of 11 ms duration;
3 shocks per direction for a
total of 18 shocks.
Vibration 3 m/s 2 Operating; vibrations in three
directions with a maximum of
20 min. per direction;
10 minutes with a frequency
of 5 - 25 Hz and amplitude
of 1.016 mm p-p; 10 min
with a frequency of 25 - 55 Hz
and an amplitude of 0.5 mm
p-p. An extra 10 minutes of
the resonant of frequency
with the highest rise in ampli-
tude. Unit mounted on vibra-
tion table without shock
absorbing material.
Dimensions Length 460mm
Width 316mm
Height 154mm 		Handle and controls excluded
Handle excluded
Feet excluded
See also Fig. 1.2.
Weight Approx. 12 kg

4.6

D .

Page 9

CONTENTS

6. CIRCUIT DESCRIPTIONS 6-5
6.1. Blockdiagram description 6-5
6.1.1. Acquisition 6-5
6.1.1.1. The vertical channels 6-14
6.1.1.2. The analog to digital converter 6-14
6.1.1.3. Trigger and delay 6-16
6.1.1.4. The sampling system 6-16
6.1.1.5. The time-base system 6-17
6.1.1.6. The acquisition control 6-17
6.1.2. Display system 6-18
6.1.2.1. Memories 6-18
6.1.2.2. Dot join and plot 6-18
6.1.2.3. Vertical final amplifier 6-19
6.1.2.4. Horizontal final amplifier 6-19
6.1.2.5. C.R.T. section 6-19
6.1.2.6. Alphanumeric display 6-20
6.1.3. Microprocessor 6-20
6.1.4. Power supply 6-23
6.2. Unit descriptions 6-23
6.2.1. Front side unit A1 6-23
6.2.2. Front unit A2 6-25
6.2.3. Motherboard unit A3 6-44
6.2.4. Microprocessor unit A4 6-45
6.2.5. Spare unit A5 6-60
6.2.6. RAM unit A6 6-61
6.2.7. Buffer unit A7 6-72
6.2.8. Conversion unit A8 6-82
6.2.9. ACL unit A9 6-92
6.2.10. CCD logic unit A10 6-110
6.2.11. P 2 CCD unit A11 6-122
6.2.12. Time-base unit A12 6-135
6.2.13. Delay trigger unit A13 6-147
6.2.14. IEC unit A14 6-156
6.2.15. DC power unit A15 6-157
6.2.16. AC power unit A16 6-166
6.2.17. Rear side unit A17 6-174
6.2.18. Delay line unit A18 6-175
6.2.19. CRT socket A19 6-176
6.2.20. Final ampl. unit A20 6-178
6.2.21. Amplifier unit A21 6-188
6.2.22. Irigger unit A22 6-211
6223 EHL unit A23 6-231
Page 10
_
7. DISMANTLING THE INSTRUMENT 7-1
7.1. Warnings 7-1
7.2. Removing the covers 7-1
7.3. Access to parts for checking and adjusting procedure 7-2
8. CHECKING AND ADJUSTING 8-1
8.1. General information 8 .1
8.1.1. Recommended test equipment 8.2
8.1.2. Preliminary settings 8-3
8.2. Survey of adjusting elements 8-4
8.3. Checking and adjusting procedure 8-8
8.3.1. Power supply 8-8
8.3.2. Cathode - ray - tube circuit 8-9
8.3.3. Pre adjustment P 2 CCD circuit 8-12
8.3.4. Balance adjustments 8-13
8.3.5. Final amplifier adjustments 8-15
8.3.6. Vertical channels 8-17
8.3.7. Time coefficient adjustments 8-20
8.3.8. Triggering 8-21
8.3.9. X-Y mode 8-24
8.3.10. Range indication 8-24
8.3.11. Plotter outputs 8-24
8.3.12. Periodic and random deviations 8-24
8.3.13. Effect of mains voltage variations 8-24
8.4. Interactions 8-25
8.5. Performance check 8-29
9. CORRECTIVE MAINTENANCE 9-1
9.1. Replacements 9-1
9.1.1. Replacing single knobs 9-1
9.1.2. Replacing double knobs 9-1
9.1.3. Replacing carrying handle 9-2
9.1.4. Removing the cabinet plates and the screen bezel 9-3
9.1.5. 9-4
9.1.6. Replacing the P 2 CCD unit A11 9-5
9.1.7. Replacing the front unit A2 9-5
9.1.8. Replacing the LEVEL control 9-7
9.1.9. Replacing the trigger mode switch 9-7
9.1.10. Replacing the C.R.L. 9-7
9.1.11. Replacing the delay line unit A18 9-8
9.1.12. Removing the rear plate together with the AC POWER UNIT ATE 9-8
9.1.13. Removing the DUPOWER UNIT A15 9-8
0 0
9.1.14. Removing the mains filter 9-0
00
9.1.15. Removing the Enti Unit A23 9-0
0.0
9.1.16.
9.1.17. 		Removing the vertical amplifier unit A21
Removing the trigger unit A22 		9-8
9-8
0.2 Soldering techniques 0_0
9.2.
Q 3 		Handling MOS devices 0.10
A 4 - A 4 - 0.10

Special tools

Recalibration after repair

Instrument repackaging

Trouble shooting

9.4. 9.5.

9.6.

9.7.

8.8 8-8 8-9 8-12 8-13 8-15 8-17 8-20 8-20 8-24

9-10

9-11

9-12

9-12

9-13

6.2

Page 11
9.7.1. Introduction 9-13
9.7.2. Power-up routine 9-13
9.7.3. Trouble shooting aids 9-15
9.7.4. Service faultfinding software routines 9-15
9.7.5. Trouble shooting hints
9.7.6. Overal view of provisions and service methods 9-20
9.7.7. Checks after repair and maintenance 9-26
10. INTRODUCTION TO MICROPROCESSOR'S 10-1
10.1 A brief encounter 10-1
10.1. Coming to terms 10.1
10.2. System features 10-4
10.0. eyeten reaction 10 1
11. EXPLANATION OF USED SYMBOLS 11-1
12. PARTS LISTS 12-1
(Subject to alteration without notice)
12.2
12.1. Mechanical parts 12-2
12.2. Electrical parts 12:0
13 ADDITIONAL DIAGRAMS 13-2
Page 12

6. CIRCUIT DESCRIPTIONS

6.1. BLOCK DIAGRAM DESCRIPTION

This chapter serves to explain the main functions of the oscilloscope. The working principle is divided into four sections:

  • 6.1.1. Acquisition system
  • 6.1.2. Display system
  • 6.1.3. Microprocessor and software
  • 6.1.4. Power supply

6.1.1. Acquisition system

By means of the acquisition system the analog input signals are converted into digital information. Before conversion the analog signals must be adapted so that an Analog to Digital Converter (ADC) is able to convert them. This system can be divided into the following sections:

  • 6.1.1.1. The vertical channels
  • 6.1.1.2. The analog-to-digital convertor (including P2CCD)
  • 6.1.1.3. Trigger and trigger delay circuits
  • 6.1.1.4. The sampling system
  • 6.1.1.5. The time base system
  • 6.1.1.6. The acquisition control
Page 13

6-10

Fig. 6.1.1.

Page 14

Page 15

Page 16

Page 17

Page 18

6-14

6.1.1.1. The vertical channels (unit A21 page 6-188)

The vertical channel consist of two identical channels A and B except for the possibility B invert. The sensitivity range is 10 mV/div ... 50 V/div in a 1-2-5 sequence.

All front panel settings of the vertical channels except for the CONTINUE an OFFSET controls are read each main loop of the program of the microprocessor system via multiplexers.

After calculation in the microprocessor, the settings are written into the switch setting decoding. This decoding generates the signals to set the ac/dc coupling, the high and low ohmic attenuators and the amplifier gain according to the front panel settings. Moreover these settings can be determined by the IEC Bus interface option The input signal is applied to the channel switch via the ac/dc coupling, the high ohmic attenuator, the impedance convertor, the low ohmic attenuator and the amplifier.

Just after the amplifier a zero in signal NULIN for P2CCD-mode operation is applied to the channel switch. For time base settings of 3600 s/div. 0.5ms/div - and 0.2 µs/div - 5 ns/div the channel switch connects the signal to the delay line.

In dual channel mode (A and B) the microprocessor system generates via the switch setting decoding the signals A ON and B ON in such a way, that a chopped signal is applied to the delay line. The output of the delay line is connected to a compensation network to correct the faults introduced by the delay line.

6.1.1.2. The analog-to-digital convertor (including P2CCD) (unit A10 + A11 page 6-110 and page 6-122).

The output signal of the delay line is applied to the T&H (Track and Hold) gate via a subtractor. This T&H gate tracks the input signal continuously and at a command TANDH its output is held to the momentary value of the input signal for about 4 µseconds. The signal TANDH is generated on the trigger unit and will be described later. Via a low frequency amplifier and a multiplexer the output signal of the T&H gate is applied to the sample and hold gate of an ADC in which the output signal of the T&H gate is taken over and held to the same value for at least the conversion time.

The ADC is controlled by the signals TRACK and CLADC which are generated at the Acquisition Control Logic A9 (ACL).

To eliminate faults of the ADC conversion a correction takes place.

In ROLL, DIRECT and SAMPLING (see operating manual and chapter 6.1.1.6.) mode the correction functions as follows:

Page 19

To reduce errors in conversion, analog samples for digitising are compared with preceding samples, these being subtracted so that only small increments are converted to digital values in the ADC. After conversion, the digital equivalent of the original analog signal is produced by adding the differential signal from the ADC to the digital value of the preceding sample.

Referring to the block diagram, Mn is the new sample of the input signal from the acquisition system; Mn-1 is the preceding sample, derived from the shift register and re-converted by DAC M-1 to analog form. At the input to the Track and Hold circuit, Mn-1 is subtracted from Mn to produce a differential analog voltage, which is then converted to digital form in the ADC and added to the preceding digital value Mn-1.

After this procedure, the adder output value Mn will be shifted into a shift register as a new and corrected value. This system of digital adding is also used, in a different way, in the P2CCD-mode as described below.

For time base settings of 0.2 ms/div - 0.5 µs/div the instrument operates in P2CCD mode. P2CCD means Profiled Peristaltic Charge Coupled Device in which an input signal can be written-in at a high speed and afterwards can be read out at a low speed.

If the instrument operates in P2CCD mode, the output of the channel selector is applied to the input amplifier of the P2CCD. Because of the principle of the P2CCD in dual channel mode the signals – A and + B are applied as P AMP OUT 1 and P AMP OUT 2 resp. The P2CCD contents is read out by a 78 kHz signal and written in by a Time Base Fast (TBF) pulse via the clock driver input logic. The output of the P2CCD is amplified and applied to a multiplexer which switches between the two P2CCD outputs. So in the P2CCD mode the chopper switch of the channel switch is inoperative.

Output VOUT of the multiplexer is applied to the sample and hold gate of the ADC.

Due to internal P2CCD faults and differences between the frequencies fin and fout, an incorrect zero level of the P2CCD output signal is possible as shown in the following graph.

Fig. 6.1.3. P2CCD output signal with shifting zero level

Under these conditions, the total faulty contents of the P2CCD are converted from analog form to digital in 256 steps and after each conversion the data is put on the ADCBØ ... ADCB8 bus and directly shifted into the 9-bit shift register on buffer unit A7. After 256 steps, the total P2CCD contents are stored here, and the register is then blocked.

In order to correct the zero level, the P2CCD input is switched to zero by a signal NULIN and 256 samples of this zero signal are shifted into the P2CCD at the same frequency fin as for the normal input signal.

Page 20

By reading the P2CCD contents again, with the same frequency fout (78 kHz) as for the faulty ADC input signal, an incorrect zero level having the same errors as described above will appear on the P2CCD output as shown below.

Fig. 6.1.4.

This incorrect zero level is then digitally subtracted (in 256 steps) from the faulty ADC input signal, which was already stored in the shift register.

The corrected result is then re-stored in the shift register.

6.1.1.3. Trigger and trigger delay circuits (unit A22 page 6–211)

In the trigger channel a signal derived from one of the sources A, B, external or line is applied to the AC/DC switch. The output of this switch is applied to the automatic level circuit which determines the peak-peak value. If automatic triggering is selected the peak-peak value is applied to the level potentiometer to obtain the possibility to level over the complete signal.

In the modes AC or DC a constant voltage is applied to the level potentiometer. In TVF mode the same voltage is applied to both sides of the potentiometer so that leveling is inoperative.

The slope determines which voltage is selected; positive or negative peak voltage.

After amplification the slope is selected and the trigger signal is applied to the pulse stretcher. The TV path in parallel applies its output signal also to the pulse stretcher.

If the TV signal contains equalisation pulses there is a selection to odd or even frame pulses. Otherwise only frame pulses are available at the output.

The pulse stretcher output signal is applied to two circuits: the sampling circuit and the trigger delay circuit. The trigger delay circuit contains a down counter of which the loading is effected by the microprocessor system via an output port with a value derived from the front panel settings in combination with the TIME/DIV switch setting. Upon the receipt of a trigger pulse from the trigger circuit the down-counter starts counting time base pulses (see also 6.1.1.5.) until its zero state is reached. This effects in a pulse which blocks the reading of new information in the shift register. After this the shift register contents can be copied in the ACCU memory.

6.1.1.4. The sampling system (unit A22 page 6–211)

In sampling mode the output of the pulse stretcher is controlling the fast ramp generator. The ramp is determined by the TIME/DIV switch setting via the microprocessor and the control signals LØ ... L2. The fast ramp output is applied to a comparator. At the other input of the comparator a signal DACSTAIR is applied which is a stair case voltage derived from the ACL counter that increases one step every time that a conversion is completed and a COUNT pulse is counted by the ACL counter. To this staircase voltage a voltage called DACDEL is added which is derived from the trigger delay unit. This is a voltage proportional to the preset trigger delay.

If now the fast ramp voltage reaches the same potential as the sum of DACDEL and DACSTAIR, the system generates a HOCON (Hold and convert) and a TANDH (Track and hold) pulse to start an analog to digital conversion. If a conversion is completed the output of the pulse stretcher is enabled to generate via the fast ramp generator a new HOCONDRS pulse to start the next conversion. Now the DACSTAIR signal will be increased one stair level so this conversion takes place at the following point of the repetitive input signal.

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6 1 1 5 The time base system (unit A12 page 6-135)

With respect to an ordinary oscilloscope this digital storage oscilloscope does not need a sawtooth time base generator because the position on the screen is determined digitally.

Therefore the time-base system consists mainly of frequency dividers.

The base frequency is 2.5 MHz derived from the cristal clock frequency of the microprocessor system. Because the need of higher frequencies then 2.5 MHz a voltage controlled oscillator is introduced with a frequency of 100 MHz. This frequency is kept stable by dividing it by a factor of 80 and to compare it with the microprocessor clockpulse divided by a factor of 2. Now both signals have a frequency of 1.25 MHz and via a feedback loop the VCO is controlled.

For the P2CCD mode a TBF signal is generated and in DIRECT and ROLL mode a TBS signal.

The dividing factors, so the frequencies of the TBF and TBS signals, are determined by the setting of the TIME/DIV switch which is decoded by the time base setting decoding.

The frequency of the TBF and TBS signals is such that for one horizontally division on the screen exactly 25 TBF or TBS periods are generated.

6,1.1.6. The acquisition control (unit A9 page 6–92)

The most important part of the acquisition control is a counter which counts the number of conversions by counting COUNT pulses.

Each conversion is initiated by a HOCON (hold and convert pulse) and results after completion into a COUNT pulse.

So it is counting how many input values are written into the shift register.

The acquisition control is operating in a different way for each of the four system modes DIRECT (D) - ROLL (R) - SAMPLING (S) and P2CCD (P).

In each of these four modes NDR (New Data Ready) pulses are generated to indicate to the microprocessor that new data is ready and can be copied in the ACCU memory.

The microprocessor in turn answers with SOD pulses telling that the copying of new information into the ACCU memory is completed and that new information can be stored in the shift register.

Direct mode

After a hold-off period in which at least 256 new input signal samples are shifted into the shift register, so after a total refreshment of the shift register contents the acquisition system is enabled to react on a new trigger pulse.

Upon the receipt of such a trigger pulse a NDR pulse will be generated just after the completion of the last conversion.

ROLL-mode

The ROLL-mode action is started when ROLL-mode is selected and the front panel R/S pushbutton is depressed. This results in the generation of TBS pulses by the time-base unit. These TBS pulses are converted by the trigger unit in HOCONDRS (Hold and convert) pulses which are used in the ACL unit to initiate the conversions of new input signal samples.

After each completed conversion a COUNT pulse is generated and so a NDR pulse.

On each NDR pulse the total shift register contents are copied into the RAM memory and in the same time the shift register output information is shifted again into this shift register by coupling the output of the shift register directly to its input.

Furthermore ROLL-mode functions are under the control of the software.

The software counts the number of NDR pulses and after 256 NDR pulses it saves the ACCU contents into STO3, after again 256 pulses into STO2, then into STO1. After in total 4 x 256 pulses the software stops the ROLL-mode action and indicates this by generating a flashing command for the RUN lamp.

Sampling mode

In sampling mode a HOCONDRS pulse is generated on each incoming TRIST pulse except for those coming within the hold-off period. These HOCONDRS pulses initiate conversions of the input signal samples. After 256 samples are converted and stored in the shift register a NDR pulse is generated and the shift register contents are copied into the ACCU memory.

The microprocessor generates a SOD signal after this copying, the ACL counter is reset to zero and the system reacts again on new incoming triggers.

Page 22
P2CCD-mode

After reading in at least 256 samples of new input information into the P2CCD circuit, these samples are read out, converted and shifted into the shift register.

Then for a period of about 5 ms zero information will be shifted into the P2CCD, controlled by the signal NUL IN from the ACL unit which is active in the vertical channels (see also 6.1.1.1.).

These zero information is then read out and corrected (see also 6.1.1.2.) with the 256 samples of signal information which was already stored in the shift register and the corrected information is shifted again in the shift register. This total procedure results then in a NDR pulse and copying of shift register contents into the ACCU memory can be started.

6.1.2. Display system

The display part consists of hardware to store and display data on the CRT display. Moreover this part arranges the coding for information to be displayed on pilot and control lamps and on the alphanumeric display. This chapter can be divided in:

6.1.2.1. Memories 6.1.2.2. Dot join and plot 6.1.2.3. Vertical amplifier 6.1.2.4. Horizontal amplifier 6.1.2.5. CRT section 6.1.2.6. Alphanumeric display

6.1.2.1. Memories (unit A6 page 6-61)

The memories are consisting of four separate parts which can be written and read independently. If from the acquisition control logic the signal New Data Ready arrives, new information is written in the ACCU. This means that the contents of the shift register is copied in the ACCU.

This information is now read out continuously with a speed, determined so that the display on the CRT seams to be steady.

At a "SAVE" command the contents of the ACCU is copied in one or more of the registers STO1...STO3. The registers STO1...STO3 can only copy information from the ACCU. The only other possibility to write in one of the memories STO1...STO3 is with the use of the IEC-bus interface via the databus. The information is stored in the memories as a two-complement notation which means that the data are integers with values from -128 up to and including +127. To convert this in straight binary notation for the YDAC only the most significant bit has to be inverted. After that the complete information can be inverted by operating the push pull knobs "pull to invert". This inversion takes place by an eight-bit-exclusive-or. Via the databus the information can be applied also to the X-DAC. This is necessary in the mode X = A; Y = B.

6.1.2.2. Dot join and plot (unit A20 page 6–178)

If the mode "DOTS" is selected separate dots will appear on the CRT display. The dot join circuit generates straight lines between the consecutively dots. The block diagram of the dot join principle is shown in the figure below.

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In dual channel operation on points 1 and 3 is always the information of one channel. By the control signals AØ and A1 this information is switched to the output of the multiplexer. Suggest A is the oldest information and B the newest, then, the subtractor output is A-B. This voltage controls the variable sawtooth generator of which the ramp is determined so that the B value is reached before a new write pulse arrives. The output of the sawtooth generator is added to the oldest information A and applied to the final amplifier. If the sawtooth generator is reset the CRT display is blanked.

For X-deflection also a sawtooth voltage is generated but now with a fixed ramp and amplitude. The plot action is principally a software matter.

The microprocessor system activates the sample and hold gates for the plots so that every 0.25 sec a new sample is taken. This is visible on the CRT display as an intensified point so it is traceable for how far the plot action is got.

The speedness is choosen in such a way that a simple chart recorder is able to record the information.

6.1.2.3. Vertical amplifier (unit A20 page 6–178)

After the dot join it is possible to magnify the signal 5x. Now it is possible to obtain the contents of the ACCU or STO1 ... STO3 for full screen deflection. In Y x 1 mode for each memory two divisions are available. Midrange of the position controls effects in displaying the memory base lines on the CRT at resp. 1, 3, 5 and 7 cm with respect to the screen top. This offset is switched to zero if the Y x 5 mode is choosen.

Now all base lines of the memories are situated in the centre of the screen.

The final amplifier consists of a long tailed pair which drives the CRT directly. This is possible because of the low bandwidth of 1 MHz.

6.1.2.4. Horizontal amplifier (unit A20 page 6-178)

The horizontal amplifier consists of an integrated circuit for the magnifier adjusting and a final amplifier consisting of two shunted feedback pushpull amplifiers. Position control is effected at the input of the integrated circuit.

6.1.2.5. CRT section (unit A15 page 6–157)

Because of the principle of the CRT it is not necessary to correct the barrel and pin cushion distortion. The cathode current of the CRT as used in the concept of this oscilloscope will never yet very high so that a focus voltage dependent to the intensity setting can be arranged automatically. Now there is no need for a front panel focus control.

The Z-control is arranged by the microprocessor system.

Only if a memory is read the CRT is unblanked.

If via the overflow detection a maximum or a minimum value is exceeded this part is displayed with a frequency of approx. 5 Hz so the display blinks.

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6.1.2.6. Display (unit A2 page 6-25)

There are four front-panel alphanumeric displays:

  • channel A V/DIV display
  • channel B V/DIV display
  • s/DIV display
  • DIV display.

Each of these alphanumeric displays is an intelligent four-digit unit with a built-in CMOS integrated circuit. The integrated circuit contains a memory, an ASCII-character generator, and a LED multiplexing and drive circuit.

The displays are controlled by the microprocessor, each individual display section being selected by means of addresses fed to the ADDRESS-bus by the microprocessor.

The characters that are required to be displayed are generated by the microprocessor system in Standard ASCII character code and are placed on the databus (signals DØ ... D7).

Control and pilot lamps

The NOT TRIG'D, RUN and REMOTE lamps are directly controlled by the signals NOT TRIG'D, RUNL and REM, which are generated on the microprocessor board.

The DISPLAY lamps, the SELECT lamps, the UNCAL A and UNCAL B lamps, the A and B AMPL/DIV control lamps and the TIME/DIV control lamps are controlled by addresses generated by the microprocessor system.

6.1.3. Microprocessor (unit A4 page 6–45)

As shown in the simplified block diagram, the micro-processor unit basically consists of the following circuit elements:

  • A micro-processor integrated circuit block for controlling and organising data flow.
  • Ereasable and programmable read-only memories (EPROMs) for system programming.
  • Random-access memories (RAMs) for stacking and storing the variable data.
  • Address and data selection latches for the multiplexed address bus.
  • Decoders for RAM and ROM selection and address decoding.
  • Trap and watchdog circuits to guard against loss of data
  • Two-way buffer circuit to the system data-bus.
  • A blanking circuit for the c.r.t.

The heart of the microprocessor unit is an 8-bit microprocessor type 8085 with 16 address lines. The first eight address lines AØ ... A7 are multiplexed with the eight data lines DØ ... D7 and are defined as ADØ ... AD7. Addressing is selected by the ALE (address latch enable) signal from the microprocessor, which gives an external indication when address information is on the bus-lines.

Trap Input Circuit

The TRAP input is effective when the battery back-up facility is used. It prevents the RAM contents being disturbed when the instrument is switched off or in the event of a power failure. The TRAP input forces the microprocessor to continue with the execution of the program at the starting address of the POWER DOWN routine. Failure of the power supply activates the TRAP input of the microprocessor.

A 5 MHz crystal, is connected to the clock inputs of the microprocessor to provide an accurate timing reference source.

A reset signal is generated when the instrument is switched ON. This reset signal forces the microprocessor to start the execution of the main program.

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Connection to the system address bus

The first eight address bits placed by the microprocessor on the multiplexed address-data bus lines ADØ ... AD7 have to be separated from the eight data bits. This separation is achieved by an address latch, which is enabled by signal ALE.

The group of output signals AØ ... A7 constitute the system address bus.

Connection to the system data-bus

The eight data bits placed by the microprocessor on the multiplexed address-data bus lines ADØ ... AD7 have to be separated from the first eight address bits.

This separation is done by a bidirectional buffer.

System memory map

ROM memory

The ROM (read-only memory), which contains the system program, consists of the four EPROM chips of 2K-bytes each (2048X 8 bits).

Because the microprocessor's first eight address lines ADØ ... AD7 are multiplexed in the microprocessor with the data lines, the addresses have to be latched by the address latch D416 with the aid of the ALE signal. When a certain ROM address is selected, the contents of the selected location are placed on the multiplexed address-data bus lines ADØ ... AD7.

RAM memory

The µP-RAM (microprocessor random access memory) is used by the microprocessor for stack purposes and for storage of variable data.

It consists of two RAM chips - of ¼K-nibbles each (256 x 4 bits), which means that a maximum of 256 bytes of data can be stored.

Each µP-RAM memory address can be selected by the address lines AØ* ... A7*

Reading the RAM contents or writing data into a RAM location is controlled by the signals RD* and WR*

The data to be written into, or read from the RAM memory is transported via the multiplexed address-data bus ADØ ... AD7.

Blanking circuit

This circuit provides for a blanking signal ZIN (Z-amplifier input) for blanking the trace on the c.r.t. display.

Page 27

6.1.4. Power supply (unit A15 page 6–157 and A16 page 6–166)

The mains voltage is applied via the mains filter and the mains selector switch on the AC POWER UNIT A16 to a rectifier where it is full-wave rectified and fed to a regulated sine-converter (oscillator and switching circuit). The output voltage of the sine converter is kept constant by regulating the duty cycle of the applied voltage by a special integrated circuit.

This output voltage is applied to the primary of a transformer, the secundary voltages of this transformer are applied to DC POWER unit A15 where they are full-wave rectified, smoothed and applied to the various circuits. Also the voltages for the C.R.T. filament and the C.R.T. cathode (-1,5 kV) are generated here. The -1.5 kV is also applied to the EHT unit A23 which gives a high tension for g8 of the C.R.T.

The MAINS triggering is taken direct from the mains and, via an opto-isolator, fed to the trigger circuitry on a safe level.

6.2. UNIT DESCRIPTIONS
6.2.1. Front side unit A1

The front side unit consists of an aluminium front cast on which the following items are mounted.

  • LED B24 + LED-holder
  • Light reflector assembly inclusive two lampholders and two 28 V 80 mA lamps E1 and E2.
  • CAL output terminals X1 and X2.
  • Measuring earth socket X5.
  • BNC input socket X6 for external triggering.
  • LEVEL/SLOPE control R9/S27.
  • INTENS control R15.
  • TRACE ROTATION control R16.
  • Trigger mode selector switch S29.

6-23

MAT 708 A

Page 28

Fig. 6.2.2.

MAT 707A

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6.2.2. Front unit A2

6.2.2.1. Front board A201

The front board houses all the front-panel control lamps, pilot lamps and alphanumeric displays.

Alphanumeric intelligent displays

There are four front-panel alphanumeric displays:

  • channel A V/DIV display
  • channel B V/DIV display
  • s/DIV display
  • DIV display

Each of these alphanumeric displays is an intelligent four-digit unit with a built-in CMOS integrated circuit. The integrated circuit contains a memory, an ASCII-character generator, and a LED multiplexing and drive circuit.

The displays are controlled by the microprocessor, each individual display section being selected by means of addresses fed to the ADDRESS-bus by the microprocessor.

DE CADE AØ A1
Ø 0 0 NA
1 0 1 Ke l
2 1 0 DECADE — ► 3
3 1 1
4 V/L DIV displa ау DECADE CONTROL ADDRESS
Ø 8ØAØ
1 8ØA1
2 8ØA2
3 8ØA3
3 V/L DIV displa ay DECADE CONTROL ADDRESS
0 8ØA4
1 8ØA5
2 8ØA6
3 8ØA7
s/D IV displa v DECADE CONTROL ADDRESS
· 0 8008
1 8040
8044
3 8048
D١ / display DECADE CONTROL ADDRESS
Ø 8ØAC
1 80AD
2 8ØAE
3 80AF

The characters that are required to be displayed are generated by the microprocessor system in Standard ASCII character code and are placed on the data-bus (signals DØ ... D7).

Page 30
1 DO L н L н L н L н
1 D1 L L н н L L н Н
D2 L L L L н н н н
D6 5 D 5 5 D4 D3
L н L L П 뷥 5 労 о
СУ 		1
L н L н < > ₩ ł 1 1
L н н L Û 1 б 3 Ч 5 δ ?
L н н н 8 9 - - 1 7 7
H L L L പ R 3 [] Л E F 5
- L L н Н ľ Ĵ К ! M Ņ []
1 L н L P 0 R 5 Ţ IJ 11 Ы
1 L н н Х Y 7 ſ ] Λ

CHARACTER SET (all other input codes display 'BLANK')

Control and pilot lamps

The NOT TRIG'D, RUN and REMOTE lamps are directly controlled by the signals NOT TRIG'D, RUNL, and REM, which are generated on the microprocessor board.

The DISPLAY lamps (DISØ ... DIS3), the SELECT lamps (SELØ ... SEL3), the UNCAL A and UNCAL B lamps, the A and B AMPL/DIV control lamps LA1, LA1Ø, LB1, LB1Ø and the TIME/DIV control lamps LREC - LROLL are controlled by the addresses 8ØBØ and 8ØB4 as shown in the table in conjunction with the data bits DØ to D7.

ADDRESS D7 D6 D5 D4 D3 D2 D1 DØ
8ØBØ SEL3 SEL2 SEL1 SELØ DIS3 DIS2 DIS1 DISØ
8ØB4 UNCB UNCA LROLL LREC LB1Ø LB1 LA1Ø LA1

Selection of a display segment or a group of pilot lamps or control lamps is achieved by decoder D203. This three-bit decoder decodes the three address-bits A2, A3 and A4 if the input signal combination WR.I0A is active. This results in one active decoder output line at a time.

The IOA signal is an address decoding signal for address lines A5 ... A15 and decodes addresses 80A0 to 80BF.

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INCOMING
SIGNAL 		OUTGOING
SIGNAL 		GENERATED
ON UNIT 		DESCRIPTION
AØ A4
A1 A4
A2 A4 Address bits from system address bus
A3 A4
A4 A4 ļ
DØ A4 1
D1 A4
D2 À4
D3 A4
D4 A4 Data bits from system data-bus
D5 A4
D6 A4
D7 A4 1
NOT TRIG'D A4 Control for NOT TRIG'D lamp
ĪŪĀ A4 Address decoding signal for addresses
80A0H - 80FFH (Display select)
REM A4 Control for REMOTE lamp
RUNL A4 Control for RUN lamp
WR A4 Signal WRITE from microprocessor
+5 V A15 -
A15
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FRONT BOARD A201

ia. 6.2.3.

Page 33

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s/DIV B12 B V/DIV B11 A V/DIV B10 ADDRESS RES A1 -BOAS DADE READ AMAL × × DDRESS

1.5V

B10 B11 B12 B21 12 7

Fig. 6.2.4.

Page 37
Table A
YA1 YA4 YA5 YA6 YAT YA2
D7 06 05 04 D3 D2
- 1 ۰ - ٥ - 10 - nV/d
- - ٥ 0 0 - 20 1 hV/d
- 0 0 ٥ 0 - 50 n P/Au
- 0 0 0 - - 1 V/d
- _ 0 0 - - N V/d
0 - 0 0 0 - 'n V/d
0 - - 0 0 - - V/d
0 - - 0 0 0 2 V/d
0 - 0 - 0 0 cn V/di
- - 0 - 0 0 10
- - -1 0 0 0 20
٥ 0 0 0 50 V/di
A DESCRIPTION OF
YB1 YB4 YB5 YB6 YB7 YB2
D7 D 6 D5 04 D3 D2
- - 0 - • - 10 N/Vn
- - 0 0 0 _ 20 7 nV/o
- 0 0 0 0 - 50 . nV/o
- 0 0 0 - - 4 <
- - 0 0 - _ 2 <
0 - 0 0 0 4 'n <
0 - 0 0 _ <
C _ 0 0 0 2
0 - 0 - 0 0 m
- 0 - 0 0 10 <
- - 0 0 0 20
۰ 0 - 0 0 50
N. 60 min/div - 0 - 0 0
30 min/div. - 0 0 0 0
15 min/div. 0 - 0 0 0 -
b min/civ. - - - 0 c -
• & manuar.
3 min/riu • • 4.
1 min/div. 0 - - - • 0
. 5 min/div. 0 0 _ _ 0
20 s/div. 0 0 - _ 0 0
10 s/div. 0 - 1 _ 0 0
5 s/div. - - _ _ 0 0
2 s/div. 0 0 - 0 0
1 s/div. 0 0 0 _ - -
_] . 5 s/div. 0 0 - 0 - -
١ . 4 3/014. c c ÷ 4 9
2 - 141 - 1
1 s/div 0 0 - 0 -
50 ms/div. - 0 - 0 0
20 ms/div. - - 0 0 0 0
10 ms/div. 0 - 0 0 0 -
5 ms/div, 0 - 4 0 0 -
2 ms/div. 0 - _ 0 0 0
1 ms/div. 0 - - _ - 0
. 5 ms/div. 0 0 - - - 0
. 2 ms/div. 0 0 - - 0 0
. 1 ms/d/v. 0 1 - _ 0 0
50 µs/div. _ - - - 0 0
20 µs/div. _ 0 0 - 0 0
10 µs/div. 0 0 0 - -
5 µs/div. 0 0 - 0 -
2 µs/div. 0 0 - 0 0
1 µs/div. 0 0 0 - - 0
. 5 µs/div. _ 0 0 _ - 0
. 2 µs/div. _ 0 0 0 0
. 1 µs/div. _ - 0 0 - -
50 ns/div. - - 0 0 0 -
20 ns/div. 4 0 0 0 0 -
10 ns/div. - 0 0 0 - -
5 ns/div. - 0 - 0 - -
02 D3 D4 05 06 07
182 T 87 TB6 T85 TB4 TB1
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6.2.2.2. Switchboard A202 and Switch Units A203 ... A207

The front-panel controls listed below are located on these units.

A202 switchboard
SWITCHES Circuit ref. Switch signals
YA AMPL/DIV S20 YA1
YA2
YA4
YA5
YA6
YA7
YB AMPL/DIV S22 YB1
YB2
YB4
YB5
YB6
YB7
TB TIME/DIV $23 TB1
TB2
TB4
TB5
TB5
TB6
TB7
INV STO1 S5 INV1
INV STO2 S6 INV2
INV STO3 S7 INV3
CALA S19 CALA
CALB S21 CALB
INV YB $28 BIN
SERV 1 X241 SERV1
SERV 2 X241 SERV2
POTENTIOMETERS Circuit ref. Slider signals
X POSITION R3 X POS
X MAGN R2 X MAGN
(+12 V in X CAL)
OFFSET A R10/R11 OFF A
OFFSET B R12/R13 OFF B
POS ACCU R1 POSØ
POS STO1 R4 POS1
POS STO2 R5 POS2
POS STO3 R6 POS3
CONT A R7 ACON
CONT B R8 BCON

The slider signals of the above-listed potentiometers are applied to various units of the instrument via connector X259

Page 39
A203 interconnection board

Provides the connection between units S201 and A202.

A204 display switch board
Switch signals
DISPLAY ACCU S1 DISØ
DISPLAY STO1 S2 DIS1
DISPLAY STO2 S3 DIS2
DISPLAY STO3 S4 DIS3
A 205 I delay switch board
UP S24 UP
S25 DIG
DOWN S26 DOWN
A 205 II save switch board
SAVE STO1 S8 SAV1
SAVE STO2 S9 SAV2
SAVE STO3 S10 SAV3
A206 clear switch board 611 CLEAR
511 ULEAN
512A
612B
LUCK 3120 LUCK
A207 select switch board
SELECT S14 SEL
X=t S15A
X=A/Y=B S15B A/B
Yx1 S16A _
Yx5 S16B Yx5
DOTS S17 DOTS
PLOT S18 PLOT

The settings of all the switches on the above units are read periodically by the microprocessor system via three groups of multiplexers, D241/D247, D242/D248, D243/D249 according to the following table:

ADDR ESS AØF D7 D6 D5 D4 D3 D2 D1 DØ
8Ø2Ø RDFØ=Ø 1 YA1 YA4 YA5 YA6 YA7 YA2 DIG CALA
8Ø21 RDFØ=Ø ø YB1 YB4 YB5 YB6 YB7 YB2 BIN CALB
8022 RDF2≃Ø 1 TB1 TB4 TB5 TB6 TB7 TB2 UP DOWN
8023 RDF2=Ø Ø DIS3 DIS2 DIS1 DISØ INV3 INV2 INV1 FRUN
8024 RDF4=Ø 1 +5 V FASA Yx5 SEL SAV3 SAV2 SAV1 DELTRG
8025 RDF4=Ø Ø PLOT ØV DOTS A/B CLEAR LOCK SERV2 SERV1

The selection of one of the multiplexer groups and the internal setting of the selected group is made via the address selector circuit, which consists of NAND-gate D244 (11, 12, 13) and the three-to-eight decoder circuit D246, as shown in the following table:

Page 40
ADDRESS 102 A3 A2 A1 AØ AØF
8020 ø Ø Ø Ø Ø 1
8021 ø Ø Ø Ø 1 Ø
8022 Ø Ø Ø 1 Ø 1
8023 Ø Ø Ø 1 1 Ø
8024 Ø Ø 1 Ø Ø 1
8025 ø Ø 1 Ø 1 Ø
GENERATED DESCRIPTION
JIGNAL SIGNAL ON UNT
AØ A4 A4 Address bits from system address-bus
ACON A202 A21 Slider of channel A continuous control
BCON A202 A21 Slider of channel B continuous control
DØ D7 A4 Data bits from system data-bus
DØ D7 A202 A4 Data bits to system data-bus
DELTRG 1 A13 A9 Delayed trigger signal
FASA A9 Output phase flip-flop
FRUN A13 Freerun signal
102 A4 Input switches select
ĪŌĀ A4 Display select I/O address decoding signals
NOT TRIG'D A4 Control for NOT TRIG D lamp
OFFA A202 A21 Slider of channel A OFFSET control
OFFB A202 A21 Slider of channel B OFFSET control
POSØ A202 A20 Slider of ACCU position control
POS1 A202 A20 Slider of STO1 position control
POS2 A202 A20 Slider of STO2 position control
POS3 A202 A20 Slider of STO3 position control
REM A4 Control for REMOTE lamp
RUNL A4 Control for RUN lamp
RD A4 Signal READ from microprocessor
WR A4 Signal WRITE from microprocessor
XMAG A202 A20 Slider of XMAGN control
XPOS A202 A20 Slider of X POSITION control
+5 V A15
—12 K A15
+12 K A15
—12 L A15
+12 L A15
/ A15
TEST POINTS
X248 DØ
X249 D1
X251 D4
X252 D5
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SWITCH BOARDS

Page 46
6.2.3. Motherboard unit A3

The motherboard unit is installed to interconnect the various plug-in units. No components are mounted on this board.

Fig. 6.2.13.

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1
2 DAC STAIR
3 DAC DEL
5 HOCOURDE 		X 1322 ŢIIZĬĬŶ ŢIJĬĬĮ и и рана
акулана
37 		x 801 x 1002
* 911 x 1401
* 914 x 1401
x 1201
x 1201 		1203
1200, 1200
1200, 1200
1200, 1200 		x 302 د
مېرىيى ( 		21
21 		×101 ×101 >10 1 >10 0
6 3
7
9 Track
10 Frun
10 Frun
11 Track
11 Track
11 Track 		2003
29.1
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20.5
25.5
25.5
20.5
20.1
25.0
20.1
25.0
25.0
25.0
25.0
25.0
25.0
25.0
25.0 		2000
2003
2003
2004
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2005
2005 		x1202
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30-7
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50-02
50-02
50-02
50-02
50-02
50-02
50-02
50-02
50-02
50-02
50-02
50-02
50-02
50-02
50-02
50-02
50-02
50-02
50-02
50-00 		x1211
ye_15v
ye_2
ye_4_
ye_6
ye_6
ye_7_ 		x1011
y2.2
y2.3
y2.3
y2.4
y2.5
y2.6
y2.6
y2.6
y2.6
y2.6
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7
y2.7 		98-1
92-2
92-3
92-6
92-5
92-5
92-5
92-5
92-5
92-7 		x801
20 2
20 2
20 4
20 5
20 6
20 7
20 7 		5701
922
922
923
925
025
025
025
025
025
025
025
025
025
0 		7601
79.2
79.3
79.3
79.5
79.5
79.5
79.5
79.5
79.7
7.5patt 		2501
26.2
36.2
36.4
39.4
30.6
39.5
200
30.6
30.6
30.6
30.6
30.6
30.6
30.6
30 		9.2
9.2
9.4
9.6
9.6
9.6
9.6
9.6
9.7 		88
위재치지대리의어섹시이에지지니
PWH 2
-SBAT(
-SV
-SV
-SV
-SV
-SV
-SV
-SV
-SV 		9 8 9 10 9 11 9 12 9 12 9 14 9 15 9 16 9 17 9 18 9 19 9 221 9 22 9 23 9 24 9 25 9 28 9 20 9 21 9 22 9 23 9 24 9.8
9.9
9.00
9.010
9.012
9.012
9.012
9.014
9.015
9.015
9.015
9.015
9.015
9.015
9.015
9.015
9.015
9.015
9.015
9.015
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.017
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027
9.027 		9.0.0
9.10
9.11
9.12
9.12
9.12
9.12
9.14
Ad
9.15
105
9.16
WB
9.16
WB
9.19
9.22
9.223
1.2949z
9.223
1.2949z
9.225
FaSO
9.226
9.225
FaSO
9.226
9.227
01
9.228
1.2949z
9.228
1.2949z
9.228
1.2949z
9.228
1.2949z
9.228
1.2949z
9.228
1.2949z
9.228
1.2949z
9.228
1.2949z
9.228
1.2949z
9.228
1.2949z
9.228
1.2949z
9.228
1.2949z
9.228
1.2949z
9.228
1.2949z
9.228
1.2949z
9.228
1.2949z
9.228
1.2949z
9.228
1.2949z
1.2949z
1.2949z
9.228
1.2949z
9.228
1.2949z
1.2949z
9.228
1.2949z
1.2949z
9.228
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2947z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2949z
1.2947z
1.2949z
1.2947z
1.2949z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2947z
1.2 		30.8 36.9 36.10 37.11 37.12 37.12 37.13 37.14 37.15 37.17 37.18 37.19 37.10 37.11 37.12 37.12 37.13 37.14 37.15 37.11 37.11 20.8
20.9
20.11
20.12
20.12
20.12
20.12
20.12
20.13
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20.15
20 		0.8
9.9
9.10
9.11
9.12
9.12
9.13
9.15
9.16
9.15
9.15
9.15
9.15
1.15
9.15
9.15
1.15
9.15
1.15
9.15
1.15
9.15
1.15
9.15
1.15
9.15
1.15
9.15
1.15
9.15
1.15
9.15
1.15
9.15
1.15
9.15
1.15
9.15
1.15
9.15
1.15
9.15
1.15
9.15
1.15
9.15
1.15
9.15
1.15
9.15
1.15
9.15
1.15
9.15
1.15
9.15
1.15
9.15
1.15
9.215
1.15
9.215
1.15
9.215
1.15
9.215
1.15
9.215
1.15
9.215
1.15
9.215
1.15
9.215
1.15
9.215
1.15
9.215
1.15
9.215
1.15
9.215
1.15
9.215
1.15
9.215
1.15
9.215
1.15
9.215
1.15
9.215
1.15
9.215
1.15
9.215
1.15
9.215
1.15
9.215
1.15
9.215
1.15
9.25
1.15
9.25
1.15
9.25
1.15
9.25
1.15
9.25
1.15
9.25
1.15
9.25
1.15
9.25
1.15
9.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25 		30 8 30 9 11 30 12 30 10 р. 6
92.9
92.10
92.11
92.12
92.13
92.14
92.15
92.16
92.16
92.16
92.16
92.10
92.11
92.21
92.22
80.094
92.23
80.094
92.23
80.094
92.25
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.094
92.26
80.095
80.095
80.095
80.095
80.095
80.095
80.095
80.095
80.095
80.095
80.095
80.095
80.095
80.095
80.095
80.095
80.095
80.095
80.095
80.095
80.095
80.095
80.095
80.095
80.095
80.095
80.095
80.095
80.095
80.095
80.095
80.095
80.095
80.095
80.095
80.095
80.095
80.095
80.095
80.095
80.095
80.095
80.095
80.095
80.055
80.055
80.055
80.055
80.0555
80.0555
80.05555
80.055555555555555555555555555555555555 		20 8 32 9 3110 07 3211 06 3212 73 3213 07 3214 9 3215 3255 3216 9 3217 9 3218 9 3219 30 3220 155 3221 34000 3222 34000 3223 34000 3224 34000 3225 34000 3226 54000 3227 32700 323 34000 3245 34000 3226 5400 3227 32700 328 6470 329 347 329 347 3200 347 323 347 0.8 р. 8
9. 10
5. 11
5. 12
5. 12
5. 13
5. 14
5. 14
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
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5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
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5. 15
5. 15
5. 15
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5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
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5. 15
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5. 15
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5. 15
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5. 15
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5. 15
5. 15
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5. 15
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5. 15
5. 15
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5. 15
5. 15
5. 15
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5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
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5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15
5. 15 		۲۵۵۵
۵۵۵
۵۵۵
۵۵۵
۵۵۵
۵۵۵
۵۵۵
۵۵۵
۵۵۵
۵۵
ZIN
155 MHz
45 TIGM
+125Y
-125Y 		در 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 252
باب 		922
5.3
5.3
5.5
5.5
5.5
5.5
5.5
5.5 		2022
2017
2027
2027
2027
2027
2027
2027
2027
2027
2027
2027
2027
2027
2027
2027
2027
2027
2027
2027
2027
2027
2027
2027
2027
2027
2027
2027
2027
2027
2027
2027
2027
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2027
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2027
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2027
2027
2027
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2027
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2027
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2027
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2027
2027
2027
2027
2027
2027
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2027
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2027
2027
2027
2027
2027
2027
2027
2027
2027
2027
2027
2027
2027
2027
2027
2027
2027
2027
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2027
2027
2027
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2027
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2027
2027
2027
2027
2027
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2027
2027
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2027
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2027
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2027
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2027
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2027
2027
2027
2027
2027
2027
2027
2027
2027
2027
2027
2027
2027
2027
2027
2027 		522
523
523
523
523
523
523
523 		22110000000000000000000000000000000000 9227 EDD
500
500
500
500
500
500
500
5 		2022 ADC 609
5 - 137
5 - 2 		9222 ADCB#
56-1
56-2
56-2
56-3
56-5
56-5
56-5
56-5
56-5
56-9
56-9
56-9
56-10
56-10
56-12
56-13
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
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56-15
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56-15
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56-15
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56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
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56-15
56-15
56-15
56-15
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56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
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56-15
56-15
56-15
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56-15
56-15
56-15
56-15
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56-15
56-15
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56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56-15
56 		222 A1
5-1-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-1-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14
5-2-14 		222 ±1
y = 1 + see
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 2 = 2
y = 		22 A1
24.1 - 55
24.3 - 55
24.4 - 55
24.5 - 50A1
24.5 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
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24.1 - 50A1
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24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
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24.1 - 50A1
24.1 - 50A1
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24.1 - 50A1
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24.1 - 50A1
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24.1 - 50A1
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24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 - 50A1
24.1 		ا م
22
22
22
22
22
22
22
22
22
22
22
22
22 		A PERIO D N N P
PLUT
I
PENLITY
VPLOT
I 		5239 00000
5220 0000
5221 0000
5222 0000
5222 0000
5222 0000
5224 0000
5225 0000
5226 0000
5226 0000
5227 0000
5228 0000
5230 0000
5230 0000
5231 701 		2.18 mesour
2.19 mile
220
221
222
222
224
225
225
225
225
225 		SE.18 SE.20 SE.21 RESOJ SE.22 PINCL SE.23 ZOMR SE.24 AUTO TB SE.25 DT SE.26 PERCET SE.27 Imist SE.28 AUTO TB SE.26 DE CES DT SE.26 AUTO TB SE.27 SE.28 AUTO TB SE.29 CERUN SE.20 5.18
5.20
5.20
5.21
5.22
5.23
5.22
5.23
5.225
5.227
7.250
5.227
7.250
5.227
7.250
5.227
7.250
5.227
7.250
5.227
7.250
5.220
5.20
5.20
5.20
5.20
5.20
5.20 		523
520
520
522
522
522
523
525
525
525
525
527
727
727
727
727
727 		>210 c2 >2019 c3 >2020 c1n >221 ccn >222 ccn >223 ccn >224 mes >225 ccn >227 c22 >228 ccn >229 cr >230 ccstan >231 resa 5.18 c2
5.19 c3
5.20 ETB
5.22 ACCOA
5.23 ACCOA
5.23 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.22 ACCOA
5.22 ACCOA
5.23 ACCOA
5.23 ACCOA
5.23 ACCOA
5.23 ACCOA
5.23 ACCOA
5.23 ACCOA
5.23 ACCOA
5.23 ACCOA
5.23 ACCOA
5.23 ACCOA
5.23 ACCOA
5.23 ACCOA
5.23 ACCOA
5.24 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5.25 ACCOA
5. 		36.18 500 36.20 3620 3622 Acons 3622 Acons 3625 Acons 3626 Acons 3627 JC28 3628 Accos 3629 Accos 3629 Accos 3621 Accos >c18 505 >c19 70 >c20 507 >c21 807 >c221 807 >c221 808 >c255 8086 >c256 8086 >c225 8088 >c226 807 >c228 80708 >c229 84 >c231 42 >c231 42 シム13 3000 シム13 第二 シム20 昭和 シム21 昭和 シム221 福石田市 シム221 福石田市 シム225 ACOBN シム226 BERTD シム230 RETD シム230 AC シム300 AL 5218 505
5220 194
5220 1947
5222 107
5222 107
5224 107
5224 107
5225 107
5225 107
5225 107
5225 107
5227 100
5228 100
5228 100
5229 10
5229 10
5229 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5231 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 10
5331 1 		7 م
ي
ي ي
ي ي
ي
ي
ي
ي
ي
ي
ي
ي
ي
ي
ي
ي
DC 32 ASTIGN 3 C 32 5 32 5 € 32 - 32 32 EDCT ≫32 25.32 5 532 AU 32 NB 84 23.2 Fig. 6 3 .2

13a

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剩 ┥┥┥┥┥┥┥┥┥ਗ਼ਗ਼ਗ਼ਗ਼ਗ਼ਗ਼ਗ਼ਗ਼ਗ਼ਗ਼ਗ਼ਗ਼ਗ਼ਗ਼ਗ਼ਗ਼ਗ਼ਗ਼ਗ਼ਗ਼ਗ਼ਗ਼ਗ਼ਗ਼ਗ਼ਗ਼ਗ਼ਗ਼
20E1 X 1302
1021 X 2003
2 X 2003
x 801
x 915
x 1011
x 1211 		~
2425
2501
2427
PECL
PECL
33
5 5 4 4 5 L S S L S
6 VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
VPLOT
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×917 		x 801 X 130
X 801 X 130
X 801 X 200
X 201 X 200
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50
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x 2003 > 16 > 17 10 > 12 x1 10 07 08 05 7 04 05 5 03 5 04 10 x 302
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2

6-44A

Page 50
6.2.4. Microprocessor unit A4
6.2.4.1. General

As shown in the simplified block diagram, the microprocessor unit basically consists of the following circuit elements:

  • A microprocessor integrated circuit block for controlling and organising data now.
  • Erasable and programmable read-only memories (EPROMs) for system programming.
  • Random-access memories (RAMs) for stacking and storing the variable data.
  • Address and data selection latches for the multiplexed address bus.
  • Decoders for RAM and ROM selection and address decoding.
  • Trap and watchdog circuits to guard against loss of data.
  • Two-way buffer circuit to the system data-bus.
  • A blanking circuit for the c.r.t.

The heart of the microprocessor unit is integrated circuit D408, an 8-bit microprocessor type 8085 with 16 address lines.

The first eight address lines AØ ... A7 are multiplexed with the eight data lines DØ ... D7 and are defined as ADØ ... AD7. Addressing is selected by the ALE (address latch enable) signal from the microprocessor, which gives an external indication when address information is on the bus-lines.

6.2.4.2. Trap Input Circuit

The TRAP input is effective when the battery back-up facility is used. It prevents the RAM contents being disturbed when the instrument is switched off or in the event of a power failure. The TRAP input can be regarded as a non-maskable restart input. A logic 1 level on this input forces the microprocessor to continue with the execution of the program starting at address Ø024H, the starting address of the POWER DOWN routine.

The signal PWR (power), a 50Hz sinewave signal generated on the power supply unit, is converted to a 50Hz squarewave voltage on pin 3 of Schmitt trigger D426 and integrated by C437/R412 to provide pulses on input 11 of the retriggerable one-shot D424.

During the initial switching-on of the power supply, a low voltage on reset input 13 of the one-shot holds the circuit in its reset state. When the power supply is started, however, the retriggerable one-shot switches over and signal PON (power on) goes to logic 1. As long as pulses are generated on input 12, the one-shot will remain in this state.

Failure of the power supply, i.e. no control pulses on input 11, causes the one-shot to be reset and thus activate the TRAP input of the microprocessor.

For test procedures, the circuit can be isolated by unsoldering the spot on the printed-circuit track.

6.2.4.3. CLOCK inputs X1 and X2

A 5 MHz crystal, B401, is connected to the clock inputs X1 and X2 of the microprocessor to provide an accurate timing reference source.

6.2.4.4. RESIN input and WATCHDOG Circuit

A reset signal is generated when the instrument is switched ON. This reset signal forces the microprocessor to start the execution of the main program beginning at the address ØØØØH.

The retriggerable one-shot D424 is initially reset by input pin 3 (R) during the switching-on of the instrument. After switching on, the one-shot is set to the logic 1 state by the DT (display timing) pulses from the display timing flip-flop D409, pin 9 on this p.c. board, applied to D424-5.

The one-shot remains in this state as long as the system continues to generate DT pulses.

If these pulses are interrupted, the circuit functions as a watchdog and resets the microprocessor. The one-shot will in fact be reset to logic 0 and a 1 Hz Schmitt oscillator consisting of C432/V402/R421 and D426 will switch the RESIN input of the microprocessor between logic 0 and logic 1.

Page 51

Page 52

Page 53

This reset process continues unless the program resumes correct running.

For test purposes, the watchdog circuit can be replaced by a fixed reset circuit by soldering the spot on the printed-circuit track.

6.2.4.5. RST 7.5 – RST 6.5 – RST 5.5 inputs

These restart inputs to the microprocessor force it to continue the program on defined addresses, from where it can jump to different programs.

RESTART
INPUTS 		PRIORITY RESTART
ADDRESS 		REMARKS
RS 7.5 Highest ØØ3CH Not used in standard instruments (can eventually be used for test purposes)
RS 6.5 ØØ34H Not used in standard instruments (connected to 'SPARE' connector)
RS 5.5 Lowest ØØ2CH Used by IEC-bus interface option
6.2.4.6. SID (Serial data input)

The microprocessor will receive the information NDR (new data ready) on the SID input.

6.2.4.7. READY input

Via this input, additional WAIT states are generated to double the RD* and WR* pulse duration. This is necessary to provide correct adaption between the microprocessor and the slower acting data RAM circuits. The length of the signals RD* and WR* is doubled by flip-flop D423 only when signal DAT is logic 0. The output of this flip-flop D423 is connected to the microprocessor READY input to indicate the end of the wait time.

6.2.4.8. Connection to the system address bus

The first eight address bits placed by the microprocessor on the multiplexed address-data bus lines ADØ ... AD7 have to be separated from the eight data bits. This separation is achieved by address latch D413, which is enabled by signal ALE.

The group of output signals AØ ... A7 constitute the system address bus.

6.2.4.9. Connection to the system data-bus

The eight data bits placed by the microprocessor on the multiplexed address-data bus lines ADØ ... AD7 have to be separated from the first eight address bits.

This separation is done by the bidirectional buffer D417.

This buffer is selected if address line A15 is logic 1 (as in I/O and DATA part of the memory map). Input or output data depends on the logic level of signal RD*.

RD* = logic 1 means OUTPUT RD* = logic 0 means INPUT

Data is transported between the D417 in- and outputs and the system data-bus over the lines DØ ... D7.

Page 54

Fig. 6.2.15.

ADDRESS DECODING

6.2.4.10. ROM - μP/RAM - I/O - DATA selection

In decoder D419, four select signals are generated as follows:

A15 A14 OUTPUT SIGNAL
0 0 ROM selection to pin 15 - D419
0 1 μPRAM selection signal UPR
1 0 I/O selection signal (not used)
1 1 DATA SELECTION SIGNAL DAT

ROM chip select signals ROMØ ... ROM3

A15 A14 A13 A12 OUTPUT SIGNAL ADDRESSES
0 0 0 0 ROMØ 0000-07FF
0 0 0 1 ROM1 1000 - 17FF
0 0 1 0 ROM2 2000 - 27FF
0 0 1 1 ROM3 3000 - 37FF

I/O select signals IOO ... IOE.

The three-bit decoder D418 decodes the address bits A15, A14, A7*, A6* and A5* into the eight address decoding signals IOØ ... IOE. Each of these signals represent a group of addresses as shown in the table. The signals are used in various circuits of the instrument.

Page 55
A15 A14 A7* A6* A5* OUTPUT SIGNAL ADDRESSES TO UNIT
1 0 0 0 0 ĪOØ 8000 - 801F A21 AMPLIFIER
1 0 0 0 1 102 8Ø2Ø - 8Ø3F A2-A4 SWITCHES + µP
1 0 0 1 0 104 8Ø4Ø - 8Ø5F A6 RAM
1 0 0 1 1 IO6 8Ø6Ø - 8Ø7F A12 TIME-BASE
1 0 1 0 0 108 8Ø8Ø - 8Ø9F A13 TRIGGER DELAY
1 0 1 0 1 ĪŌĀ 80A0-80BF A2 DISPLAY
1 0 1 1 0 IOC 8ØCØ - 8ØDF NOT USED
1 0 1 1 1 ĪŌĒ 8ØEØ - 8ØFF A14 IEC OPTION
ROM MEMORY

The ROM (read-only memory), which contains the system program, consists of the four EPROM chips D403 - D404 - D406 and D407 and 2K-bytes each (2048X 8 bits).

Because the microprocessor's first eight address lines ADØ ... AD7 are multiplexed in the microprocessor with the data lines, the addresses have to be latched by the address latch D416 with the aid of the ALE signal. The ALE signal enables the latching of the AØ* ... A7* signals. These AØ* ... A7* signals are placed on the microprocessor board internal address bus.

Each ROM memory address can be selected by the address lines AØ* ... A7* together with address lines A8 - A9 and A10.

Each ROM memory chip is selected by the read signal RD* and the relevant ROM selection signal ROMØ, ROM1, ROM2 or ROM3.

When a certain ROM address is selected in this way, the contents of the selected location are placed on the multiplexed address-data bus lines ADØ ... AD7.

μP-RAM MEMORY

The µP-RAM (microprocessor random access memory) is used by the microprocessor for stack purposes and for storage of variable data.

It consists of two RAM chips D401 - D402 of ¼K-nibbles each (256 x 4 bits), which means that a maximum of 256 bytes of data can be stored.

Each µP-RAM memory address can be selected by the address lines AØ* ... A7*. The two chips are selected by the signal combination PON.UPR.

Reading the RAM contents or writing data into a RAM location is controlled by the signals RD* and WR*.

The data to be written into, or read from the RAM memory is transported via the multiplexed address-data bus ADØ ... AD7.

DATA LATCH D414

When the microprocessor places the address 8020 on the multiplexed address data bus, this results in signal 102 going to logic 0. This 102 combined with the WR signal on gate D421 enables data latch D414 to latch the byte of data present on the multiplexed address data-bus.

The byte of data consists of the following signals:

BITØ CLR Clear signal for clearing the shift register
BIT 1 REM Control signal for REMOTE lamp
BIT 2 NOT TRIG'D Control signal for NOT TRIG'D lamp
BIT 3 ZEN Z enable signal
BIT 4 RUNL Control signal for RUN lamp
BIT 5 BLOL Blinking overload signal
BIT 6 INV Invert signal for RAM output data
BIT 7 CLDT Clear display timing flip-flop
Page 56
BLANKING CIRCUIT

This circuit provides for a blanking signal ZIN (Z-amplifier input) for blanking the trace on the c.r.t. display.

ZIN = logic 1 means blanking.

The trace on the c.r.t. display is only present if all the input signals of NAND circuit D411 are logic 1 at the same time.

  • pin 4 The signal ZEN is only present during the time that a selected memory (ACCU, STO1, STO 2 or STO3) is displayed.
  • pin 11 If an overflow is detected on the RAM unit the short signal ZOVL (Z-overflow), will be latched in a D-type flip-flop D423 with the clock signal DAT.WR. As the output signal of the flip-flop is connected to OR circuit D421, the blinking overload signal is passed to pin 11 of the NAND D411, resulting in blinking of the trace at a low frequency.
  • pin 3 In mode DOTS, the ZDJ (Z dot join) blinking signal will be active.
  • pin 5 Signal DT (display timing) blanks the trace when no memory contents (ACCU, STO1, STO2 or STO3) are displayed. Signal DT is derived from the addresses, which are also applied to the XDAC for horizontal deflection.

NAND circuit D412 detects the address FDH on the first eight address lines.

The output signal indicates the beginning and the end of a sweep by going to logic 1 level. This signal is latched in D-type flip-flop D409 with the clock signal DAT.WR, resulting in a signal DT.

The trace is blanked if DT = logic 0. Flip-flop D409 can be reset by signal CLDT (clear display timing flip-flop) resulting in a blanked trace.

pin 1 In mode X = A/Y = B (A versus B – AVSB) a signal ZAB is generated on output pin 5 of flip-flop D409. Data can only be latched in this flip-flop on clock signal DAT.WR. This data is derived from signal AØAB. (AØAB is address AØ in mode X = A/Y = B)

Page 57

TRIGGER PULSES FOR TEST PURPOSES

Trigger pulse 'START MAINLOOP' is available at X407 Trigger pulse ''START DISPLAY LOOP'' is available at X409 Trigger pulse 'START DELAY LOOP' is available at X412

INCOMING
SIGNAL 		OUTGOING
SIGNAL 		GENERATED
ON UNIT 		USED
ON UNIT 		DESCRIPTION
AØAB
AVSB 		AØ A7
BLOL
CLK 		A4
A6
A13
A4
A4 		A6 Address bits from system address bit
Address bit AØ in X = A/Y = B mode
Logic 0 in X = A/Y = B mode
Blinking overload
Microprocessor clock pulse output si 		ignal (2,5 MHz
DØ D7 CLR
DØ D7
DAT
DT 		A4
A4-A6
A4
A4 		A8–A9
A6
A13 		Clear signal for shift register
Data bits from system data-bus
Data selection
Display timing
A4
A4 		A0
A21 		Input switches select
amplifier settings (A21)
104
106
108 		A4
A4
A4
A4 		A6
A12
A13 		Output port select (A4)
Data RAM select (A6)
Time-base select (A12)
Delay trigger unit settings (A13) 		I/O address
decoding
signals.
IOA
IOC
IOE 		A4
A4
A4 		A201/A202
NOT USED
A14 		Display select (A2)
NDR NOT TRIG'D
PON 		A9
A4
A4 		A201/A202
A6 		New data ready
Control for NOT TRIG'D lamp
Power on
PWR RD
REM
RESOUT 		A15
A4
A4
A4 		A201/A202
A14 		Power signal (20 KHZ)
Signal READ from microprocessor
Control for REMOTE lamp
Microprocessor RESET OUTPUT sig 		Inal
RST5,5
RST6,5 		A 14
A5
A4
A4
A4 		A201/A202
A6-7-9 		Restart 5,5 input from IEC-bus inter
Restart 6,5 input (not used)
Control for RUN lamp
Microprocessor serial output data
Signal WRITE from microprocessor 		face
ZDJ ZEN
ZIN 		A13
A4
A4 		A15 Z dot join
Z enable
Z input
ZOVL
+5 V
+5 BATT 		A6
A15
A15
A15 		Z overflow signal
Page 58
TEST POINTS
X401 D421-pin 6 (WR.DAT)
X402 PON
X403 UPR
X404 DT
X406 ROMØ
X407 REM
X408 ROM1
X409 RUNL
X411 ROM2
X412 NOT TRIG'D
X413 ROM3
X414 ALE
X416 A15
X417 NDR
X418 SOD
X419 RD*
X421 CLK (OUT)
X422 WR*
V 400
Page 59

Fig. 6.2.16.

MAT 772 B

Page 60

6.58

Page 61

Page 62

RAM - MEMORY

A 4 MICRO PROC UNIT

Page 63
6.2.5. Spare unit A5

There is a connector X501 available on the motherboard unit A3 in which no plug-in unit is placed.

On this connector X501 a number of signals are available for measuring purposes.

A1 +5 V C1 +5 V
A2 0 V C2 0 V
A3 +12 V C3 +12 V
A4 –12 V C4 12 V
A5 ZIN C5 PWR2
A6 XDAC C6 YDAC
A7 +5 BATT C7 +5 BATT
A8 0 V C8 0 V
A9 +6 V C9 6V
A10 D7 C10 D6
A11 D5 C11 D4
A12 D3 C12 D2
A13 D1 C13 DØ
A14 RST 6.5 C14 RES OUT
A15 AVSB C15 IOC
A16 PON C16 ZOVL
A17 NDR C17 INV
A18 IOØ C18 SOD
A19 WR C19 RD
A20 IO4 C20 DAT
A21 IO2 C21 IOA
A22 ACQB3 C22 ACQB7
A23 ACQB2 C23 ACQB6
A24 ACQB1 C24 ACQB5
A25 ACQBØ C25 ACQB4
A26 IOE C26 2,5 MHz
A27 OER3 C27 OER2
A28 OER1 C28 OERØ
A29 A7 C29 A6
A30 A5 C30 A4
A31 A3 C31 A2
A32 A1 C32 AØ
Page 64
6.2.6. RAM unit A6

The RAM unit basically comprises the four random-access memories, ACCU, STO1, STO2, STO3 used for signal storage, the two digital-to-analog converters X DAC and Y DAC and their associated control circuits.

6.2.6.1. RAM memories ACCU, STO1, STO2, STO3

Each of the RAM memories consists of two RAM IC-chips of ¼K-nibbles each (256x4 bits) enabling a maximum of 256 bytes to be stored.

The overall memory is selected by PON.DAT = 1, i.e. with the power on and the data field addressed. Memory allocation is as follows:

MEMORY IC ELEMENTS
ACCU D601, D602
STO1 D603, D604
STO2 D606, D607
STO3 D608, D609

Selection of one or more of the memories is made under microprocessor control.

A byte of data representing the information for reading or writing one or more of the memories is sent by the microprocessor on data-lines DØ ... D7 to the latch D613. If the signal combination WR.IO4 is logic 1, the data byte will be latched by D613.

Two groups of output signals are produced by latch D613:

Output Enable RAM signals (OER)
  • signals OERØ OER3 select the memory of which the contents are
    required to be read.
Write Enable RAM signals (WRER)
  • signals WRERØ WRER3 select the memory in which data is
    required to be written. With no WR signal available these signals are
    blocked.

Individual RAM locations are selected by address lines AØ ... A7.

Data inputs for the memories

Data received from other units can only be stored in the ACCU RAM. Data stored in any of the other three memories STO1, STO2, STO3, is always derived from the ACCU memory.

Data for storage in the ACCU memory (D601, D602) can be:

- output data ACQBØ ... ACQB7 from the acquisition circuit,

- data from the microprocessor,

- data from the IEC-bus interface board via the system data-bus lines DØ ... D7.

The signals ACQB0 ... ACQB7 are applied to the latch D614 and the signals D0 ... D7 are applied to the latch D616.

Selection of either one of these latches is made under microprocessor control via the logic level of signal SOD (serial output data).

SOD = 1selectsD614SOD = 0selectsD616 via inverter D626

Inverter D626 prohibits the output of data from both latches to the ACCU bit lines at the same time.

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Overflow detection

The information in the RAMs is stored in 2's complement notation, which means that signal amplitudes are stored in positive as well as negative binary numbers.

maximum positive +127 0111 1111 +1 0000 0001 +0 0000 0000 -1 1111 1111 maximum negative -128 1000 0000

From the above, we can see that if the most-significant bit of a binary number is at logic 0, we have a positive number, otherwise it represents a negative number.

An incorrect setting of the AMPL/DIV switch or the OFFSET control causes an overflow, which means that the result after digitising is greater than can be stored. Therefore, if the maximum number 0111 1111 or the minimum number 1000 0000 is reached, an overflow situation is recognised. This is signalled by a flashing trace on the c.r.t. display.

These two extreme overflow situations can be decoded as follows:

The most-significant bit D7 is inverted by D626 (1,2) resulting in the overflow codes 0000 0000 or 1111 1111. By comparing the inverted most-significant bit with the other seven bits in exclusive OR circuits D618 and D619, an output signal ZOVL (Z Overload) is indicated when one of these two overload situations occurs. The overflow signal ZOVL is applied to the Z-pulse (ZIN) circuit on Unit 4 to produce the flashing of the display when overload is reached.

6.2.6.2. Digital-to-analog converters X DAC, Y DAC
DAC output signals in X = t mode

Horizontal deflection on the c.r.t. display in the X = t mode is controlled by the addresses needed for reading the contents of the memories. Therefore, the address bits A0 ... A7 are applied to the X DAC (horizontal digital-to-analog converter) D622 to generate an analog deflection signal XDAC that varies between +5 V and -5 V.

The address bits are applied to the X DAC (D622) via two multiplexers D611 and D612, which are controlled by the signal AVSB.

AVSB= 1selects X = t modeAVSB= 0selects X = A / Y = B mode

Vertical deflection on the c.r.t. display is controlled by the eight data bits D0' ... D7', which are applied to the Y DAC (D621) to generate an analog deflection signal Y DAC.

These data bits are routed to the Y DAC via eight exclusive OR gates D623, D624, which are controlled by the INV signal to invert the data when the front-panel INV switches are operated.

The X DAC and Y DAC latches can be enabled by the enable signals X DACE and Y DACE respectively. These are the output signals from the multiplexer D628, which is enabled by the DAT signal. Selection of input signals to the multiplexer is made by the signals AØAB and AVSB according to the following table:

AVSB AØAB XDACE YDACE
0 0 WR _ }. X=A/Y=B mode
0 1 WR WR
1 1 WR WR | } X=t mode
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DAC output signals in X = A/Y = B mode

If channel A as well as channel B information is stored in the RAMs, XY deflection can be obtained by selecting the X = A/Y = B mode by depressing the relevant front-papel switch

To give XY deflection, the channel information on A and B has to be applied to the X DAC and the Y DAC respectively.

There are two different methods of storing the channel A and channel B information in the RAMs.

Channel A ODD:
(FASDI = 0) 		Channel A information is stored in locations with ODD addresses and channel B in locations with EVEN addresses.
Channel A EVEN: Channel A information is stored in locations with EVEN addresses and channel B in
(FASDI = 1) locations with ODD addresses.

To obtain XY deflection, it is necessary to apply data from the ODD addresses to the X DAC and data from the EVEN addresses to the Y DAC or vice versa depending on the logic level of the FASDI signal.

For correct functioning, only one DAC latch may be enabled at a time, this being controlled by the enable signals XDACE and YDACE on the output of multiplexer D628.

The logic level of signal FASDI (phase of display) controls which channel is stored in odd or even addresses by determining which DAC is loaded first. If FASDI is at logic 0, we have the situation where X DAC (latch D622) is loaded first; i.e. channel A will be stored in the odd addresses.

Alternatively, if FASDI is at logic 1, then Y DAC (latch D621) will be loaded first and channel B will be stored in the odd addresses.

FASDI AØ AØAB
0 0 1
0 1 0
1 0 0
1 1 1

FASDI = 0 results in AØ being inverted FASDI = 1 results in AØ not inverted

Page 67
INCOMING
SIGNAL 		OUTGOING
SIGNAL 		GENERATED
ON UNIT 		USED
ON UNIT 		DESCRIPTION
AØ A7 A4 Address bits from system address bus
AØAB A6 A4 Address bit AØ in X=A/Y=B mode
ACQBØ ACQB7 A7 Acquisition output bits 0 8
AVSB A13 Logic 0 in X=A/Y=B mode
DØ D7 DØ D7 A4-A6 Data bits from system data-bus
DAT A4 Data selection
FASDI A13 Phase on display level
INV A4 Signal invert
104 A4 Data RAM select
OERØ A6 A20 Output enable RAMØ
OER1 A6 A20 Output enable RAM1
OER2 A6 A20 Output enable RAM2
OER3 A6 Output enable RAM3
PON A4 Power on
RD A4 Signal READ from microprocessor
SOD A4 Microprocessor serial output data
WR A4 Signal WRITE from microprocessor
X DAC A6 A20 Horizontal DAC output signal
Y DAC A6 A20 Vertical DAC output signal
ZOVL A6 A4 Z overflow signal
+5 V A15
A15
+5 BATT A15
+12 V A15
-12 V A15
Page 68

Page 69

6.7

Page 70

Page 71

Page 72
6.2.7. Buffer unit A7
6.2.7.1. General

The buffer unit consists of a 9-bit x 256 digital shift register for data storage and a digital-to-analog converter DAC M-1, which re-converts the digital output signals from the ADC for the correction of subsequent analog signals.

Analog information from the acquisition section of the oscilloscope is converted into a 9-bit digital value ADCBØ ... ADCB8 on the conversion unit. After conversion and final correction, these signal bits are shifted into the 9-bit x 256 digital shift register D701 ... D711 on this buffer unit, for storage. The contents of this shift register are only shifted under the control of a clock signal CLKSH, generated in D718 D719

CLKSH = (INSNDR) + (SODWR)

Shifting can be interrupted therefore by blocking signal CLKSH.

The nine shift register output signals will only be applied to the ACQB bus in the P2CCD-mode (signal P = logic 1) for correction purposes or if signal NDR = logic 1 (new data is available). Data is applied to the ACQB bus via the 3-state non-inverting buffers D716 and D717.

6.2.7.2. Data routeing and correction in P2CCD mode

For details of this, refer to the Conversion Unit A8 description.

6.2.7.3. Data routeing and correction in DRS-mode

In the DRS-mode (Direct, Roll and Sample), inaccuracies of the Track/Hold circuit and the ADC circuit are corrected before the information is stored in the shift register.

The circuit is operative for dual-channel mode working, i.e. with both channel A and channel B switched on. This mode is arranged to function automatically even if only one channel is selected.

Principle of operation

Fig. 6.2.20

To reduce errors in conversion, analog samples for digitising are compared with preceding samples, these being subtracted so that only small increments are converted to digital values in the ADC. After conversion, the digital equivalent of the original analog signal is produced by adding the differential signal from the ADC to the digital value of the preceding sample.

Referring to the block diagram, Mn is the new sample of the input signal from the acquisition system; Mn-1 is the preceding sample, derived from the shift register and re-converted by DAC M-1 to analog form. At the input to the Track and Hold circuit, Mn-1 is subtracted from Mn to produce a differential analog voltage, which is then converted to digital form in the ADC and added to the preceding digital value Mn-1.

i.e. (M_n - M_{n-1}) + M_{n-1} = M_n

Page 73

After this procedure, the adder output value Mn will be shifted into a shift register as a new and corrected value. This system of digital adding is also used, in a different way, in the P2CCD-mode as described in the Conversion Unit A8.

Detailed description

This digital adding technique is now described in greater detail with reference to the various circuit elements. The analog value of the preceding signal sample Mn-1 is subtracted from the new sample Mn in the vertical amplifier stage. This results in a differential analog voltage Mn – Mn-1, which is converted to digital signals ADCBØ ... ADCB8 and applied to the adder circuit on unit A8 together with the preceding sample Mn-1 in digital form.

After adding overflow detection and marking, the sum signal Mn is applied as ADCBØ ... ADCB8 to the shift register on the buffer unit A7. With this new signal value stored in the shift register, the circuit continues with the next.

The corrected sample value Mn on the ADCB lines from the conversion unit A8 to the shift register is also applied to the 4-bit latches D712 and stored under the control of signal CØ. The output signals from the latches are applied to the digital-to-analog converter DAC (M-1) D714.

In the P-mode, the DAC (M-1) circuit is switched off by the P signal on the LE input pin 10.

However, in the DRS-mode the DAC (M-1) circuit is switched on.

The most-significant bit of the 8-bit 2's complement information offered to the DAC (M-1) is inverted by D719 (4,5) to translate the data into 8-bit straight binary notation.

Conversion by DAC (M-1) results in the analog value of the preceding digital sample Mn-1 and this value is fed back to the vertical amplifier stage for subtraction from the new signal sample Mn.

In the amplifier stage, analog subtraction will result in a new differential voltage as previously described. This differential voltage Mn – Mn-1 is then converted to digital in the ADC and added to the old digital value Mn-1. The old digital value that was stored in the two 4-bit latches D712 is in the meantime shifted to the next two 4-bit latches D713 by control signal C4 and fed to the adder circuit. Here, the 8-bit 2's complement notation is converted into a 9-bit ACQBØ ... ACQB8 digital form by copying the last bit.

Data from one signal source only may be fed to the ACQB bus by more than one buffer simultaneously. This is made possible by signals P and NDR via NOR-gate D718 (4,5,6) and inverter D719 (2,3).

Each time an NDR pulse is generated, the total shift register contents will be copied into the ACCU memory. Precise timing diagrams are given in the ACL Unit A9 description.

Fig. 6.2.21.

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INCOMING
SIGNALS 		OUTGOING
SIGNALS 		GENERATED
ON UNIT 		USED
ON UNIT 		DESCRIPTION
АСОВФ 8 A7 A68 Acquisition output bits Ø 8
ADCBØ 8 A8 ADC bits
CØ A9 Control Ø signal from ACL unit
C4 A9 Control 4 signal from ACL unit
CLKSH A7 Clock pulse for shift register
DAC M-1 A7 A21 DAC M-1 output signal
INS A9 Shift command for shift register
NDR A9 A4 New data ready
Ρ A12 A78910 P-mode signal
SOD A4 Microprocessor serial output data
SOD A7 A8 | Microprocessor serial output data
WR A4 | | Signal write from microprocessor
+5 V A15
+12 V A15
—12 V A15
A15
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Page 76

-5V

Page 77

MAT BOIA

Fig. 6.2.23.

6.80

Page 78

Page 79

Fig. 6.2.23.

Page 80
6.2.8. Conversion unit A8

The conversion unit basically consists of an ADC for converting the input signals into digital form for storing in the shift register on the buffer unit A7, a circuit for signal zero correction, and an overflow detection and marking circuit.

These functions are performed by the following circuit blocks:

  • a sample and hold circuit for analog inputs, D822
  • analog-to-digital converter (ADC) D821
  • AND-gates D801, D813 for controlling inputs to the adder circuit
  • exclusive-OR gates D802, D814, D809 for inverting signal to adder for subtraction during correction
  • adder circuit D803, D816, D804
  • multiplexers D806, D807, D817, D818 on adder outputs for overflow detection, marking, etc.
  • result registers D819, D811 for storing multiplexer output signals.
6.2.8.1. Sample and Hold circuit

Analog output signal VOUT from the CCD logic unit (A10), which represents the A and/or B channel input signals in one of the selected modes, is applied to input 3 of the sample and hold circuit D822. This circuit is controlled by the TRACK signal:

TRACK = logic 1 – the circuit only tracks the input signal

TRACK = logic 0 - (= HOLD) the circuit holds the input level that was present at the negative-going edge of the TRACK signal

The output signal of this sample and hold circuit D822 provides an input to the ADC that lies between +5 V and -5 V.

6,2.8,2, Analog-to-digital converter (ADC)

The analog input level from the sample and hold circuit is converted into a digital 9-bit number in the ADC circuit D823.

Conversion is controlled by the clock pulses CLADC. (Nine clock pulses are used to convert to this 9-bit number). As the ADC is a 10-bit type, the least-significant bit being ignored. These clock pulses are only generated by the ACL unit A9 during the period when the CONV signal (conversion) is at logic 1.

The ADC output signal CONV reverts to logic 0 at the end of the conversion period, thus indicating that conversion is complete and that the results can be fed to the ADCBØ ... ADCB8 bus via the tri-state non-inverting buffers D811, D812.

The 9-bit digital output of the ADC is straight binary coded and is converted to 2's complement notation in exclusive-OR gate D809 (11.12.13) by inverting the most-significant (9th) bit, as shown in the following table.

STRAIGHT BINARY (9-bit) 2's COMF 2's COMPLEMENT (9-bit)
Decimal Decimal
–5 V +0 0 0 0 0 0 0 0 0 0 -256 1 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 -255 1 0 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 0 -128 1 1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1 1 -1 1 1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 0 0 +0 0 0 0 0 0 0 0 0 0
1 0 1 1 1 1 1 1 1 +127 0 0 1 1 1 1 1 1 1
+5 V +511 1 1 1 1 1 1 1 1 1 +255 0 1 1 1 1 1 1 1 1
Ł ÷ I N٧ /EF ٩SI ٥N I OF THE 9th B IT ——— 4
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The 2's complement equivalent value is fed to the ADCB bus-lines by the tri-state non-inverting buffers D811, D812 under the control of signal C1. With C1 at logic 1, the buffers are in 3-state mode.

Signal input C1 is a control line which, together with signal C2 prevents simultaneous input of data to the bus-lines by more than one buffer.

6.2.8.3. Correction circuits

As the correction circuits operate in conjunction with other circuits that are not part of the conversion unit A8, the data routeing and the principles of correction in the P2CCD-mode are first discussed.

Data routeing and correction in the P2CCD-mode

Due to internal P2CCD faults and differences between the frequencies fin and fout, an incorrect zero level of the P2CCD output signal is possible as shown in the following graph.

P2 CCD output signal with shifting zero level

Under these conditions, the total faulty contents of the P2CCD are converted from analog form to digital in 256 steps and after each conversion the data is put on the ADCBØ ... ADCB8 bus and directly shifted into the 9-bit shift register on buffer unit A7. After 256 steps, the total P2CCD contents are stored here, and the register is then blocked.

In order to correct the zero level, the P2CCD input is switched to zero and 256 samples of this zero signal are shifted into the P2CCD at the same frequency fin as for the normal input signal.

By reading the P2CCD contents again, with the same frequency fout (78 kHz) as for the faulty input signal, an incorrect zero level having the same errors as described above will appear on the P2CCD output as shown below.

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This incorrect zero level is then digitally subtracted (in 256 steps) from the faulty input signal, which was already stored in the shift register

The corrected result is then re-stored in the shift register

Correction circuit description

Considering the correction circuits in more detail, the correction cycle is started when the P2CCD is completely filled with zero samples. This is done in 256 steps, in which for every step, one sample of faulty input information from the shift register, and one converted zero sample from the P2CCD are applied to an adder circuit on this conversion unit (A8) consisting of the integrated circuits D803 D816 and D804

The procedure is as follows:

  • The shift register contents are placed byte after byte on the ACOBØ ... 8 bus via a buffer and directly applied to the inputs of the adder circuite
  • The samples of zero information from the P2CCD are placed on the ADCBØ ... 8 bus, sample after sample in the same way as described for the uncorrected signal information. However, in this case it is not shifted into the shift register but is transferred via AND-gates D801, D813 and exclusive-OR gates D802, D814 and D809 (4.5.6) to the adder circuit. For correct overflow detection and marking, bit 9 is copied and applied to the adder as hit 10

(During the copying of the shift register contents into the ACCU memory in BOLL-mode, one side of the adder input is blocked via AND-gates D801, D813 by the NDB signal to permit recirculation of the shiftregister contents )

The exclusive-OR circuits serve to invert the zero information so that it can be subtracted from the signal information. The subtraction process is performed by inverting the zero information and adding it, together with a forced carry to the signal information from the shift register The forced carry is obtained by signal P on input 9 of adder circuit D803.

At the output of the adder, the corrected signal samples appear one by one and are transferred to the overflow detecting and marking circuits (multiplexers D806, D807, D817, D818).

The ACCU memory, and thus the c.r.t. display, is 8-bit wide; therefore the corrected adder output signals, which can be 10-bit wide are checked for overflow. Consequently, if overflow occurs, this condition will be indicated and overflow marking is necessary

Fig. 6.2.26.

Marking is carried out by changing the signal value during overflow in one of the digital values +127 or -128. via the multiplexers D806 D807 D817 D818

These multiplexers are controlled by the adder output bits ADOB7, ADOB8, ADOB9, which give information about overflow

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ADOB9 ADOB8 ADOB7 MULTIPLEXER OUTPUT
0 0 0 ADDER OUTPUT
0 0 1 +127
0 1 0 +127
0 1 1 NON-EXISTING
1 0 0 COMBINATIONS
1 0 1 —128
1 1 0 —128
1 1 1 ADDER OUTPUT

In case of an overflow, signal ADOB9 indicates whether it is an overflow or an underflow. ADOB8 and ADOB7 together indicate whether there is an overflow condition.

After marking, the multiplexer output signals are stored in the result register D819 under the control of C3. These output signals are applied to the bus ADCBØ ... 8 via D819 and D811 when signal C2 is logic 0. C2 = 1 indicates that the buffer outputs are in tri-state.

At the same time, the last bit is copied to re-establish a correct 9-bit 2's complement notation.

The data placed on the bus in this way are the corrected samples and are shifted again into the shift register. After 256 correction steps the shift register contains the complete corrected signal.

Signal NDR (new data ready) now reverts to logic 1 and the shift register contents are copied into the ACCU memory under the control of the microprocessor and its software.

The contents of the shift register are copied into the ACCU memory including the overflow markings +127 or -128. The overflow markings are detected by hardware when the contents of the ACCU are required to be displayed on the c.r.t. screen. This results then in a flashing trace on the c.r.t. screen to indicate this overflow. The same is possible if the ACCU-memory contents are saved in one of the memories STO1 - STO2 or STO3.

Signal CLR enables zeros to be placed on the bus to reset the shift register contents in case of ACCU-memory clearing.

Data routeing and correction in DRS mode

Refer to description of buffer unit A7.

Note: For timing diagrams and explanation of timing refer to the description of the ACL unit A9.

INCOMING OUTGOING GENERATED USED DESCRIPTION
SIGNAL SIGNAL ON UNIT ON UNIT
ACQBØ ACQB8
C1
C2
C3
CLADC
CLR
NDR
P
SOD
TRACK
VOUT
WR 		ADCBØ 8 A7
A8
A9
A9
A9
A9
A4
A4
A8
A9
A12
A7
A9
A10
A10
A4 		Acquisition output bits Ø 8
ADC output signals bit Ø bit 8
Control 1 signal from ACL unit
Control 2 signal from ACL unit
Control 3 signal from ACL unit
Clock signal for ADC
Clear signal for shift register
Conversion
New data ready
P 2 CCD-mode
Microprocessor serial output data
Track command from ACL unit
CCD logic unit analog output signal
Signal WRITE from microprocessor
Page 84

CONVERSION UNIT A8

Fig. 6.2.27.

-----

Page 85

Page 86

Page 87

A 8 CONVERSION U

c2|

Fig. 6.2.28.

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6.2.9. Acquisition control logic unit A9
6.2.9.1. General

Before discussing the timing functions in the various operating modes, the general circuit functions of the Acquisition Control Logic unit are first outlined. The ACL unit contains the timing circuits that generate the signals required to control the conversion unit (A8) and the buffer unit (A7).

A Hold and Convert pulse HOCON starts each analog-to-digital conversion of an input signal sample. In the P-mode, this is signal HOCON P from the CCD logic unit A10; in the Direct, Roll and Sampling modes, this is HOCON DRS from the trigger unit A22.

Depending on the mode selected, one of these hold and convert signal lines is applied to the clock input of D-type flip-flop D909 via multiplexer D911, pin 7. This multiplexer is controlled by the signals P and R, to give the following:

-
SIGN
R 		NALS
P 		D911
output pin 7
0 0 HOCON DRS
0 1 HOCON P
1 0 HOCON DRS
1 1 (unavailable input signal combination)

Flip-flop D909 is switched by the HOCON pulse, resulting in the TRACK signal going to logic 0, which brings the Track and Hold circuit on the conversion unit to the HOLD state.

Analog-to-digital conversion is now started and controlled by the nine clock pulses CLADC (pin 11 of NANDgate D906), which are derived from a 1,25 MHz clock signal. During conversion in the ADC, a signal CONV is at logic 1. After conversion, this signal goes to logic 0, indicating that conversion is finished. Output pin 6 of flip-flop D909 is now switched to 0 by the CONV signal and this zero resets the other two flip-flops in the circuit (RESET inputs D908-12, D909-13). In this way, the CONV signal blocks the CLADC pulses again and switches the TRACK signal. The track and hold circuit now returns to tracking the input signal.

The CHOP output of chopper flip-flop D908 is switched to its opposite state at the end of each conversion by signal CONV on its clock input. Only in the P-mode, where the CHOP signal is not required, is the chopper flip-flop set permanently to its '1'-state, i.e. signal CHOP is logic 1. This is achieved by a zero level on the direct set input of the flip-flop.

During each conversion, a CØ pulse on D906-8 is fed from the CONV signal to control the first buffer stage (D712 on unit A7) after the adder circuit (on unit A8). This is the buffer stage that sends its data to the digital-to-analog converter DAC (M-1).

At the completion of each ADC conversion, counter D928, which has been preset to the value 15, starts counting the 1,25 MHz pulses on its clock input.

The start of counting is initiated by the output signal of flip-flop D927, which is set to logic 1 by the positivegoing edge of the CONV signal.

OD ос ОВ OA
15 — →_ _1 1 1 1
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 O 1 1 1
15 20
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The first counting pulse results in counter-state 0. Output signals OA, OB, OC and OD are applied to a BCD/1 : 10 decoder, D923.

Control pulses C3 and C4 are derived directly from decoder outputs 3 and 4 respectively. The C3 pulses are only present whenever there is no new data ready, i.e. if NDR = logic 1.

After state 7 of the counter, a logic 0 on output pin 9 of the decoder is fed back to the direct reset input of flip-flop D927 to switch it to its zero state. Thus the count pulses for the counter are blocked and it is again preset by the value 15. From the same decoder output signal a COUNT pulse is given via flip-flop D913, which is switched as a normal inverter. One COUNT signal is generated for each ADC conversion and so provides a means of counting the number of conversions.

Control pulses C1, C2 (C1 inverted) and INSP are generated by multiplexer D921 controlled by the NDR and PN signals.

CONTROL SIGNALS OUTPUT SIGNALS
NDR PN C1 INSP
0 0 ОС INSR
0 1 0 V C3
1 0 +5 V +5 V
1 1 +5 V +5 V

Signals C1 and INSP are permanently at logic 1 during NDR. Therefore, during copying the contents of the shift register into the ACCU memory, the buffer following the ADC circuit will be set in its tri-state, i.e. no ADC output data can be sent either to the adder or to the shift register circuit.

Signal C1 will be at logic 1 when uncorrected signal information has to be shifted into the shift register in the P-mode (PN at logic 1). This allows the information to be shifted directly into the register. The shift command INSP is in this situation derived from signal C3. In the DRS modes and during zero correction in the P-mode, C1 and also C2 signals are derived from counter output OC. These signals control the ADC output buffer and the adder output register (D819 on unit A8) so that only one of the two can output data on to the ADCBØ ... 8 bus at any given time.

In the DRS modes, and during zero correction in the P-mode, the INSP signal is derived from decoder output signal INSR. Therefore, INSP is generated after the correction result is put in the result register and the register output data is fed to the ADCBØ ... 8 bus.

6.2.9.2. Timing in P-mode

Flip-flop D913 is set to logic 1 by a trigger pulse DELTRG in normal trigger mode and by AUTRI in the AUTO mode, both signals being generated by the delayed trigger unit (A13).

After receiving a trigger signal, the NULIN signal goes to logic 1. This signal is applied to the vertical amplifier unit A21 to block the amplifier channels so that a zero level is offered to the P2CCD inputs. A signal FOE (frequency output enable) also goes to logic 0 (assuming that pin 10 of D914 is at logic 1) to

indicate to the CCD logic unit that the P2CCD contents can be read with a clock signal of 78 kHz approx. This will result in HOCON P pulses to start ADC conversions.

The COUNT signals generated at each conversion are counted by the 10-bit acquisition control logic counter consisting of two flip-flops D924 and two 4-bit counters D918 and D917.

This counter, which was in its reset state in the preceding P-mode cycle, is now enabled for counting. Signal NUL IN switches, via multiplexer D916, the flip-flop D902 so that the counter is no longer held in its reset state and is ready to receive count pulses. Signal FOE sets the multiplexer D926 so that the COUNT pulses on input 12 appear at output 9. These COUNT pulses are applied to the counter and after 256 have been counted the entire P2CCD contents are read, digitised and shifted into the shift register. Counter state 256 is indicated by a logic 1 on pin 12 of D917. This signal switches FOE to logic 1 via inverter D919 and NAND-gate D914 to stop the P2CCD read cycle.

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A cycle now starts in which the P2CCD is completely filled with zero information, using the same frequency for shifting as that for reading in the input signal information.

Signal FOE now switches multiplexer D926 to the state where the 50 kHz signal on pin 13 is coupled to the input of the counter. Counting continues up to 512 and in the meantime, zero information is shifted for about 5 msec into the P2CCD via the NUL IN signal in the vertical amplifier unit (256 x 0,02 msec is approximately 5 msec).

When the counter reaches 512, output 12 of D917 returns to logic 0 and also signal FOE = logic 0. Now a cycle starts in which the zero contents of the P2CCD are read and digitised in 256 steps at a clock frequency of approximately 78 kHz. At every step, one sample of uncorrected information in the shift register is corrected by a zero sample from the P2CCD and the result shifted again into the register. After 256 corrections the total corrected signal is present in the shift register.

At the end of the correction cycle, the state 768 (512+256) of the counter is detected by NAND-gate D914 (11,12,13), which results in a logic 0 on output pin 11.

This signal is fed to output pin 9 of multiplexer D916 and causes flip-flop D902 to switch to its zero state. The output signal on pin 9 of D902 prepares the reset of two synchronous counters with synchronous clear, D918, D917. These can now be reset by a pulse on the clock input, which is derived from a 1,25 MHz clock signal via D926 and D924. The clock signal can pass through multiplexer D926 because of the low level of the output signal on pin 9 of D916, which is applied to input 2 of D926.

After the reset of counters D918 and D917, the output pin 3 of NAND-gate D914 goes to logic 0 via the multiplexer and NAND-gate D914 (11,12,13). This signal resets the two flip-flops D924 of the acquisition control logic counter. The entire counter is now in the reset state and remains in this state until the next NUL IN signal is generated.

At the end of the correction cycle, the positive-going edge of the signal on output 8 of flip-flop D902 will, via multiplexer D901, switch NDR flip-flop D902 to its logic 1 state. Signal NDR is applied to the SID input of the microprocessor on unit A4 to indicate that new data is ready and can be copied by the ACCU memory.

After a certain time, the microprocessor reacts by generating a logic 1 on its SOD output and 256 WR pulses followed by a logic 0 on its SOD input. During the SOD signal the shift register contents are copied into the ACCU memory in 256 steps controlled by the WR pulses from the microprocessor.

Trigger flip-flop D913 is then brought to its reset state by signal CTF, which is derived from signal NDR via multiplexer D901.

The whole system can react again on incoming trigger pulses at the end of the 'handshake' cycle.

Fig. 6.2.29

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Flip-flop NDR is then reset by the positive-going edge of the SOD signal via the flip-flop consisting of NAND-gates D903, and signal CTF goes to logic 1 so enabling trigger flip-flop D913 again.

The NDR signal will also be generated while the CLEAR button on the front panel is operated. Signal CLR is then at logic 0.

6.2.9.3. Timing in Direct mode

In the Direct mode the flip-flop D913 is switched to logic 1 by a trigger pulse DELTRG in normal trigger mode and by AUTRI in the AUTO mode, both signals being generated by the delayed trigger unit (A13).

On receipt of a trigger, flip-flop D913 is switched and applies a logic 1 to the D-input of NDR flip-flop D902 via NAND-gate D903 (1,2,3).

The NDR flip-flop switches to logic 1 at the first COUNT pulse on its clock input (received via multiplexer D901). This commences an NDR cycle to copy the shift register contents into the ACCU memory in the way already described for the P-mode.

The NDR flip-flop is reset by the positive-going edge of the SOD signal via the flip-flop comprising NAND circuits D903. Simultaneously, the acquisition control logic counter starts counting 256 COUNT pulses. This start is initiated by the NDR signal on the clock input of flip-flop D902, received via multiplexer D916. At this same start time, a logic 0 on output 8 of flip-flop D902 causes output CTF of multiplexer D901 to go to logic 0. This results in a reset of the trigger flip-flop D913.

The acquisition control logic counter counts up to state 256. This state is decoded, resulting in a logic 1 on pin 12 of counter D917, which is applied via inverter D919 (8,9) and multiplexer D916 to flip-flop D902.

The counter is then reset in the way described for the P-mode.

At this moment, it is established that at least 256 new samples of the input signal are stored in the shift register, so the total shift register contents are refreshed (i.e. a type of trigger hold-off).

Resetting the acquisition control logic counter results in signal CTF going to logic 1, thus again enabling the trigger flip-flop D913.

This prepares the flip-flop to receive another trigger to start a new D-mode cycle.

Fig. 6.2.30.

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6201 Timing in Poll mode

If ROLL-mode is selected and the RUN/STOP pushbutton is pressed once, the ROLL-mode action is started by TBS pulses generated on time-base unit A12 after a start signal from the microprocessor HOCON DBS pulses are derived from the TBS pulses on trigger unit A22. Each HOCON DBS pulse applied to the ACL unit A9 starts an analog-to-digital conversion of a new input signal sample. The ACL unit is set to ROLL-mode by the B control signal

In the ROLL-mode the D-input of the NDR flip-flop D902 is permanently at logic 1 via NAND-gate D903 (1.2.3). Each time a new signal sample is stored in the shift register, a COUNT pulse is generated and an NDR cycle started as described for the P-mode

During this NDR cycle, the entire shift register contents are copied by the ACCU memory and re-circulated.

The microprocessor and its software calculate the number of NDR cycles and after each 256 the ACCU memory contents are copied in one of the memories STO3_STO2_STO1 under software control The last 256 samples remain in the ACCU memory. The ROLL-mode is now finished, this being indicated by

a flashing RUN lamp on the instrument front panel.

Fig. 6.2.31.

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6.2.9.5. Timing in Sampling mode

The control signal S sets the ACL unit in the Sampling mode.

Correct functioning in this mode requires that signals of a repetitive nature are applied to the input channels of the instrument.

Each sampling cycle is started with the staircase counter in the zero position and a pre-determined LEVEL setting.

During one sampling cycle 256 samples of the input signal are stored in the shift register to build a complete signal picture. Each input trigger signal takes one sample of the input signal as now described.

On each trigger signal a fast ramp signal is generated (on unit A22) which is compared with the output of a DAC circuit DACSTAIR, D904. This circuit is coupled to the staircase counter to convert the counter state into the analog signal DACSTAIR.

At the crossover point determined by each comparison of the fast ramp signal and the DACSTAIR signal, an HOCON DRS pulse is generated to start the ADC conversion of the new signal sample.

The time between samples depends on the fast ramp speed which, in turn, is determined by the time-base frequency setting.

Fig. 6.2.32.

After each conversion, a COUNT pulse is counted by the staircase counter, which causes the DACSTAIR output signal to increase by one step (40 mV).

In this way, the time between the trigger pulses and the generation of the HOCON DRS signal increases so that each new sample is taken one step later.

The shift register is completely filled after 256 samples and its contents can be copied by the ACCU memory. This is initiated by state 256 of the staircase counter. A logic 1 on pin 12 of the counter D917 causes it to reset to zero as already described in the P-mode. The logic 1 level on output 8 of reset flip-flop D902 is fed to the clock input of the NDR flip-flop via multiplexer D901. This starts an NDR cycle and the shift register contents can be copied in the ACCU memory. After this, the staircase counter is again enabled for counting by the positive-going edge of the NDR signal via multiplexer D916 and a new sampling cycle is started.

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Fig. 6.2.33.

Fig. 6.2.34.

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6.2.9.6. Flip-flop FASA

The flip-flop FASA stores the information indicating whether the last sample stored in the shift register was from channel A or channel B.

FASA = 1 : channel A was last sample FASA = 0 : channel B was last sample

In the P-mode, the flip-flop FASA is set to the level of its D-input signal PDRIVE by the leading edge of every INS pulse on its clock input while the PR signal is logic 1 (CHOP is permanently at logic 1 in the P-mode).

In the DRS modes, flip-flop FASA is switched to the level of its D-input signal CHOP by the leading edge of every INS pulse on its clock input (signals PR and PDRIVE are permanently at logic 1 in the DRS modes).

The state of flip-flop FASA cannot be changed while NDR is logic 1, i.e. during the copying of the shift register contents into the ACCU memory. During this cycle the flip-flop state is read by the software.

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TAL SAMPLING SYSTEM

JTN

Page 99
INCOMING
SIGNAL 		OUTGOING
SIGNAL 		GENERATED
ON UNIT 		USED
ON UNIT 		DESCRIPTION
AUTRI 04 47
CØ A9
A9 Control 2 signal
C2 A9 AO
C3 A9 AO
C4 A9 Control 4 signal
СНОР A9 AZI
CLADC A9 A8
CLR A4 Clear signal for shift register
CLR A9 A8 Inverted CLR signal
CONV A8 Conversion
CTF A9 A13 Clear signal for trigger flip-flop
D A12 D-mode signal
DACSTAIR A9 A22
DELTRIG A13 Delayed trigger signal
EOCØ A9 A9 Enable output COUNT Ø
EOC1 A3 Enable output COUNT 1
FASA A9 A202 Output phase flip-flop
FOE A9 A10 Frequency output enable
HOCON DRS A22 Hold and convert signal in D-R and S mode
HOCONP A10 Hold and convert signal in P-mode
INS A9 A7 Shift command for shift register
NDR-NDR A9 A4-7-8 New data ready
NULIN A9 A21 Signal to switch vert. ampl. input to zero
Ρ A12 P-mode signal
PDRIVE A10 Phase signal in P-mode
PRES A9 A10 Enable signal in P-mode.
R A12 R-mode signal
S A12 S-mode signal
SOD A4 Microprocessor serial output data
ТВАСК A9 A8-A22 Track command for S/H circuit
50 kHz A12 50 kHz pulse
1.25 MHz A12 1,25 MHz pulse
+5 V A15
_12 V A15
+12 V A15
A15
TEST POINTS
TEST POINTS
X901
X902
X903
X904
X906
X907
X908
X909
X909
X911
X912
X913 		FOE
NUL IN
HOCONDRS
SOD
NDR
TRACK
CØ
CLADC
CONV
C3
C4
X914
X916 		EOCØ/EOC1
Page 100

ACL UNIT A9

Fig. 6.2.37.

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