Philips PHP82NQ03LT, PHB82NQ03LT, PHD82NQ03LT User Guide

1. Product proﬁle

1.1 Description

1.2 Features

PHP/PHB/PHD82NQ03LT

TrenchMOS™ logic level FET

Rev. 01 — 28 March 2002 Product data

N-channel logic level ﬁeld-effect transistor in a plastic package using TrenchMOS™ technology.

Product availability:

PHP82NQ03LT in SOT78 (TO-220AB) PHB82NQ03LT in SOT404 (D2-PAK) PHD82NQ03LT in SOT428 (D-PAK).

■ Logic level compatible ■ Low gate charge

1.3 Applications

■ DC to DC converters ■ Switched mode power supplies

1.4 Quick reference data

■ VDS=30V ■ ID=75A

■ P

= 136 W ■ R

tot

DSon

≤ 8mΩ

2. Pinning information

Table 1: Pinning - SOT78, SOT404, SOT428 simpliﬁed outlines and symbol

Pin Description Simpliﬁed outline Symbol

1 gate (g) 2 drain (d) 3 source (s) mb mounting base,

connected to drain (d)

[1]

MBK106

12mb3

SOT78 (TO-220) SOT404 (D

mb

2

13

2

-PAK)

MBK116

mb

2

13

Top view

MBK091

SOT428 (D-PAK)

MBB076

d

g

s

[1] It is not possible to make connection to pin 2 of the SOT404 or SOT428 packages.

Philips Semiconductors

PHP/PHB/PHD82NQ03LT

TrenchMOS™ logic level FET

3. Limiting values

Table 2: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

V

DS

V

DGR

V

GS

V

GSM

I

D

I

DM

P

tot

T

stg

T

j

Source-drain diode

I

S

I

SM

drain-source voltage (DC) 25 ≤ Tj≤ 175oC - 30 V drain-gate voltage (DC) 25 ≤ Tj≤ 175oC; RGS=20kΩ -30V gate-source voltage (DC) - ±20 V peak gate-source voltage tp≤ 50 µs; pulsed; duty cycle = 25 % - ±25 V drain current (DC) Tmb=25°C; VGS= 10 V; Figure 2 and 3 -75A

= 100 °C; VGS=10V;Figure 2 -75A

T

mb

peak drain current Tmb=25°C; pulsed; tp≤ 10 µs; Figure 3 - 240 A total power dissipation Tmb=25°C; Figure 1 - 136 W storage temperature −55 +175 °C operating junction temperature −55 +175 °C

source (diode forward) current (DC) Tmb=25°C - 75 A peak source (diode forward) current Tmb=25°C; pulsed; tp≤ 10 µs - 240 A

9397 750 09308

Product data Rev. 01 — 28 March 2002 2 of 14

Philips Semiconductors

()

PHP/PHB/PHD82NQ03LT

TrenchMOS™ logic level FET

120

P

der

(%)

80

40

0

0 50 100 150 200

P

tot

P

der

-----------------------

P

tot 25 C°()

100%×= I

03aa16

T

(oC)

mb

Fig 1. Normalized total power dissipation as a

function of mounting base temperature.

3

10

120

I

der

(%)

80

40

0

0 50 100 150 200

I

D

der

-------------------

I

D25C

100%×=

°

03ai53

T

(ºC)

mb

Fig 2. Normalized continuous drain current as a

function of mounting base temperature.

03ai55

I

D

(A)

2

10

1

1 10 10

R

DSon

= V

DS

/ I

D

DC

V

DS

tp = 10 µs 100 µs

1 ms

10 ms

2

(V)

Tmb=25°C; IDM is single pulse; VGS = 10V.

Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.

9397 750 09308

Product data Rev. 01 — 28 March 2002 3 of 14

Philips Semiconductors

PHP/PHB/PHD82NQ03LT

TrenchMOS™ logic level FET

4. Thermal characteristics

Table 3: Thermal characteristics

Symbol Parameter Conditions Min Typ Max Unit

R

th(j-mb)

R

th(j-a)

thermal resistance from junction to mounting base Figure 4 - - 1.1 K/W thermal resistance from junction to ambient SOT78 package; vertical in still air - 60 - K/W

SOT428 package;

- 75 - K/W SOT428 minimum footprint; mounted on a PCB

SOT404 and SOT428 packages;

- 50 - K/W SOT404 minimum footprint; mounted on a PCB

4.1 Transient thermal impedance

03ai54

t

p

δ =

T

t

T

(s)

t

p

Z

th(j-mb)

(K/W)

10

1

10

δ = 0.5

0.2

-1

0.1

0.05

0.02

-2

single pulse

-3 10

-5

10

-4

10

-3

10

-2

10

-1

P

t

p

1 10

Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.

9397 750 09308

Product data Rev. 01 — 28 March 2002 4 of 14

Philips Semiconductors

PHP/PHB/PHD82NQ03LT

TrenchMOS™ logic level FET

5. Characteristics

Table 4: Characteristics

Tj=25°C unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Static characteristics

V

(BR)DSS

V

GS(th)

I

DSS

I

GSS

R

DSon

Dynamic characteristics

Q

g(tot)

Q

gs

Q

gd

C

iss

C

oss

C

rss

t

d(on)

t

r

t

d(off)

t

f

Source-drain diode

V

SD

t

rr

Q

r

drain-source breakdown voltage ID= 250 µA; VGS=0V

=25°C 30--V

T

j

= −55 °C 27--V

T

j

gate-source threshold voltage ID= 1 mA; VDS=VGS; Figure 9

T

=25°C 1 1.9 2.5 V

j

= 175 °C 0.6 - - V

T

j

= −55 °C - - 2.9 V

T

j

drain-source leakage current VDS=30V; VGS=0V

T

=25°C - 0.05 1 µA

j

= 175 °C - - 500 µA

T

j

gate-source leakage current VGS= ±20 V; VDS= 0 V - 10 100 nA drain-source on-state resistance VGS=5V; ID=25A;Figure 7 and 8

T

=25°C - 8.3 10 mΩ

j

= 175 °C - 15 18 mΩ

T

j

= 10 V; ID=25A;Figure 7 and 8 - 6.3 8 mΩ

V

GS

total gate charge ID= 50 A; VDD=15V; VGS=5V;Figure 13 - 16.7 - nC gate-source charge - 8 - nC gate-drain (Miller) charge - 5 - nC input capacitance VGS=0V; VDS= 25 V; f = 1 MHz; Figure 11 -1620-pF output capacitance - 480 - pF reverse transfer capacitance - 165 - pF turn-on delay time VDD=15V; ID= 25 A; VGS= 4.5 V; RG= 5.6 Ω -20-ns rise time -78-ns turn-off delay time - 30 - ns fall time -24-ns

source-drain (diode forward) voltage IS= 25 A; VGS=0V;Figure 12 - 0.9 1.2 V reverse recovery time IS= 10 A; dIS/dt = −100 A/µs;

=0V;VDS=25V

V

recovered charge - 24 - nC

GS

-32-ns

9397 750 09308

Product data Rev. 01 — 28 March 2002 5 of 14