Philips PHP71NQ03LT, PHB71NQ03LT, PHD71NQ03LT User Guide

1. Product profile

1.1 Description

1.2 Features

PHP/PHB/PHD71NQ03LT

TrenchMOS™ logic level FET

Rev. 01 — 25 June 2002 Product data

N-channel enhancement mode field-effect transistor in a plastic package using
TrenchMOS™ technology.

Product availability:

PHP71NQ03LT in SOT78 (TO-220AB)
PHB71NQ03LT in SOT404 (D2-PAK)
PHD71NQ03LT in SOT428 (D-PAK).

■ Logic level compatible ■ Low gate charge

1.3 Applications

■ DC to DC converters ■ Switched mode power supplies

1.4 Quick reference data

■ VDS=30V ■ ID=75A

■ P

= 120 W ■ R

tot

DSon

≤ 10 mΩ

2. Pinning information

Table 1: Pinning - SOT78, SOT404, SOT428 simplified outline and symbol

Pin Description Simplified outline Symbol

1 gate (g)
2 drain (d)
3 source (s)
mb mounting base,

connected to drain (d)

[1]

MBK106

12mb3

SOT78 (TO-220) SOT404 (D

mb

2

13

MBK116

2

-PAK) SOT428 (D-PAK)

mb

2

13

Top view

MBK091

MBB076

d

g

s

[1] It is not possible to make connection to pin 2 of the SOT404 or SOT428 packages.

Philips Semiconductors

PHP/PHB/PHD71NQ03LT

TrenchMOS™ logic level FET

3. Limiting values

Table 2: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

V

DS

V

DGR

V

GS

V

GSM

I

D

I

DM

P

tot

T

stg

T

j

Source-drain diode

I

S

I

SM

drain-source voltage (DC) 25 °C ≤ Tj≤ 175 °C - 30 V
drain-gate voltage (DC) 25 °C ≤ Tj≤ 175 °C; RGS=20kΩ -30V
gate-source voltage (DC) - ±20 V
peak gate-source voltage tp≤ 50 µs; pulsed; duty cycle = 25 % - ±25 V
drain current (DC) Tmb=25°C; VGS=10V;Figure 2 and 3 -75A

= 100 °C; VGS=10V;Figure 2 - 57.7 A

T

mb

peak drain current Tmb=25°C; pulsed; tp≤ 10 µs; Figure 3 - 240 A
total power dissipation Tmb=25°C; Figure 1 - 120 W
storage temperature −55 +175 °C
junction temperature −55 +175 °C

source (diode forward) current (DC) Tmb=25°C - 75 A
peak source (diode forward) current Tmb=25°C; pulsed; tp≤ 10 µs - 57.7 A

9397 750 09821

Product data Rev. 01 — 25 June 2002 2 of 14

© Koninklijke Philips Electronics N.V. 2002. All rights reserved.

Philips Semiconductors

03aa16

0

40

80

120

0 50 100 150 200

Tmb (°C)

P

der

(%)

PHP/PHB/PHD71NQ03LT

TrenchMOS™ logic level FET

P

tot

P

der

-----------------------

P

tot 25 C°()

100%×= I

Fig 1. Normalized total power dissipation as a

function of mounting base temperature.

3

10

120

I

der

(%)

80

40

0

0 50 100 150 200

I

D

der

-------------------

I

D25C

()

100%×=

°

03ai74

Tmb (°C)

Fig 2. Normalized continuous drain current as a

function of mounting base temperature.

03ai76

I

D

(A)

2

10

10

1

1 10 10

Limit R

DSon

= V

DS

/ I

D

DC

tp = 10 µs

100 µs

1 ms

10 ms

2

VDS (V)

Tmb=25°C; IDM is single pulse; VGS = 10V.

Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.

9397 750 09821

Product data Rev. 01 — 25 June 2002 3 of 14

© Koninklijke Philips Electronics N.V. 2002. All rights reserved.

Philips Semiconductors

PHP/PHB/PHD71NQ03LT

TrenchMOS™ logic level FET

4. Thermal characteristics

Table 3: Thermal characteristics

Symbol Parameter Conditions Min Typ Max Unit

R

th(j-mb)

R

th(j-a)

thermal resistance from junction to mounting base Figure 4 - - 1.25 K/W
thermal resistance from junction to ambient

SOT78 vertical in still air - 60 - K/W
SOT428 SOT428 minimum footprint;

- 75 - K/W

mounted on a PCB

SOT404 and SOT428 SOT404 minimum footprint;

- 50 - K/W

mounted on a PCB

4.1 Transient thermal impedance

03ai75

δ =

t

p

T

tp (s)

Z

th(j-mb)

(K/W)

10

1

10

10

δ = 0.5

0.2

0.1

-1

0.05

0.02

single pulse

-2
10

-5

10

-4

10

-3

10

P

-2

Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.

t

p

T

t

-1

10

9397 750 09821

© Koninklijke Philips Electronics N.V. 2002. All rights reserved.

Product data Rev. 01 — 25 June 2002 4 of 14

Philips Semiconductors

PHP/PHB/PHD71NQ03LT

TrenchMOS™ logic level FET

5. Characteristics

Table 4: Characteristics

Tj=25°C unless otherwise specified

Symbol Parameter Conditions Min Typ Max Unit

Static characteristics

V

(BR)DSS

V

GS(th)

I

DSS

I

GSS

R

DSon

Dynamic characteristics

Q

g(tot)

Q

gs

Q

gd

C

iss

C

oss

C

rss

t

d(on)

t

r

t

d(off)

t

f

Source-drain diode

V

SD

t

rr

Q

r

drain-source breakdown voltage ID= 250 µA; VGS=0V

T

=25°C 30--V

j

= −55 °C 27--V

T

j

gate-source threshold voltage ID= 1 mA; VDS=VGS; Figure 9

T

=25°C 1 1.9 2.5 V

j

= 175 °C 0.6 - - V

T

j

= −55 °C - - 2.9 V

T

j

drain-source leakage current VDS=30V; VGS=0V

T

=25°C - 0.05 1 µA

j

= 175 °C - - 500 µA

T

j

gate-source leakage current VGS= ±20 V; VDS= 0 V - 10 100 nA
drain-source on-state resistance VGS=5V; ID=25A;Figure 7 and 8

T

=25°C - 12 15.2 mΩ

j

= 175 °C - 21.6 27.4 mΩ

T

j

= 10 V; ID=25A;Figure 7 - 8 10 mΩ

V

GS

total gate charge ID= 50 A; VDD=15V; VGS=5V;Figure 13 - 13.2 - nC
gate-source charge - 5.3 - nC
gate-drain (Miller) charge - 4.6 - nC
input capacitance VGS=0V; VDS= 25 V; f = 1 MHz; Figure 11 - 1220 - pF
output capacitance - 330 - pF
reverse transfer capacitance - 140 - pF
turn-on delay time VDD=15V; ID= 25 A; VGS= 4.5 V; RG= 5.6 Ω -15-ns
rise time - 150 - ns
turn-off delay time - 13.5 - ns
fall time -18-ns

source-drain (diode forward) voltage IS= 25 A; VGS=0V;Figure 12 - 0.9 1.2 V
reverse recovery time IS= 10 A; dIS/dt = −100 A/µs; VGS=0V - 29 - ns
recovered charge - 20 - nC

9397 750 09821

Product data Rev. 01 — 25 June 2002 5 of 14

© Koninklijke Philips Electronics N.V. 2002. All rights reserved.

Philips Semiconductors

PHP/PHB/PHD71NQ03LT

TrenchMOS™ logic level FET

7 V

03ai77

5.5 V6 V
5 V

4.5 V

4 V

3.5 V

VGS = 3 V

VDS (V)

03ai78

5 V

80

VDS > ID x R

I

D

(A)

60

40

20

0

0246

=25°C and 175 °C; VDS> IDxR

j

DSon

175 °C

Tj = 25 °C

Fig 6. Transfer characteristics: drain current as a

function of gate-source voltage; typical values.

2

a

1.5

80

Tj = 25 °C

I

D

(A)

60

40

20

0

0 0.2 0.4 0.6 0.8 1

10 V

Tj=25°CT

Fig 5. Output characteristics: drain current as a

function of drain-source voltage; typical values.

20

R

(mΩ)

DSon

15

VGS = 4.5 VTj = 25 °C

03ai79

VGS (V)

DSon

03af18

5.5 V

10

5

0

0

20

40

6 V
7 V

10 V

60

ID (A)

80

Tj=25°C

Fig 7. Drain-source on-state resistance as a function

of drain current; typical values.

1

0.5

0

-60 0 60 120 180

R

DSon

=

a

---------------------------- -

R

DSon 25 C°()

Tj (°C)

Fig 8. Normalized drain-source on-state resistance

factor as a function of junction temperature.

9397 750 09821

© Koninklijke Philips Electronics N.V. 2002. All rights reserved.

Product data Rev. 01 — 25 June 2002 6 of 14

Philips Semiconductors

PHP/PHB/PHD71NQ03LT

TrenchMOS™ logic level FET

3.2

V

GS(th)

(V)

2.4

1.6

0.8

0

-60 0 60 120 180

ID= 1 mA; VDS=V

max

typ

min

GS

03ai29

Tj (°C)

Fig 9. Gate-source threshold voltage as a function of

junction temperature.

4

10

-1

10

I

D

(A)

-2

10

-3

10

-4

10

-5

10

-6

10

0 0.8 1.6 2.4 3.2

typ maxmin

03ai28

VGS(V)

Tj=25°C; VDS=5V

Fig 10. Sub-threshold drain current as a function of

gate-source voltage.

03ai81

C

(pF)

C

10

10

3

2

-1

10

1 10 10

iss

C

oss

C

rss

VDS (V)

2

VGS=0V;f=1MHz

Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values.

9397 750 09821

© Koninklijke Philips Electronics N.V. 2002. All rights reserved.

Product data Rev. 01 — 25 June 2002 7 of 14

Philips Semiconductors

03ai82

0

2

4

6

8

10

0 5 10 15 20 25

QG (nC)

V

GS

(V)

ID = 50 A
Tj = 25 °C
VDD = 15 V

PHP/PHB/PHD71NQ03LT

TrenchMOS™ logic level FET

80

VGS = 0 V

I

S

(A)

60

40

20

0

0 0.3 0.6 0.9 1.2

03ai80

Tj = 25 °C175 °C

VSD (V)

Tj=25°C and 175 °C; VGS=0V ID= 50 A; VDD=15V

Fig 12. Source (diode forward) current as a function of

source-drain (diode forward) voltage; typical

Fig 13. Gate-source voltage as a function of gate

charge; typical values.

values.

9397 750 09821

© Koninklijke Philips Electronics N.V. 2002. All rights reserved.

Product data Rev. 01 — 25 June 2002 8 of 14

Philips Semiconductors

PHP/PHB/PHD71NQ03LT

TrenchMOS™ logic level FET

6. Package outline

Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB SOT78

AE

p

A

1

q

D

1

D

(1)

L

1

b

L

1

L

2

mounting

base

Q

123

b

e

e

0 5 10 mm

scale

c

DIMENSIONS (mm are the original dimensions)

L

(1)

b

A

4.5

4.1

A

1.39

1.27

1

UNIT

mm

Note

1. Terminals in this zone are not tinned.

OUTLINE

VERSION

SOT78 SC-463-lead TO-220AB

b

c

1

1.3

1.0

0.7

0.4

0.9

0.7

IEC JEDEC EIAJ

D

D

15.8

6.4

15.2

5.9

REFERENCES

e

E

1

10.3

9.7

2.54

L

15.0

13.5

L

3.30

2.79

2

1

max.

3.0

qQ

p

3.8

3.0

3.6

2.7

EUROPEAN

PROJECTION

2.6

2.2

ISSUE DATE

00-09-07
01-02-16

Fig 14. SOT78 (TO-220AB).

9397 750 09821

Product data Rev. 01 — 25 June 2002 9 of 14

© Koninklijke Philips Electronics N.V. 2002. All rights reserved.

Philips Semiconductors

PHP/PHB/PHD71NQ03LT

TrenchMOS™ logic level FET

Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads
(one lead cropped)

A

E

D

1

D

H

D

mounting

base

2

A

1

SOT404

13

e e

DIMENSIONS (mm are the original dimensions)

0.64

0.46

D

max.

11

UNIT

mm

VERSION

A

4.50

4.10

OUTLINE

SOT404

A

1.40

1.27

b

1

0.85

0.60

IEC JEDEC EIAJ

D

1

1.60

10.30

1.20

9.70

REFERENCES

b

0 2.5 5 mm

scale

E

eLpH

2.90

2.54

2.10

D

15.80

14.80

Qc

2.60

2.20

L

p

c

Q

EUROPEAN

PROJECTION

ISSUE DATE

99-06-25
01-02-12

Fig 15. SOT404 (D2-PAK)

9397 750 09821

Product data Rev. 01 — 25 June 2002 10 of 14

© Koninklijke Philips Electronics N.V. 2002. All rights reserved.

Philips Semiconductors

PHP/PHB/PHD71NQ03LT

Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads
(one lead cropped)

seating plane

y

A

E

b

2

A

mounting

base

A

2

A

1

TrenchMOS™ logic level FET

SOT428

E

1

D

H

E

L

2

2

L

13

b

1

e

e

1

DIMENSIONS (mm are the original dimensions)

(1)

A

A

A

UNIT

mm

Note

1. Measured from heatsink back to lead.

OUTLINE
VERSION

SOT428 TO-252 SC-63

2.38

2.22

1

0.65

0.45

b

2

0.89

0.93

0.71

0.73

IEC JEDEC JEITA

bc

b

1

1.1

0.9

b

5.46

5.26

wAM

D

c

2

0.4

6.22

0.2

5.98

REFERENCES

D

1

L

1

0 10 20 mm

scale

D

1

min.

4.0

E

EH

6.73

6.47

4.81

4.45

1

2.285

ee

1

4.57

10.4

9.6

E

2.95

2.55

L

1

L

min.

0.5

EUROPEAN

PROJECTION

L

0.9

0.5

2

y

w

max.

0.2 0.2

ISSUE DATE

99-09-13
01-12-11

Fig 16. SOT428 (D-PAK)

9397 750 09821

Product data Rev. 01 — 25 June 2002 11 of 14

© Koninklijke Philips Electronics N.V. 2002. All rights reserved.

Philips Semiconductors

7. Revision history

Table 5: Revision history

Rev Date CPCN Description

01 20020625 Product data; initial version.

PHP/PHB/PHD71NQ03LT

TrenchMOS™ logic level FET

9397 750 09821

Product data Rev. 01 — 25 June 2002 12 of 14

© Koninklijke Philips Electronics N.V. 2002. All rights reserved.

Philips Semiconductors

Philips Semiconductors

8. Data sheet status

PHP/PHB/PHD71NQ03LT

PHP/PHB/PHD71NQ03LT

TrenchMOS™ logic level FET

TrenchMOS™ logic level FET

Data sheet status

Objective data Development This data sheet containsdata from the objectivespecification for productdevelopment. Philips Semiconductors

Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a

Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to

[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[1]

Product status

9. Definitions

Short-form specification — The data in a short-form specification is

extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.

Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.

Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitablefor
the specified use without further testing or modification.

[2]

Definition

reserves the right to change the specification in any manner without notice.

later date. Philips Semiconductors reserves the right to change the specification without notice, in order to
improve the design and supply the best possible product.

make changes at any time in order to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change Notification (CPCN) procedure
SNW-SQ-650A.

10. Disclaimers

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to
make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve
design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, andmakes no representationsor warranties thatthese products are
free frompatent,copyright, or mask workright infringement, unlessotherwise
specified.

11. Trademarks

TrenchMOS —is a trademark of Koninklijke Philips Electronics N.V.

Contact information

For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: [e-mail]. Fax: [phone]

© Koninklijke Philips Electronics N.V. 2002. All rights reserved.

9397 750 09821

9397 750 09821

Product data Rev. 01 — 25 June 2002 13 of 14

Product data Rev. 01 — 25 June 2002 13 of 14

© Koninklijke Philips Electronics N.V. 2002. All rights reserved.

Philips Semiconductors

Contents

1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.4 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1

2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 1

3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2

4 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4

4.1 Transient thermal impedance . . . . . . . . . . . . . . 4

5 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5

6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9

7 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12

8 Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 13

9 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

10 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

11 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

PHP/PHB/PHD71NQ03LT

TrenchMOS™ logic level FET

© Koninklijke Philips Electronics N.V. 2002.
Printed in The Netherlands

All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.

The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.

Date of release: 25 June 2002 Document order number: 9397 750 09821