PHP/PHB/PHD71NQ03LT
TrenchMOS™ logic level FET
Rev. 01 — 25 June 2002 |
Product data |
1.Product profile
1.1Description
N-channel enhancement mode field-effect transistor in a plastic package using
TrenchMOS™ technology.
Product availability:
PHP71NQ03LT in SOT78 (TO-220AB)
PHB71NQ03LT in SOT404 (D2-PAK)
PHD71NQ03LT in SOT428 (D-PAK).
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1.2 |
Features |
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■ Logic level compatible |
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■ Low gate charge |
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1.3 |
Applications |
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■ DC to DC converters |
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■ Switched mode power supplies |
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1.4 |
Quick reference data |
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■ VDS = 30 V |
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■ ID = 75 A |
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■ Ptot = 120 W |
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■ RDSon ≤ 10 mΩ |
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2. |
Pinning information |
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Table 1: Pinning - SOT78, SOT404, SOT428 simplified outline and symbol |
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Pin |
Description |
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Simplified outline |
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Symbol |
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1 |
gate (g) |
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mb |
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mb |
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mb |
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d |
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2 |
drain (d) |
[1] |
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3 |
source (s) |
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mb |
mounting base, |
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g |
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connected to drain (d) |
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2 |
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MBB076 s |
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1 |
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2 |
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3 MBK116 |
1 |
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3 |
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MBK106 |
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Top view |
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MBK091 |
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1 |
2 |
3 |
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SOT78 (TO-220) |
SOT404 (D2-PAK) |
SOT428 (D-PAK) |
[1]It is not possible to make connection to pin 2 of the SOT404 or SOT428 packages.
Philips Semiconductors |
PHP/PHB/PHD71NQ03LT |
|
TrenchMOS™ logic level FET |
Table 2: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol |
Parameter |
Conditions |
Min |
Max |
Unit |
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VDS |
drain-source voltage (DC) |
25 °C ≤ Tj ≤ 175 °C |
- |
30 |
V |
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VDGR |
drain-gate voltage (DC) |
25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ |
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30 |
V |
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VGS |
gate-source voltage (DC) |
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- |
±20 |
V |
VGSM |
peak gate-source voltage |
tp ≤ 50 μs; pulsed; duty cycle = 25 % |
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±25 |
V |
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ID |
drain current (DC) |
Tmb = 25 °C; VGS = 10 V; Figure 2 and 3 |
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75 |
A |
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Tmb = 100 °C; VGS = 10 V; Figure 2 |
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57.7 |
A |
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IDM |
peak drain current |
Tmb = 25 |
°C; pulsed; tp ≤ 10 μs; Figure 3 |
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240 |
A |
Ptot |
total power dissipation |
Tmb = 25 |
°C; Figure 1 |
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120 |
W |
Tstg |
storage temperature |
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−55 |
+175 |
°C |
Tj |
junction temperature |
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−55 |
+175 |
°C |
Source-drain diode |
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IS |
source (diode forward) current (DC) |
Tmb = 25 |
°C |
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75 |
A |
ISM |
peak source (diode forward) current |
Tmb = 25 |
°C; pulsed; tp ≤ 10 μs |
- |
57.7 |
A |
9397 750 09821 |
© Koninklijke Philips Electronics N.V. 2002. All rights reserved. |
Product data |
Rev. 01 — 25 June 2002 |
2 of 14 |
Philips Semiconductors |
PHP/PHB/PHD71NQ03LT |
|
TrenchMOS™ logic level FET |
120 |
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03aa16 |
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Pder |
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(%) |
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80 |
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40 |
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0 |
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0 |
50 |
100 |
150 |
200 |
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Tmb (°C) |
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P |
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= |
Ptot |
× 100% |
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der |
---------------------- |
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P |
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tot (25°C ) |
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Fig 1. Normalized total power dissipation as a function of mounting base temperature.
120 |
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03ai74 |
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Ider |
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(%) |
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80 |
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40 |
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0 |
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0 |
50 |
100 |
150 |
200 |
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Tmb (°C) |
I der |
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I D |
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= ------------------- × 100% |
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I D(25°C ) |
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Fig 2. Normalized continuous drain current as a function of mounting base temperature.
103 |
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03ai76 |
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ID |
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(A) |
Limit RDSon = VDS / ID |
tp = 10 μs |
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102 |
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100 μs |
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DC |
1 ms |
10 |
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10 ms |
1 |
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102 |
1 |
10 |
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VDS (V) |
Tmb = 25 °C; IDM is single pulse; VGS = 10V.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 09821 |
© Koninklijke Philips Electronics N.V. 2002. All rights reserved. |
Product data |
Rev. 01 — 25 June 2002 |
3 of 14 |
Philips Semiconductors |
PHP/PHB/PHD71NQ03LT |
|||||
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|
TrenchMOS™ logic level FET |
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4. Thermal characteristics |
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Table 3: |
Thermal characteristics |
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Symbol |
Parameter |
Conditions |
Min |
Typ |
Max |
Unit |
Rth(j-mb) |
thermal resistance from junction to mounting base |
Figure 4 |
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1.25 |
K/W |
Rth(j-a) |
thermal resistance from junction to ambient |
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SOT78 |
vertical in still air |
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60 |
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K/W |
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SOT428 |
SOT428 minimum footprint; |
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75 |
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K/W |
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mounted on a PCB |
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SOT404 and SOT428 |
SOT404 minimum footprint; |
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50 |
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K/W |
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mounted on a PCB |
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10 |
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03ai75 |
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Zth(j-mb) |
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(K/W) |
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1 |
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δ = 0.5 |
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0.2 |
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0.1 |
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10-1 |
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P |
tp |
0.05 |
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δ = T |
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0.02 |
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single pulse |
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tp |
t |
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T |
10-2 |
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10-5 |
10-4 |
10-3 |
10-2 |
10-1 |
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tp (s) |
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.
9397 750 09821 |
© Koninklijke Philips Electronics N.V. 2002. All rights reserved. |
Product data |
Rev. 01 — 25 June 2002 |
4 of 14 |
Philips Semiconductors |
PHP/PHB/PHD71NQ03LT |
|
TrenchMOS™ logic level FET |
Table 4: Characteristics
Tj = 25 °C unless otherwise specified
Symbol |
Parameter |
Conditions |
Min |
Typ |
Max |
Unit |
Static characteristics |
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V(BR)DSS |
drain-source breakdown voltage |
ID = 250 μA; VGS = 0 V |
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Tj = 25 °C |
30 |
- |
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V |
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Tj = −55 °C |
27 |
- |
- |
V |
VGS(th) |
gate-source threshold voltage |
ID = 1 mA; VDS = VGS; Figure 9 |
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Tj = 25 °C |
1 |
1.9 |
2.5 |
V |
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Tj = 175 °C |
0.6 |
- |
- |
V |
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Tj = −55 °C |
- |
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2.9 |
V |
IDSS |
drain-source leakage current |
VDS = 30 V; VGS = 0 V |
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Tj = 25 °C |
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0.05 |
1 |
μA |
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Tj = 175 °C |
- |
- |
500 |
μA |
IGSS |
gate-source leakage current |
VGS = ±20 V; VDS = 0 V |
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10 |
100 |
nA |
RDSon |
drain-source on-state resistance |
VGS = 5 V; ID = 25 A; Figure 7 and 8 |
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Tj = 25 °C |
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12 |
15.2 |
mΩ |
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Tj = 175 °C |
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21.6 |
27.4 |
mΩ |
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VGS = 10 V; ID = 25 A; Figure 7 |
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8 |
10 |
mΩ |
Dynamic characteristics |
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Qg(tot) |
total gate charge |
ID = 50 A; VDD = 15 V; VGS = 5 V; Figure 13 |
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13.2 |
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nC |
Qgs |
gate-source charge |
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5.3 |
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nC |
Qgd |
gate-drain (Miller) charge |
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4.6 |
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nC |
Ciss |
input capacitance |
VGS = 0 V; VDS = 25 V; f = 1 MHz; Figure 11 |
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1220 |
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pF |
Coss |
output capacitance |
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330 |
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pF |
Crss |
reverse transfer capacitance |
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140 |
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pF |
td(on) |
turn-on delay time |
VDD = 15 V; ID = 25 A; VGS = 4.5 V; RG = 5.6 Ω |
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15 |
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ns |
tr |
rise time |
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150 |
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ns |
td(off) |
turn-off delay time |
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13.5 |
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ns |
tf |
fall time |
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18 |
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ns |
Source-drain diode |
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VSD |
source-drain (diode forward) voltage |
IS = 25 A; VGS = 0 V; Figure 12 |
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0.9 |
1.2 |
V |
trr |
reverse recovery time |
IS = 10 A; dIS/dt = −100 A/μs; VGS = 0 V |
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29 |
- |
ns |
Qr |
recovered charge |
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20 |
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nC |
9397 750 09821 |
© Koninklijke Philips Electronics N.V. 2002. All rights reserved. |
Product data |
Rev. 01 — 25 June 2002 |
5 of 14 |