Datasheet PHP50N06LT Datasheet (Philips)

Philips Semiconductors Product specification

TrenchMOS transistor PHP50N06LT, PHB50N06LT, PHD50N06LT
Logic level FET

FEATURES SYMBOL QUICK REFERENCE DATA

• ’Trench’ technology V

d

= 55 V

DSS

• Very low on-state resistance

• Fast switching I

= 50 A

D

• Stable off-state characteristics

• High thermal cycling performance R

• Low thermal resistance

g

R

s

≤ 24 mΩ (VGS = 5 V)

DS(ON)

≤ 22 mΩ (VGS = 10 V)

DS(ON)

GENERAL DESCRIPTION

N-channelenhancementmode,logic level, field-effect power transistor in a plastic envelopeusing’trench’technology.
Thedevicehas very low on-stateresistance. It is intended foruse in dc to dc converters and general purpose switching
applications.

The PHP50N06LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB50N06LT is supplied in the SOT404 surface mounting package.
The PHD50N06LT is supplied in the SOT428 surface mounting package.

PINNING SOT78 (TO220AB) SOT404 SOT428

PIN DESCRIPTION

1 gate
2 drain

1

tab

tab

tab

3 source

tab drain

123

2

13

2

1

3

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DSS

V

DGR

V

GS

I

D

I

DM

P

D

Tj, T

Drain-source voltage Tj = 25 ˚C to 175˚C - 55 V
Drain-gate voltage Tj = 25 ˚C to 175˚C; RGS = 20 kΩ -55V
Gate-source voltage - ± 13 V
Continuous drain current Tmb = 25 ˚C - 50 A

Tmb = 100 ˚C - 35 A
Pulsed drain current Tmb = 25 ˚C - 200 A
Total power dissipation Tmb = 25 ˚C - 125 W
Operating junction and - 55 175 ˚C

stg

storage temperature

1 It is not possible to make connection to pin 2 of the SOT428 or SOT404 packages.

September 1998 1 Rev 1.400

Philips Semiconductors Product specification

TrenchMOS transistor PHP50N06LT, PHB50N06LT, PHD50N06LT

Logic level FET

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT

R

th j-mb

R

th j-a

ESD LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

C

ELECTRICAL CHARACTERISTICS

Tj= 25˚C unless otherwise specified

Thermal resistance junction - 1.2 K/W
to mounting base
Thermal resistance junction SOT78 package, in free air 60 - K/W
to ambient SOT404 and SOT428 package, pcb 50 - K/W

mounted, minimum footprint

Electrostatic discharge Human body model (100 pF, 1.5 kΩ)-2kV
capacitor voltage, all pins

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(BR)DSS

Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 55 - - V
voltage Tj = -55˚C 50 - - V

V

(BR)GSS

Gate-source breakdown IG = ±1 mA; 10 - - V
voltage

V

GS(TO)

Gate threshold voltage VDS = VGS; ID = 1 mA 1.0 1.5 2.0 V

Tj = 175˚C 0.5 - - V

Tj = -55˚C - - 2.3 V

R

DS(ON)

Drain-source on-state VGS = 5 V; ID = 12.5 A - 19 24 mΩ
resistance VGS = 10 V; ID = 12.5 A - 17 22 mΩ

Tj = 175˚C - - 50 mΩ
g
I

fs

GSS

Forward transconductance VDS = 25 V; ID = 25 A 15 40 - S
Gate source leakage current VGS = ±5 V; VDS = 0 V - 0.02 1 µA

Tj = 175˚C - - 20 µA

I

DSS

Zero gate voltage drain VDS = 55 V; VGS = 0 V; - 0.05 10 µA
current Tj = 175˚C - - 500 µA

Q
Q
Q

t
t
t
t

L
L

g(tot)
gs
gd

d on
r
d off
f

d
d

Total gate charge ID = 50 A; V

= 44 V; VGS = 5 V - 27 - nC

DD

Gate-source charge - 4 - nC
Gate-drain (Miller) charge - 14 - nC

Turn-on delay time VDD = 30 V; ID = 25 A; - 30 45 ns
Turn-on rise time VGS = 5 V; RG = 10 Ω - 80 130 ns
Turn-off delay time Resistive load - 95 135 ns
Turn-off fall time - 40 55 ns

Internal drain inductance Measured from tab to centre of die - 3.5 - nH
Internal drain inductance Measured from drain lead to centre of die - 4.5 - nH

(SOT78 package only)

L

s

Internal source inductance Measured from source lead to source - 7.5 - nH

bond pad

C

iss

C

oss

C

rss

Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 1500 2000 pF
Output capacitance - 300 360 pF
Feedback capacitance - 150 200 pF

September 1998 2 Rev 1.400

Philips Semiconductors Product specification

TrenchMOS transistor PHP50N06LT, PHB50N06LT, PHD50N06LT

Logic level FET

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tj = 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

S

I

SM

V

SD

t

rr

Q

rr

AVALANCHE LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

W

DSS

Continuous source current - - 50 A
(body diode)
Pulsed source current (body - - 200 A
diode)
Diode forward voltage IF = 25 A; VGS = 0 V - 0.95 1.2 V

IF = 40 A; VGS = 0 V - 1.0 - V

Reverse recovery time IF = 40 A; -dIF/dt = 100 A/µs; - 40 - ns
Reverse recovery charge VGS = -10 V; VR = 30 V - 0.07 - µC

Drain-source non-repetitive ID = 40 A; VDD ≤ 25 V; VGS = 5 V; - 80 mJ
unclamped inductive turn-off RGS = 50 Ω; Tmb = 25 ˚C
energy

PD%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140 160 180

Normalised Power Derating

Tmb / C

Fig.1. Normalised power dissipation.

PD% = 100⋅PD/P

D 25 ˚C

= f(Tmb)

ID%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140 160 180

Normalised Current Derating

Tmb / C

Fig.2. Normalised continuous drain current.

ID% = 100⋅ID/I

= f(Tmb); conditions: VGS ≥ 5 V

D 25 ˚C

September 1998 3 Rev 1.400

Philips Semiconductors Product specification

TrenchMOS transistor PHP50N06LT, PHB50N06LT, PHD50N06LT
Logic level FET

ID / A

1000

RDS(ON) = VDS / ID

100

tp = 10 us

100 us

10

1

1 10 100 1000

DC

VDS / V

1 ms
10 ms

100 ms

Fig.3. Safe operating area. Tmb = 25 ˚C

ID & IDM = f(VDS); IDM single pulse; parameter t

Transient thermal impedance, Zth (K/W)

10

1

0.5

0.2

0.1

0.1

0.05

0.01

0.001

0.02

0

10us 1ms 0.1s 10s

pulse width, tp (s)

p

t

P

D

D =

T

Fig.4. Transient thermal impedance.

Z

= f(t); parameter D = tp/T

th j-mb

7524-55

p

t
T

t

RDS(ON)/mOhm

40

35

30

25

20

15

10 15 20 25 30 35 40 45 50 55 60 65 70 75

Fig.6. Typical on-state resistance, Tj = 25 ˚C

p

100

ID/A

80

60

40

20

0

VGS/V = 4

ID/A

4.2

4.4

4.6

4.8
5

.

R

= f(ID); parameter V

DS(ON)

Tj/C = 175 25

01234567

VGS/V

GS

Fig.7. Typical transfer characteristics.

ID = f(VGS) ; conditions: VDS = 25 V; parameter T

j

Drain current, ID (A)

100

10

8

80

60

40

20

0

0246810

6

Drain-source voltage, VDS (V)

VGS = 5.0 V

2.6

4.8

4.6

4.4

4.2

4.0

3.8

3.6

3.4

3.2

3.0

2.8

Fig.5. Typical output characteristics, Tj = 25 ˚C

ID = f(VDS); parameter V

GS

.

Transconductance, gfs (S)

40

35

30

25

20

15

10

5

0 20406080100

Fig.8. Typical transconductance, Tj = 25 ˚C

Drain current, ID (A)

.

gfs = f(ID); conditions: VDS = 25 V

September 1998 4 Rev 1.400

Philips Semiconductors Product specification

TrenchMOS transistor PHP50N06LT, PHB50N06LT, PHD50N06LT
Logic level FET

a

2.5

2

1.5

1

0.5

-100 -50 0 50 100 150 200

BUK959-60

Rds(on) normlised to 25degC

Tmb / degC

Fig.9. Normalised drain-source on-state resistance.

a = R

DS(ON)/RDS(ON)25 ˚C

VGS(TO) / V

2.5
max.

2

typ.

1.5

min.

1

= f(Tj); ID = 25 A; VGS = 5 V

BUK959-60

3

2.5

2

1.5

Thousands pF

1

0.5

0

0.01 0.1 1 10 100

Fig.12. Typical capacitances, C

VDS/V

, C

iss

oss

C = f(VDS); conditions: VGS = 0 V; f = 1 MHz

6

VGS/V

5

4

3

2

VDS = 14V

VDS = 44V

, C

rss

.

Ciss

Coss
Crss

0.5

0

-100 -50 0 50 100 150 200
Tj / C

Fig.10. Gate threshold voltage.

V

= f(Tj); conditions: ID = 1 mA; VDS = V

GS(TO)

1E-01

1E-02

1E-03

1E-04

1E-05

1E-05

0 0.5 1 1.5 2 2.5 3

2% typ

Sub-Threshold Conduction

98%

Fig.11. Sub-threshold drain current.

ID = f(V

; conditions: Tj = 25 ˚C; VDS = V

GS)

GS

GS

1

0

0 5 10 15 20 25 30

QG/nC

Fig.13. Typical turn-on gate-charge characteristics.

V

= f(QG); conditions: ID = 50 A; parameter V

GS

100

IF/A

80

60

40

20

0

0 0.5 1 1.5

Tj/C = 175 25

VSDS/V

DS

Fig.14. Typical reverse diode current.

IF = f(V

); conditions: V

SDS

= 0 V; parameter T

GS

j

September 1998 5 Rev 1.400

Philips Semiconductors Product specification

TrenchMOS transistor PHP50N06LT, PHB50N06LT, PHD50N06LT
Logic level FET

WDSS%

120
110
100

90
80
70
60
50
40
30
20
10

0

20 40 60 80 100 120 140 160 180

Tmb / C

Fig.15. Normalised avalanche energy rating.

W

% = f(Tmb); conditions: ID = 40 A

DSS

L

VDS

VGS

0

RGS

T.U.T.

Fig.16. Avalanche energy test circuit.

W

= 0.5 ⋅ LI

DSS

2

D

⋅BV

DSS

/(BV

R 01

shunt

DSS−VDD

VDD

+

-

-ID/100

)

September 1998 6 Rev 1.400

Philips Semiconductors Product specification

TrenchMOS transistor PHP50N06LT, PHB50N06LT, PHD50N06LT

Logic level FET

MECHANICAL DATA

Dimensions in mm
Net Mass: 2 g

10,3
max

1,3

3,7

4,5

max

3,0 max

not tinned

1,3

max

(2x)

123

2,54 2,54

2,8

3,0

13,5

min

0,9 max (3x)

5,9

min

15,8

max

0,6

2,4

Fig.17. SOT78 (TO220AB); pin 2 connected to mounting base.

Notes

1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.

2. Refer to mounting instructions for SOT78 (TO220) envelopes.

3. Epoxy meets UL94 V0 at 1/8".

September 1998 7 Rev 1.400

Philips Semiconductors Product specification

TrenchMOS transistor PHP50N06LT, PHB50N06LT, PHD50N06LT

Logic level FET

MECHANICAL DATA

Dimensions in mm
Net Mass: 1.4 g

2.54 (x2)

MOUNTING INSTRUCTIONS

Dimensions in mm

10.3 max

11 max

15.4

0.85 max
(x2)

4.5 max

1.4 max

0.5

Fig.18. SOT404 : centre pin connected to mounting base.

11.5

2.5

9.0

17.5

2.0

3.8

5.08

Fig.19. SOT404 : soldering pattern for surface mounting

.

Notes

1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.

2. Epoxy meets UL94 V0 at 1/8".

September 1998 8 Rev 1.400

Philips Semiconductors Product specification

TrenchMOS transistor PHP50N06LT, PHB50N06LT, PHD50N06LT

Logic level FET

MECHANICAL DATA

Dimensions in mm : Net Mass: 1.4 g

seating plane

1

2.285 (x2)

Fig.20. SOT428 : centre pin connected to mounting base.

MOUNTING INSTRUCTIONS

6.73 max

tab

2

3

1.1

6.22 max

10.4 max

0.5 min

0.8 max
(x2)

Dimensions in mm

2.38 max

0.93 max

0.3

0.5

7.0

5.4

4 min

4.6

0.5

7.0

2.15

2.5

4.57

Fig.21. SOT428 : soldering pattern for surface mounting

1.5

.

Notes

1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.

2. Epoxy meets UL94 V0 at 1/8".

September 1998 9 Rev 1.400

Philips Semiconductors Product specification

TrenchMOS transistor PHP50N06LT, PHB50N06LT, PHD50N06LT

Logic level FET

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

 Philips Electronics N.V. 1998

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.

The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.

September 1998 10 Rev 1.400