Datasheet PHD50N03LT, PHP50N03LT Datasheet (Philips)

Philips Semiconductors Product specification

TrenchMOS transistor PHP50N03LT, PHB50N03LT, PHD50N03LT
Logic level FET

FEATURES SYMBOL QUICK REFERENCE DATA

• ’Trench’ technology V

d

= 25 V

DSS

• Very low on-state resistance

• Fast switching I

= 48 A

D

• Stable off-state characteristics

• High thermal cycling performance R

g

≤ 21 mΩ (VGS = 5 V)

DS(ON)

• Low thermal resistance

s

R

≤ 16 mΩ (VGS = 10 V)

DS(ON)

GENERAL DESCRIPTION

N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology.
The combinationofverylow on-state resistance and low switching losses make this device the optimum choice in high
speed computer motherboard d.c. to d.c. converters.

The PHP50N03LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB505N03LT is supplied in the SOT404 surface mounting package.
The PHD50N03LT is supplied in the SOT428 surface mounting package.

PINNING SOT78 (TO220AB) SOT404 SOT428

PIN DESCRIPTION

1 gate
2 drain

1

tab

tab

tab

3 source

tab drain

123

2

13

2

1

3

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DSS

V

DGR

V

GS

V

GSM

I

D

I

DM

P

D

Tj, T

Drain-source voltage Tj = 25 ˚C to 175˚C - 25 V
Drain-gate voltage Tj = 25 ˚C to 175˚C; RGS = 20 kΩ -25V
Gate-source voltage - ± 15 V
Pulsed gate-source voltage Tj ≤ 150˚C - ± 20 V
Continuous drain current Tmb = 25 ˚C; VGS = 10 V - 48 A

Tmb = 100 ˚C; VGS = 10 V - 34 A
Pulsed drain current Tmb = 25 ˚C - 180 A
Total power dissipation Tmb = 25 ˚C - 86 W
Operating junction and - 55 175 ˚C

stg

storage temperature

1 It is not possible to make connection to pin 2 of the SOT428 or SOT404 packages.

June 1998 1 Rev 1.500

Philips Semiconductors Product specification

TrenchMOS transistor PHP50N03LT, PHB50N03LT, PHD50N03LT

Logic level FET

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

R

th j-mb

R

th j-a

ELECTRICAL CHARACTERISTICS

Tj= 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(BR)DSS

V

GS(TO)

R

DS(ON)

g

fs

I

DSS

I

GSS

Q

g(tot)

Q

gs

Q

gd

t

d on

t

r

t

d off

t

f

L

d

L

d

L

s

C

iss

C

oss

C

rss

Thermal resistance junction - - 1.75 K/W
to mounting base
Thermal resistance junction SOT78 package, in free air - 60 - K/W
to ambient SOT404 and SOT428 packages, pcb - 50 - K/W

mounted, minimum footprint

Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 25 - - V
voltage Tj = -55˚C 22 - - V
Gate threshold voltage VDS = VGS; ID = 1 mA 1 1.5 2 V

Tj = 175˚C 0.5 - - V

Tj = -55˚C - - 2.3 V
Drain-source on-state VGS = 10 V; ID = 25 A - 13 16 mΩ
resistance VGS = 10 V; ID = 25 A (SOT428 package) - 15 18 mΩ

VGS = 5 V; ID = 25 A - 18 21 mΩ

VGS = 5 V; ID = 25 A; Tj = 175˚C - - 39 mΩ
Forward transconductance VDS = 25 V; ID = 25 A 8 27 - S
Zero gate voltage drain VDS = 25 V; VGS = 0 V; - 0.05 10 µA
current Tj = 175˚C - - 500 µA
Gate source leakage current VGS = ±5 V; VDS = 0 V - 10 100 nA

Total gate charge ID = 20 A; V

= 24 V; VGS = 10 V - 40 - nC

DD

Gate-source charge - 7 - nC
Gate-drain (Miller) charge - 10 - nC

Turn-on delay time VDD = 15 V; ID = 25 A; - 10 20 ns
Turn-on rise time VGS = 10 V; RG = 5 Ω -5075ns
Turn-off delay time Resistive load - 50 75 ns
Turn-off fall time - 30 45 ns

Internal drain inductance Measured tab to centre of die - 3.5 - nH
Internal drain inductance Measured from drain lead to centre of die - 4.5 - nH

(SOT78 package only)
Internal source inductance Measured from source lead to source - 7.5 - nH

bond pad
Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 1050 - pF

Output capacitance - 270 - pF
Feedback capacitance - 140 - pF

June 1998 2 Rev 1.500

Philips Semiconductors Product specification

TrenchMOS transistor PHP50N03LT, PHB50N03LT, PHD50N03LT

Logic level FET

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tj = 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

S

I

SM

V

SD

t

rr

Q

rr

AVALANCHE LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

W

DSS

Continuous source current - - 48 A
(body diode)
Pulsed source current (body - - 180 A
diode)
Diode forward voltage IF = 25 A; VGS = 0 V - 0.95 1.2 V

IF = 40 A; VGS = 0 V - 1.0 ­Reverse recovery time IF = 40 A; -dIF/dt = 100 A/µs; - 52 - ns

Reverse recovery charge VGS = -10 V; VR = 25 V - 0.08 - µC

Drain-source non-repetitive ID = 25 A; VDD ≤ 15 V; - 60 mJ
unclamped inductive turn-off VGS = 10 V; RGS = 50 Ω; Tmb = 25 ˚C
energy

PD%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140 160 180

Normalised Power Derating

Tmb / C

Fig.1. Normalised power dissipation.

PD% = 100⋅PD/P

D 25 ˚C

= f(Tmb)

ID%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140 160 180

Normalised Current Derating

Tmb / C

Fig.2. Normalised continuous drain current.

ID% = 100⋅ID/I

= f(Tmb); conditions: VGS ≥ 5 V

D 25 ˚C

June 1998 3 Rev 1.500

Philips Semiconductors Product specification

TrenchMOS transistor PHP50N03LT, PHB50N03LT, PHD50N03LT
Logic level FET

ID, Drain current (Amps)

1000

100

10

RDS(ON) = VDS/ID

DC

Tmb = 25 C

1

1 10 100

VDS, Drain-source voltage (Volts)

PHP50N03T

tp =
10 us

100 us

1 ms
10 ms

Fig.3. Safe operating area

ID & IDM = f(VDS); IDM single pulse; parameter t

Zth j-mb / (K/W)

10

D =

1

0.5

0.2

0.1

0.1

0.05

0.02

0.01

0

1E-07 1E-05 1E-03 1E-01 1E+01

t / s

p

t

P

D

7528-30

p

t

D =

T

T

t

Fig.4. Transient thermal impedance.

Z

= f(t); parameter D = tp/T

th j-mb

Drain-Source on resistance, RDS(on) (Ohms)

0.06

0.05

0.04

0.03

0.02

0.01

3 V

Tj = 25 C

0

0 1020304050607080

PHP45N03LT

3.5 V 4 V

ID, Drain current (Amps)

4.5 V

5 V

10 V

VGS = 15 V

Fig.6. Typical on-state resistance

R

p

Drain current, ID (A)

50

VDS = 25 V

40

30

20

10

0

0123456

= f(ID); parameter V

DS(ON)

175 C

Gate-source voltage, VGS (V)

Tj = 25 C

GS

PHP45N03LT

Fig.7. Typical transfer characteristics.

ID = f(VGS)

ID, Drain current (Amps)

80

15 V

10 V

70
60
50
40
30
20
10

0

0246810

5 V

VDS, Drain-Source voltage (Volts)

Tj = 25 C

PHP45N03LT

4.5 V

4 V

3.5 V

3 V

VGS = 2.5 V

Fig.5. Typical output characteristics

ID = f(VDS); parameter V

GS

Transconductance, gfs (S)

30

VDS = 25 V

25

20

175 C

15

10

5

0

0 1020304050

Drain current, ID (A)

Fig.8. Typical transconductance

gfs = f(ID)

PHP45N03LT

Tj = 25 C

June 1998 4 Rev 1.500

Philips Semiconductors Product specification

TrenchMOS transistor PHP50N03LT, PHB50N03LT, PHD50N03LT
Logic level FET

a

2

1.5

1

0.5

0

-100 0 100 200
Tj / C

30V TrenchMOS

15050-50

Fig.9. Normalised drain-source on-state resistance.

VGS(TO) / V

2.5

2

1.5

1

max.

typ.

min.

a = R

DS(ON)/RDS(ON)25 ˚C

= f(Tj)

BUK959-60

C / pF

10000

1000

100

0.1 1 10 100

Fig.12. Typical capacitances, C

VDS / V

, C

iss

oss

C = f(VDS); VGS = 0 V; f = 1 MHz

VGS, Gate-Source voltage (Volts)

15

VDD=24V
ID=20A
Tj = 25C

10

5

PHP50N03LT

9528-30

Ciss

Coss
Crss

, C

rss

.

0.5

0

-100 -50 0 50 100 150 200
Tj / C

Fig.10. Gate threshold voltage.

V

= f(Tj); conditions: ID = 1 mA; VDS = V

GS(TO)

1E-01

1E-02

1E-03

1E-04

1E-05

1E-05

0 0.5 1 1.5 2 2.5 3

2% typ

Sub-Threshold Conduction

98%

Fig.11. Sub-threshold drain current.

ID = f(V

; VDS = V

GS)

GS

GS

0

0 1020304050

Qg, Gate charge (nC)

Fig.13. Typical turn-on gate-charge characteristics.

V

= f(QG)

GS

IF / A

60

50

40

30

20

10

0

0 0.5 1 1.5 2

Tj / C = 175 25

VSDS / V

9528-30

Fig.14. Typical reverse diode current.

IF = f(V

SDS

)

June 1998 5 Rev 1.500

Philips Semiconductors Product specification

TrenchMOS transistor PHP50N03LT, PHB50N03LT, PHD50N03LT
Logic level FET

WDSS%

120
110
100

90
80
70
60
50
40
30
20
10

0

20 40 60 80 100 120 140 160 180

Tmb / C

Fig.15. Normalised avalanche energy rating.

W

% = f(Tmb)

DSS

L

VDS

VGS

0

RGS

T.U.T.

Fig.16. Avalanche energy test circuit.

W

= 0.5 ⋅LI

DSS

2

D

⋅BV

DSS

/(BV

R 01

shunt

DSS−VDD

VDD

+

-

-ID/100

)

June 1998 6 Rev 1.500

Philips Semiconductors Product specification

TrenchMOS transistor PHP50N03LT, PHB50N03LT, PHD50N03LT

Logic level FET

MECHANICAL DATA

Dimensions in mm
Net Mass: 2 g

10,3
max

1,3

3,7

4,5

max

3,0 max

not tinned

1,3

max

(2x)

123

2,54 2,54

2,8

3,0

13,5

min

0,9 max (3x)

5,9

min

15,8

max

0,6

2,4

Fig.17. SOT78 (TO220AB); pin 2 connected to mounting base.

Notes

1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.

2. Refer to mounting instructions for SOT78 (TO220) envelopes.

3. Epoxy meets UL94 V0 at 1/8".

June 1998 7 Rev 1.500

Philips Semiconductors Product specification

TrenchMOS transistor PHP50N03LT, PHB50N03LT, PHD50N03LT

Logic level FET

MECHANICAL DATA

Dimensions in mm
Net Mass: 1.4 g

2.54 (x2)

MOUNTING INSTRUCTIONS

Dimensions in mm

10.3 max

11 max

15.4

0.85 max
(x2)

4.5 max

1.4 max

0.5

Fig.18. SOT404 : centre pin connected to mounting base.

11.5

2.5

9.0

17.5

2.0

3.8

5.08

Fig.19. SOT404 : soldering pattern for surface mounting

.

Notes

1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.

2. Epoxy meets UL94 V0 at 1/8".

June 1998 8 Rev 1.500

Philips Semiconductors Product specification

TrenchMOS transistor PHP50N03LT, PHB50N03LT, PHD50N03LT

Logic level FET

MECHANICAL DATA

Dimensions in mm : Net Mass: 1.4 g

seating plane

1

2.285 (x2)

Fig.20. SOT428 : centre pin connected to mounting base.

MOUNTING INSTRUCTIONS

6.73 max

tab

2

3

1.1

6.22 max

10.4 max

0.5 min

0.8 max
(x2)

Dimensions in mm

2.38 max

0.93 max

0.3

0.5

7.0

5.4

4 min

4.6

0.5

7.0

2.15

2.5

4.57

Fig.21. SOT428 : soldering pattern for surface mounting

1.5

.

Notes

1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.

2. Epoxy meets UL94 V0 at 1/8".

June 1998 9 Rev 1.500

Philips Semiconductors Product specification

TrenchMOS transistor PHP50N03LT, PHB50N03LT, PHD50N03LT

Logic level FET

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

 Philips Electronics N.V. 1998

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.

The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.

June 1998 10 Rev 1.500