Philips php45n03lt DATASHEETS
Philips Semiconductors Product specification
TrenchMOS transistor PHP45N03LT, PHB45N03LT, PHD45N03LT
Logic level FET
FEATURES SYMBOL QUICK REFERENCE DATA
• ’Trench’ technology V
d
= 30 V
DSS
• Very low on-state resistance
• Fast switching I
= 45 A
D
• Stable off-state characteristics
• High thermal cycling performance R
g
≤ 24 mΩ (VGS = 5 V)
DS(ON)
• Low thermal resistance
s
R
≤ 21 mΩ (VGS = 10 V)
DS(ON)
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology.
Thedevicehasverylowon-stateresistance. Itis intended for use in dc to dc convertersand general purpose switching
applications.
The PHP45N03LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB45N03LT is supplied in the SOT404 surface mounting package.
The PHD45N03LT is supplied in the SOT428 surface mounting package.
PINNING SOT78 (TO220AB) SOT404 SOT428
PIN DESCRIPTION
1 gate
2 drain
1
tab
tab
tab
3 source
tab drain
123
2
13
2
1
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DSS
V
DGR
V
GS
I
D
I
DM
P
D
Tj, T
Drain-source voltage Tj = 25 ˚C to 175˚C - 30 V
Drain-gate voltage Tj = 25 ˚C to 175˚C; RGS = 20 kΩ -30V
Gate-source voltage - ± 15 V
Continuous drain current Tmb = 25 ˚C; VGS = 10 V - 45 A
Tmb = 100 ˚C; VGS = 10 V - 33 A
Pulsed drain current Tmb = 25 ˚C - 180 A
Total power dissipation Tmb = 25 ˚C - 86 W
Operating junction and - 55 175 ˚C
stg
storage temperature
1 It is not possible to make connection to pin 2 of the SOT428 or SOT404 packages.
January 1998 1 Rev 1.300
Philips Semiconductors Product specification
TrenchMOS transistor PHP45N03LT, PHB45N03LT, PHD45N03LT
Logic level FET
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
R
th j-mb
R
th j-a
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
(BR)DSS
V
GS(TO)
R
DS(ON)
g
fs
I
DSS
I
GSS
Q
g(tot)
Q
gs
Q
gd
t
d on
t
r
t
d off
t
f
L
d
L
d
L
s
C
iss
C
oss
C
rss
Thermal resistance junction - - 1.75 K/W
to mounting base
Thermal resistance junction SOT78 package, in free air - 60 - K/W
to ambient SOT404 and SOT428 packages, pcb - 50 - K/W
mounted, minimum footprint
Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 30 - - V
voltage Tj = -55˚C 27 - - V
Gate threshold voltage VDS = VGS; ID = 1 mA 1 1.5 2 V
Tj = 175˚C 0.5 - - V
Tj = -55˚C - - 2.3 V
Drain-source on-state VGS = 5 V; ID = 25 A - 20 24 mΩ
resistance VGS = 10 V; ID = 25 A - 16 21 mΩ
VGS = 5 V; ID = 25 A; Tj = 175˚C - - 45 mΩ
Forward transconductance VDS = 25 V; ID = 25 A 8 27 - S
Zero gate voltage drain VDS = 30 V; VGS = 0 V; - 0.05 10 µA
current Tj = 175˚C - - 500 µA
Gate source leakage current VGS = ±5 V; VDS = 0 V - 10 100 nA
Total gate charge ID = 40 A; V
= 24 V; VGS = 5 V - 23 - nC
DD
Gate-source charge - 7 - nC
Gate-drain (Miller) charge - 10 - nC
Turn-on delay time VDD = 15 V; ID = 25 A; - 12 20 ns
Turn-on rise time VGS = 5 V; RG = 5 Ω - 80 130 ns
Turn-off delay time Resistive load - 35 60 ns
Turn-off fall time - 31 45 ns
Internal drain inductance Measured tab to centre of die - 3.5 - nH
Internal drain inductance Measured from drain lead to centre of die - 4.5 - nH
(SOT78 package only)
Internal source inductance Measured from source lead to source - 7.5 - nH
bond pad
Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 1050 - pF
Output capacitance - 270 - pF
Feedback capacitance - 140 - pF
January 1998 2 Rev 1.300
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