Philips PHB42N03LT, PHP42N03LT Datasheet
Philips Semiconductors Product specification
TrenchMOS transistor PHP42N03LT, PHB42N03LT
Logic level FET
FEATURES SYMBOL QUICK REFERENCE DATA
• ’Trench’ technology V
d
= 30 V
DSS
• Very low on-state resistance
• Fast switching I
= 42 A
D
• Stable off-state characteristics
• High thermal cycling performance R
g
≤ 26 mΩ (VGS = 5 V)
DS(ON)
• Low thermal resistance
s
R
≤ 23 mΩ (VGS = 10 V)
DS(ON)
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology.
Thedevicehasverylowon-stateresistance. Itis intended for use in dc to dc convertersand general purpose switching
applications.
The PHP42N03LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB42N03LT is supplied in the SOT404 surface mounting package.
PINNING SOT78 (TO220AB) SOT404
PIN DESCRIPTION
1 gate
2 drain
1
3 source
tab drain
tab
123
tab
2
13
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DSS
V
DGR
V
GS
I
D
I
DM
P
D
Tj, T
June 1998 1 Rev 1.300
Drain-source voltage Tj = 25 ˚C to 175˚C - 30 V
Drain-gate voltage Tj = 25 ˚C to 175˚C; RGS = 20 kΩ -30V
Gate-source voltage - ± 15 V
Continuous drain current Tmb = 25 ˚C; VGS = 5 V - 42 A
Tmb = 100 ˚C; VGS = 5 V - 30 A
Pulsed drain current Tmb = 25 ˚C - 168 A
Total power dissipation Tmb = 25 ˚C - 86 W
Operating junction and - 55 175 ˚C
stg
storage temperature
Philips Semiconductors Product specification
TrenchMOS transistor PHP42N03LT, PHB42N03LT
Logic level FET
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
R
th j-mb
R
th j-a
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
(BR)DSS
V
GS(TO)
R
DS(ON)
g
fs
I
DSS
I
GSS
Q
g(tot)
Q
gs
Q
gd
t
d on
t
r
t
d off
t
f
L
d
L
d
L
s
C
iss
C
oss
C
rss
Thermal resistance junction - - 1.75 K/W
to mounting base
Thermal resistance junction SOT78 package, in free air - 60 - K/W
to ambient SOT404 package, pcb mounted, minimum - 50 - K/W
footprint
Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 30 - - V
voltage Tj = -55˚C 27 - - V
Gate threshold voltage VDS = VGS; ID = 1 mA 1 1.5 2 V
Tj = 175˚C 0.5 - - V
Tj = -55˚C - - 2.3 V
Drain-source on-state VGS = 10 V; ID = 25 A - 16 23 mΩ
resistance VGS = 5 V; ID = 25 A - 20 26 mΩ
VGS = 5 V; ID = 25 A; Tj = 175˚C - - 48 mΩ
Forward transconductance VDS = 25 V; ID = 25 A 8 27 - S
Zero gate voltage drain VDS = 30 V; VGS = 0 V; - 0.05 10 µA
current Tj = 175˚C - - 500 µA
Gate source leakage current VGS = ±5 V; VDS = 0 V - 10 100 nA
Total gate charge ID = 20 A; V
= 24 V; VGS = 10 V - 40 - nC
DD
Gate-source charge - 7 - nC
Gate-drain (Miller) charge - 10 - nC
Turn-on delay time VDD = 15 V; ID = 25 A; - 12 20 ns
Turn-on rise time VGS = 5 V; RG = 5 Ω - 80 130 ns
Turn-off delay time Resistive load - 35 60 ns
Turn-off fall time - 31 45 ns
Internal drain inductance Measured tab to centre of die - 3.5 - nH
Internal drain inductance Measured from drain lead to centre of die - 4.5 - nH
(SOT78 package only)
Internal source inductance Measured from source lead to source - 7.5 - nH
bond pad
Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 1050 - pF
Output capacitance - 270 - pF
Feedback capacitance - 140 - pF
June 1998 2 Rev 1.300
Philips Semiconductors Product specification
TrenchMOS transistor PHP42N03LT, PHB42N03LT
Logic level FET
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
I
S
I
SM
V
SD
t
rr
Q
rr
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
W
DSS
Continuous source current - - 45 A
(body diode)
Pulsed source current (body - - 180 A
diode)
Diode forward voltage IF = 25 A; VGS = 0 V - 0.95 1.2 V
IF = 40 A; VGS = 0 V - 1.0 Reverse recovery time IF = 40 A; -dIF/dt = 100 A/µs; - 52 - ns
Reverse recovery charge VGS = -10 V; VR = 25 V - 0.08 - µC
Drain-source non-repetitive ID = 25 A; VDD ≤ 15 V; - 60 mJ
unclamped inductive turn-off VGS = 10 V; RGS = 50 Ω; Tmb = 25 ˚C
energy
PD%
120
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140 160 180
Normalised Power Derating
Tmb / C
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/P
D 25 ˚C
= f(Tmb)
ID%
120
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140 160 180
Normalised Current Derating
Tmb / C
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/I
= f(Tmb); conditions: VGS ≥ 5 V
D 25 ˚C
June 1998 3 Rev 1.300
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