Philips PHB2N50E, PHD2N50E, PHP2N50E Datasheet

Philips Semiconductors Product specification

PowerMOS transistors PHP2N50E, PHB2N50E, PHD2N50E
Avalanche energy rated

FEATURES SYMBOL QUICK REFERENCE DATA

• Repetitive Avalanche Rated

• Fast switching V

d

= 500 V

DSS

• Stable off-state characteristics

• High thermal cycling performance I

• Low thermal resistance

g

s

R

DS(ON)

= 2 A

D

≤ 5 Ω

GENERAL DESCRIPTION

N-channel,enhancementmodefield-effect power transistor, intendedforusein off-line switched mode powersupplies,
T.V.andcomputer monitor powersupplies, d.c. to d.c.converters, motor controlcircuitsand general purpose switching
applications.

The PHP2N50E is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB2N50E is supplied in the SOT404 surface mounting package.
The PHD2N50E is supplied in the SOT428 surface mounting package.

PINNING SOT78 (TO220AB) SOT404 SOT428

PIN DESCRIPTION

1 gate
2 drain

1

tab

tab

tab

3 source

tab drain

123

2

13

2

1

3

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DSS

V

DGR

V

GS

I

D

I

DM

P

D

Tj, T

Drain-source voltage Tj = 25 ˚C to 150˚C - 500 V
Drain-gate voltage Tj = 25 ˚C to 150˚C; RGS = 20 kΩ - 500 V
Gate-source voltage - ± 30 V
Continuous drain current Tmb = 25 ˚C; VGS = 10 V - 2 A

Tmb = 100 ˚C; VGS = 10 V - 1.3 A
Pulsed drain current Tmb = 25 ˚C - 8 A
Total dissipation Tmb = 25 ˚C - 50 W
Operating junction and - 55 150 ˚C

stg

storage temperature range

1 It is not possible to make connection to pin 2 of the SOT428 or SOT404 packages.

August 1998 1 Rev 1.100

Philips Semiconductors Product specification

PowerMOS transistors PHP2N50E, PHB2N50E, PHD2N50E
Avalanche energy rated

AVALANCHE ENERGY LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

E

AS

E

AR

IAS, I

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

R

th j-mb

R

th j-a

Non-repetitive avalanche Unclamped inductive load, IAS = 0.7 A; - 130 mJ
energy tp = 0.41 ms; Tj prior to avalanche = 25˚C;

VDD ≤ 50 V; RGS = 50 Ω; VGS = 10 V; refer

to fig:17
Repetitive avalanche energy2IAR = 2 A; tp = 1 µs; Tj prior to - 3.2 mJ

avalanche = 25˚C; RGS = 50 Ω; VGS = 10 V;

refer to fig:18
Repetitive and non-repetitive - 2 A

AR

avalanche current

Thermal resistance junction - - 2.5 K/W
to mounting base
Thermal resistance junction SOT78 package, in free air - 60 - K/W
to ambient SOT404 and SOT428 packages, pcb - 50 - K/W

mounted, minimum footprint

2 pulse width and repetition rate limited by Tj max.

August 1998 2 Rev 1.100

Philips Semiconductors Product specification

PowerMOS transistors PHP2N50E, PHB2N50E, PHD2N50E
Avalanche energy rated

ELECTRICAL CHARACTERISTICS

Tj = 25 ˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(BR)DSS

∆V
∆T

R

DS(ON)

V

GS(TO)

g

fs

I

DSS

I

GSS

Q

g(tot)

Q

gs

Q

gd

t

d(on)

t

r

t

d(off)

t

f

L

d

L

d

L

s

C

iss

C

oss

C

rss

(BR)DSS

j

Drain-source breakdown VGS = 0 V; ID = 0.25 mA 500 - - V
voltage

/ Drain-source breakdown VDS = VGS; ID = 0.25 mA - 0.1 - %/K

voltage temperature
coefficient
Drain-source on resistance VGS = 10 V; ID = 1 A - 3.1 5 Ω
Gate threshold voltage VDS = VGS; ID = 0.25 mA 2.0 3.0 4.0 V
Forward transconductance VDS = 30 V; ID = 1 A 0.5 1.3 - S
Drain-source leakage current VDS = 500 V; VGS = 0 V - 1 25 µA

VDS = 400 V; VGS = 0 V; Tj = 125 ˚C - 30 250 µA
Gate-source leakage current VGS = ±30 V; VDS = 0 V - 10 200 nA

Total gate charge ID = 2 A; V

= 400 V; VGS = 10 V - 20 25 nC

DD

Gate-source charge - 2 3 nC
Gate-drain (Miller) charge - 12 15 nC

Turn-on delay time VDD = 250 V; RD = 120 Ω; - 10 - ns
Turn-on rise time RG = 24 Ω -20-ns
Turn-off delay time - 60 - ns
Turn-off fall time - 20 - ns

Internal drain inductance Measured from tab to centre of die - 3.5 - nH
Internal drain inductance Measured from drain lead to centre of die - 4.5 - nH

(SOT78 package only)
Internal source inductance Measured from source lead to source - 7.5 - nH

bond pad
Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 236 - pF

Output capacitance - 40 - pF
Feedback capacitance - 22 - pF

SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS

Tj = 25 ˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

S

I

SM

V

SD

t

rr

Q

rr

Continuous source current Tmb = 25˚C - - 2 A
(body diode)
Pulsed source current (body Tmb = 25˚C - - 8 A
diode)
Diode forward voltage IS = 2 A; VGS = 0 V - - 1.2 V

Reverse recovery time IS = 2 A; VGS = 0 V; dI/dt = 100 A/µs - 300 - ns
Reverse recovery charge - 2.1 - µC

August 1998 3 Rev 1.100

Philips Semiconductors Product specification

PowerMOS transistors PHP2N50E, PHB2N50E, PHD2N50E
Avalanche energy rated

PD%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140

Normalised Power Derating

Tmb / C

Fig.1. Normalised power dissipation.

PD% = 100⋅PD/P

ID%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140

Tmb / C

= f(Tmb)

D 25 ˚C

Normalised Current Derating

Fig.2. Normalised continuous drain current.

ID% = 100⋅ID/I

= f(Tmb); conditions: VGS ≥ 10 V

D 25 ˚C

Zth j-mb / (K/W)

10

D=

0.5

1

0.2

0.1

0.05

0.1

0.01

0.02

0

10us 1ms 0.1s 10ms

t / s

t

P

D

p

p

t

D =

T

t

T

Fig.4. Transient thermal impedance.

Z

= f(t); parameter D = tp/T

th j-mb

ID, Drain current (Amps)

6

Tj = 25 C

5

4

3

2

1

0

0 5 10 15 20 25 30

VDS, Drain-Source voltage (Volts)

Fig.5. Typical output characteristics

ID = f(VDS); parameter V

PHP2N50

20 V

10 V

7 V

6.5 V
6 V

5.5 V

VGS = 5 V

.

GS

Drain current, ID (Amps)

10

Tmb = 25 C

RDS(ON) = VDS/ID

1

DC

0.1

0.01
10 100 1000

Drain-source voltage, VDS (Volts)

Fig.3. Safe operating area. Tmb = 25 ˚C

ID & IDM = f(VDS); IDM single pulse; parameter t

PHP2N50

tp =

10 us

100us

1 ms

10 ms

100ms

Drain-Source on resistance, RDS(ON) (Ohms)

10

8

6

4

2

0

012345

5.5 V5V

6 V

Drain current, ID (Amps)

6.5 V

7 V

Fig.6. Typical on-state resistance

R

p

= f(ID); parameter V

DS(ON)

PHP2N50

Tj = 25 C

10 V

VGS = 20 V

.

GS

August 1998 4 Rev 1.100

Philips Semiconductors Product specification

PowerMOS transistors PHP2N50E, PHB2N50E, PHD2N50E
Avalanche energy rated

Drain current, ID (A)

6

VDS > ID x RDS(on)max

5

4

3

2

1

0

0246810

150 C

Gate-source voltage, VGS (V)

Tj = 25 C

PHP2N50

Fig.7. Typical transfer characteristics.

ID = f(VGS); parameter T

Transconductance, gfs (S)

2.5
VDS > ID x RDS(on)max

2

1.5

1

Tj = 25 C

150 C

j

PHP2N50

VGS(TO) / V

4

3

2

1

0

-60 -40 -20 0 20 40 60 80 100 120 140

max.

typ.

min.

Tj / C

Fig.10. Gate threshold voltage

V

= f(Tj); conditions: ID = 0.25 mA; VDS = V

GS(TO)

1E-01

1E-02

1E-03

1E-04

ID / A

SUB-THRESHOLD CONDUCTION

2 %

typ

.

GS

98 %

0.5

0

0123456

Fig.8. Typical transconductance

a

2

1

0

-60 -40 -20 0 20 40 60 80 100 120 140

Drain current, ID (A)

gfs = f(ID); parameter T

Normalised RDS(ON) = f(Tj)

Tj / C

.

j

Fig.9. Normalised drain-source on-state resistance.

a = R

DS(ON)/RDS(ON)25 ˚C

= f(Tj); ID = 1 A; VGS = 10 V

1E-05

1E-06

0 1 2 3 4

VGS / V

Fig.11. Sub-threshold drain current.

ID = f(V

Capacitances, Ciss, Coss, Crss (pF)

1000

100

10

1

1 10 100 1000

Fig.12. Typical capacitances, C

C = f(VDS); conditions: VGS = 0 V; f = 1 MHz

; conditions: Tj = 25 ˚C; VDS = V

GS)

Ciss

Coss

Crss

Drain-source voltage, VDS (V)

, C

iss

PHP2N50

oss

, C

GS

rss

.

August 1998 5 Rev 1.100

Philips Semiconductors Product specification

PowerMOS transistors PHP2N50E, PHB2N50E, PHD2N50E
Avalanche energy rated

Gate-Source voltage, VGS (Volts)

20

ID = 2 A

15

10

5

0

0 10203040

Gate charge, Qg (nC)

300 V

200 V

PHP2N50

VDD = 400 V

Fig.13. Typical turn-on gate-charge characteristics.

V

= f(QG); parameter V

GS

Switching times, td(on), tr, td(off), tf (ns)

1000

VDD = 250V
RD = 120 Ohms
Tj = 25 C

100

td(off)

tr

10

tf

td(on)

1

0 20406080100

Gate resistance, RG (Ohms)

Fig.14. Typical switching times; t

d(on)

DS

, tr, t

PHP2N50

, tf = f(RG)

d(off)

Source-drain diode current, IF(A)

10

VGS = 0 V

8

150 C

6

4

2

0

0 0.5 1 1.5

Source-Drain voltage, VSDS (V)

PHP2N50

Tj = 25 C

Fig.16. Source-Drain diode characteristic.

IF = f(V

Non-repetitive Avalanche current, IAS (A)

10

1

VDS

0.1

0.01
1E-06 1E-05 1E-04 1E-03 1E-02

tp

ID

); parameter T

SDS

Tj prior to avalanche = 25 C

125 C

Avalanche time, tp (s)

j

PHP2N50E

Fig.17. Maximum permissible non-repetitive

avalanche current (IAS) versus avalanche time (tp);

unclamped inductive load

Normalised Drain-source breakdown voltage

1.15

V(BR)DSS @ Tj
V(BR)DSS @ 25 C

1.1

1.05

1

0.95

0.9

0.85

-100 -50 0 50 100 150
Tj, Junction temperature (C)

Fig.15. Normalised drain-source breakdown voltage

V

(BR)DSS/V(BR)DSS 25 ˚C

= f(Tj)

;

Maximum Repetitive Avalanche Current, IAR (A)

10

1

0.1

0.01

0.001
1E-06 1E-05 1E-04 1E-03 1E-02

Tj prior to avalanche = 25 C

125 C

PHP2N50E

Avalanche time, tp (s)

Fig.18. Maximum permissible repetitive avalanche

current (IAR) versus avalanche time (tp)

August 1998 6 Rev 1.100

Philips Semiconductors Product specification

PowerMOS transistors PHP2N50E, PHB2N50E, PHD2N50E
Avalanche energy rated

MECHANICAL DATA

Dimensions in mm
Net Mass: 2 g

10,3
max

1,3

3,7

4,5
max

3,0 max

not tinned

1,3

max

(2x)

123

2,54 2,54

2,8

3,0

13,5

min

0,9 max (3x)

5,9

min

15,8

max

0,6

2,4

Fig.19. SOT78 (TO220AB); pin 2 connected to mounting base.

Notes

1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.

2. Refer to mounting instructions for SOT78 (TO220) envelopes.

3. Epoxy meets UL94 V0 at 1/8".

August 1998 7 Rev 1.100

Philips Semiconductors Product specification

PowerMOS transistors PHP2N50E, PHB2N50E, PHD2N50E
Avalanche energy rated

MECHANICAL DATA

Dimensions in mm
Net Mass: 1.4 g

2.54 (x2)

MOUNTING INSTRUCTIONS

Dimensions in mm

10.3 max

11 max

15.4

0.85 max
(x2)

4.5 max

1.4 max

0.5

Fig.20. SOT404 : centre pin connected to mounting base.

11.5

2.5

9.0

17.5

2.0

3.8

5.08

Fig.21. SOT404 : soldering pattern for surface mounting

.

Notes

1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.

2. Epoxy meets UL94 V0 at 1/8".

August 1998 8 Rev 1.100

Philips Semiconductors Product specification

PowerMOS transistors PHP2N50E, PHB2N50E, PHD2N50E
Avalanche energy rated

MECHANICAL DATA

Dimensions in mm : Net Mass: 1.4 g

seating plane

1

2.285 (x2)

Fig.22. SOT428 : centre pin connected to mounting base.

MOUNTING INSTRUCTIONS

6.73 max

tab

2

3

1.1

6.22 max

10.4 max

0.5 min

0.8 max
(x2)

Dimensions in mm

2.38 max

0.93 max

0.3

0.5

7.0

5.4

4 min

4.6

0.5

7.0

2.15

2.5

4.57

Fig.23. SOT428 : soldering pattern for surface mounting

1.5

.

Notes

1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.

2. Epoxy meets UL94 V0 at 1/8".

August 1998 9 Rev 1.100

Philips Semiconductors Product specification

PowerMOS transistors PHP2N50E, PHB2N50E, PHD2N50E
Avalanche energy rated

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

 Philips Electronics N.V. 1998

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.

The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.

August 1998 10 Rev 1.100