Philips PHP24N03LT Datasheet
Philips Semiconductors Product specification
TrenchMOS transistor PHP24N03LT, PHB24N03LT
Logic level FET
FEATURES SYMBOL QUICK REFERENCE DATA
• ’Trench’ technology V
d
= 30 V
DSS
• Very low on-state resistance
• Fast switching I
= 24 A
D
• Stable off-state characteristics
• High thermal cycling performance R
• Low thermal resistance
g
R
s
≤ 56 mΩ (VGS = 5 V)
DS(ON)
≤ 50 mΩ (VGS = 10 V)
DS(ON)
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology.
Thedevicehasverylowon-stateresistance. Itis intended for use in dc to dc convertersand general purpose switching
applications.
The PHP24N03LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB24N03LT is supplied in the SOT404 surface mounting package.
PINNING SOT78 (TO220AB) SOT404
PIN DESCRIPTION
1 gate
2 drain
1
3 source
tab drain
tab
123
tab
2
13
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DSS
V
DGR
V
GS
I
D
I
DM
P
D
Tj, T
1 It is not possible to make connection to pin 2 of the SOT404 package.
January 1998 1 Rev 1.300
Drain-source voltage Tj = 25 ˚C to 175˚C - 30 V
Drain-gate voltage Tj = 25 ˚C to 175˚C; RGS = 20 kΩ -30V
Gate-source voltage - ± 13 V
Continuous drain current Tmb = 25 ˚C; VGS = 5 V - 24 A
Tmb = 100 ˚C; VGS = 5 V - 20 A
Pulsed drain current Tmb = 25 ˚C - 96 A
Total power dissipation Tmb = 25 ˚C - 60 W
Operating junction and - 55 175 ˚C
stg
storage temperature
Philips Semiconductors Product specification
TrenchMOS transistor PHP24N03LT, PHB24N03LT
Logic level FET
ESD LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
C
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
R
th j-mb
R
th j-a
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
Electrostatic discharge Human body model (100 pF, 1.5 kΩ)-2kV
capacitor voltage, all pins
Thermal resistance junction - - 2.5 K/W
to mounting base
Thermal resistance junction SOT78 package, in free air - 60 - K/W
to ambient SOT404 package, pcb mounted, minimum - 50 - K/W
footprint
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
(BR)DSS
Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 30 - - V
voltage Tj = -55˚C 27 - - V
V
(BR)GSS
Gate-source breakdown IG = 1 mA 10 - - V
voltage
V
GS(TO)
Gate threshold voltage VDS = VGS; ID = 1 mA 1 1.5 2 V
Tj = 175˚C 0.5 - - V
Tj = -55˚C - - 2.3 V
R
DS(ON)
Drain-source on-state VGS = 5 V; ID = 25 A - 50 56 mΩ
resistance VGS = 10 V; ID = 25 A - 45 50 mΩ
VGS = 5 V; ID = 12 A; Tj = 175˚C - - 104 mΩ
g
I
fs
GSS
Forward transconductance VDS = 25 V; ID = 12 A 3 5 - S
Gate-source leakage current VGS = ±5 V; VDS = 0 V; - 0.02 1 µA
Tj = 175˚C - - 10 µA
I
DSS
Zero gate voltage drain VDS = 30 V; VGS = 0 V; - 0.05 10 µA
current Tj = 175˚C - - 500 µA
Q
Q
Q
t
t
t
t
L
L
g(tot)
gs
gd
d on
r
d off
f
d
d
Total gate charge ID = 10 A; V
= 30 V; VGS = 5 V - 9 - nC
DD
Gate-source charge - 2.3 - nC
Gate-drain (Miller) charge - 5.4 - nC
Turn-on delay time VDD = 30 V; ID = 25 A; - 12 - ns
Turn-on rise time VGS = 5 V; RG = 10 Ω -50-ns
Turn-off delay time Resistive load - 30 - ns
Turn-off fall time - 36 - ns
Internal drain inductance Measured tab to centre of die - 3.5 - nH
Internal drain inductance Measured from drain lead to centre of die - 4.5 - nH
(SOT78 package only)
L
s
Internal source inductance Measured from source lead to source - 7.5 - nH
bond pad
C
iss
C
oss
C
rss
Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 460 - pF
Output capacitance - 144 - pF
Feedback capacitance - 78 - pF
January 1998 2 Rev 1.300
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