Page 1
DISCRETE SEMICONDUCTORS
DATA SH EET
M3D315
PHP222
Dual P-channel enhancement
mode MOS transistor
Preliminary specification
Supersedes data of 1998 Mar 24
File under Discrete Semiconductors, SC13
1998 Apr 01
Page 2
Philips Semiconductors Preliminary specification
Dual P-channel enhancement
mode MOS transistor
FEATURES
• Very low on-state resistance
• High-speed switching
• No secondary breakdown
• Low threshold.
APPLICATIONS
• Power management
• DC-DC converters
• General purpose switch.
DESCRIPTION
Two P-channel enhancement mode MOS transistors in an
8-pin SOT96-1 (SO8) SMD plastic package.
CAUTION
The device is supplied in an antistatic package.
The gate-source input must be protected against static
discharge during transport or handling.
PINNING - SOT96-1 (SO8)
PIN SYMBOL DESCRIPTION
1s
2g
3s
4g
5d
6d
7d
8d
handbook, halfpage
58
1
4
MAM119
1
1
2
2
2
2
1
1
source 1
gate 1
source 2
gate 2
drain 2
drain 2
drain 1
drain 1
d
d
1
1
gs
1
PHP222
d
2
2
1
d
2
gs
2
Fig.1 Simplified outline and symbol.
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DS
V
SD
V
GSO
V
GSth
I
D
R
DSon
P
tot
drain-source voltage (DC) −−30 V
source-drain diode forward voltage IS= −1.25 A; VGD=0 −−1.3 V
gate-source voltage (DC) open drain −±8V
gate-source threshold voltage ID= −1 mA; VDS=V
GS
−0.4 − V
drain current (DC) Ts=80°C −−3.2 A
drain-source on-state resistance ID= −1.6 A; VGS= −2.5 V − 220 mΩ
total power dissipation Ts=80°C − 3.5 W
1998 Apr 01 2
Page 3
Philips Semiconductors Preliminary specification
Dual P-channel enhancement
PHP222
mode MOS transistor
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
Per P-channel
V
DS
V
GSO
I
D
I
DM
P
tot
T
stg
T
j
Source-drain diode
I
S
I
SM
drain-source voltage (DC) −−30 V
gate-source voltage (DC) open drain −±8V
drain current (DC) Ts=80°C; note 1 −−3.2 A
peak drain current note 2 −−12.8 A
total power dissipation Ts=80°C; note 3 − 3.5 W
T
=25°C; note 4 − 2.63 W
amb
T
=25°C; note 5 − 1.14 W
amb
=25°C; note 6 − 1.56 W
T
amb
storage temperature −55 +150 °C
operating junction temperature −55 +150 °C
source current (DC) Ts=80°C −−2.7 A
peak pulsed source current note 2 −−10.8 A
Notes
is the temperature at the soldering point of the drain lead.
1. T
s
2. Pulse width and duty cycle limited by maximum junction temperature.
3. Maximum permissible dissipation per MOS transistor. Both devices may be loaded up to 3.5 W at the same time.
4. Maximum permissible dissipation per MOS transistor. Device mounted on a printed-circuit board with an R
th a-tp
(ambient to tie-point) of 27.5 K/W.
5. Maximum permissible dissipation per MOS transistor. Device mounted on a printed-circuit board with an R
th a-tp
(ambient to tie-point) of 90 K/W.
6. Maximum permissible dissipation if only one MOS transistor dissipates. Device mounted on a printed-circuit board
with an R
(ambient to tie-point) of 90 K/W.
th a-tp
THERMAL CHARACTERISTICS
SYMBOL PARAMETER VALUE UNIT
R
th j-s
thermal resistance from junction to soldering point 20 K/W
1998 Apr 01 3
Page 4
Philips Semiconductors Preliminary specification
Dual P-channel enhancement
PHP222
mode MOS transistor
CHARACTERISTICS
T
=25°C unless otherwise specified.
j
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Per P-channel
V
(BR)DSS
V
GSth
I
DSS
I
GSS
R
DSon
C
iss
C
oss
C
rss
Q
G
Q
GS
Q
GD
Switching times
t
d(on)
t
r
t
on
t
d(off)
t
f
t
off
Source-drain diode
V
SD
t
rr
drain-source breakdown voltage VGS= 0; ID= −10 µA −30 −− V
gate-source threshold voltage VGS=VDS; ID= −1mA −0.4 −− V
drain-source leakage current VGS= 0; VDS= −24 V −−−100 nA
gate leakage current VGS= ±8 V; VDS=0 −−±100 nA
drain-source on-state resistance VGS= −4.5 V; ID= −1.6 A −−200 mΩ
V
= −2.5 V; ID= −1.6 A −−220 mΩ
GS
V
= −1.8 V; ID= −0.8 A −−250 mΩ
GS
input capacitance VGS= 0; VDS= −24 V; f = 1 MHz − 696 − pF
output capacitance VGS= 0; VDS= −24 V; f = 1 MHz − 163 − pF
reverse transfer capacitance VGS= 0; VDS= −24 V; f = 1 MHz − 73 − pF
total gate charge VGS= −4.5 V; VDD= −15 V;
ID= −1 A; T
gate-source charge VDD= −15 V; ID= −1 A; T
gate-drain charge VDD= −15 V; ID= −1 A; T
amb
=25°C
=25°C − 0.7 − nC
amb
=25°C − 4.1 − nC
amb
turn-on delay time VGS=0to−8 V; VDD= −20 V;
rise time − 4 − ns
ID= −1 A; R
gen
=6Ω
− 16 − nC
− 3.5 − ns
turn-on switching time − 7.5 − ns
turn-off delay time VGS= −8to0V; VDD= −20 V;
fall time − 35 − ns
ID= −1 A; R
gen
=6Ω
− 90 − ns
turn-off switching time − 125 − ns
source-drain diode forward
VGD= 0; IS= −1.25 A −−−1.3 V
voltage
reverse recovery time IS= −1.25 A; di/dt = 100 A/µs − 65 − ns
1998 Apr 01 4
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Philips Semiconductors Preliminary specification
Dual P-channel enhancement
mode MOS transistor
PACKAGE OUTLINE
SO8: plastic small outline package; 8 leads; body width 3.9 mm
D
c
y
Z
8
5
PHP222
SOT96-1
E
H
E
A
X
v M
A
A
pin 1 index
1
e
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
mm
A
max.
1.75
0.069
A
0.25
0.10
0.010
0.004
1
A2A
1.45
1.25
0.057
0.049
0.25
0.01
b
3
p
0.49
0.25
0.36
0.19
0.019
0.0100
0.014
0.0075
UNIT
inches
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
4
w M
b
p
0 2.5 5 mm
scale
(1)E(2)
cD
5.0
4.8
0.20
0.19
eHELLpQZywv θ
4.0
1.27
3.8
0.16
0.050
0.15
2
A
6.2
5.8
0.244
0.228
Q
3
A
θ
0.25 0.10.25
0.010.010.041 0.004
(1)
0.7
0.3
0.028
0.012
o
8
o
0
L
p
L
0.7
0.6
0.028
0.024
(A )
1
detail X
1.0
1.05
0.4
0.039
0.016
OUTLINE
VERSION
SOT96-1
IEC JEDEC EIAJ
076E03S MS-012AA
REFERENCES
1998 Apr 01 5
EUROPEAN
PROJECTION
ISSUE DATE
95-02-04
97-05-22
Page 6
Philips Semiconductors Preliminary specification
Dual P-channel enhancement
PHP222
mode MOS transistor
DEFINITIONS
Data Sheet Status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1998 Apr 01 6
Page 7
Philips Semiconductors Preliminary specification
Dual P-channel enhancement
mode MOS transistor
PHP222
NOTES
1998 Apr 01 7
Page 8
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© Philips Electronics N.V. 1998 SCA59
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Printed in The Netherlands 135108/00/03/pp8 Date of release: 1998 Apr 01 Document order number: 9397 75003657
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