Philips PHP21N06LT Datasheet

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PHP21N06LT, PHB21N06LT
Logic level FET PHD21N06LT

FEATURES SYMBOL QUICK REFERENCE DATA

• ’Trench’ technology V

d

= 55 V

DSS

• Low on-state resistance

• Fast switching I

= 19 A

D

• Logic level compatible

g

R

R

s

≤ 75 mΩ (VGS = 5 V)

DS(ON)

≤ 70 mΩ (VGS = 10 V)

DS(ON)

GENERAL DESCRIPTION

N-channelenhancementmode,logic level, field-effect power transistor in a plastic envelopeusing’trench’technology.
Applications:-

• d.c. to d.c. converters

• switched mode power supplies
The PHP21N06LT is supplied in the SOT78 (TO220AB) conventional leaded package.

The PHB21N06LT is supplied in the SOT404 (D2PAK) surface mounting package.
The PHD21N06LT is supplied in the SOT428 (DPAK) surface mounting package.

PINNING SOT78 (TO220AB) SOT404 (D2PAK) SOT428 (DPAK)

PIN DESCRIPTION

1 gate
2 drain

1

3 source

tab drain

tab

123

tab

2

13

tab

123

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DSS

V

DGR

V

GS

V

GSM

I

D

I

DM

P

D

Tj, T

1 It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages.

August 1999 1 Rev 1.500

Drain-source voltage Tj = 25 ˚C to 175˚C - 55 V
Drain-gate voltage Tj = 25 ˚C to 175˚C; RGS = 20 kΩ -55V
Gate-source voltage - ± 15 V
Pulsed gate-source voltage Tj ≤ 150˚C - ± 20 V
Continuous drain current Tmb = 25 ˚C - 19 A

Tmb = 100 ˚C - 13 A
Pulsed drain current Tmb = 25 ˚C - 76 A
Total power dissipation Tmb = 25 ˚C - 56 W
Operating junction and - 55 175 ˚C

stg

storage temperature

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PHP21N06LT, PHB21N06LT

Logic level FET PHD21N06LT

AVALANCHE ENERGY LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

E

AS

I

AS

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT

R

th j-mb

R

th j-a

Non-repetitive avalanche Unclamped inductive load, IAS = 9.7 A; - 34 mJ
energy tp = 100 µs; Tj prior to avalanche = 25˚C;

VDD ≤ 25 V; RGS = 50 Ω; VGS = 5 V; refer to

fig:15
Peak non-repetitive - 19 A
avalanche current

Thermal resistance junction - 2.7 K/W
to mounting base
Thermal resistance junction SOT78 package, in free air 60 - K/W
to ambient SOT428 and SOT404 package, pcb 50 - K/W

mounted, minimum footprint

ELECTRICAL CHARACTERISTICS

Tj= 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(BR)DSS

V

GS(TO)

R

DS(ON)

g

fs

I

GSS

I

DSS

Q

g(tot)

Q

gs

Q

gd

t

d on

t

r

t

d off

t

f

L

d

L

d

L

s

C

iss

C

oss

C

rss

Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 55 - - V
voltage Tj = -55˚C 50 - - V
Gate threshold voltage VDS = VGS; ID = 1 mA 1.0 1.5 2.0 V

Tj = 175˚C 0.5 - - V

Tj = -55˚C - - 2.3 V
Drain-source on-state VGS = 10 V; ID = 10 A - 55 70 mΩ
resistance VGS = 5 V; ID = 10 A - 60 75 mΩ

Tj = 175˚C - - 158 mΩ
Forward transconductance VDS = 25 V; ID = 10 A 5 13 - S
Gate source leakage current VGS = ±5 V; VDS = 0 V - 10 100 nA
Zero gate voltage drain VDS = 55 V; VGS = 0 V; - 0.05 10 µA
current Tj = 175˚C - - 500 µA

Total gate charge ID = 20 A; V

= 44 V; VGS = 5 V - 9.4 - nC

DD

Gate-source charge - 2.2 - nC
Gate-drain (Miller) charge - 5.4 - nC

Turn-on delay time VDD = 30 V; RD = 1.2 Ω;-715ns
Turn-on rise time RG = 10 Ω; VGS = 5 V - 88 120 ns
Turn-off delay time Resistive load - 25 40 ns
Turn-off fall time - 25 45 ns

Internal drain inductance Measured from tab to centre of die - 3.5 - nH
Internal drain inductance Measured from drain lead to centre of die - 4.5 - nH

(SOT78 package only)

Internal source inductance Measured from source lead to source - 7.5 - nH

bond pad

Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 466 650 pF
Output capacitance - 95 135 pF
Feedback capacitance - 71 85 pF

August 1999 2 Rev 1.500

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PHP21N06LT, PHB21N06LT

Logic level FET PHD21N06LT

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tj = 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

S

I

SM

V

SD

t

rr

Q

rr

Continuous source current - - 19 A
(body diode)
Pulsed source current (body - - 76 A
diode)
Diode forward voltage IF = 20 A; VGS = 0 V - 1.2 1.5 V

Reverse recovery time IF = 20 A; -dIF/dt = 100 A/µs; - 43 - ns
Reverse recovery charge VGS = 0 V; VR = 30 V - 94 - nC

Normalised Power Derating, PD (%)

100

90
80
70
60
50
40
30
20
10

0

0 25 50 75 100 125 150 175

Mounting Base temperature, Tmb (C)

Fig.1. Normalised power dissipation.

PD% = 100⋅PD/P

Normalised Current Derating, ID (%)

100

90
80
70
60
50
40
30
20
10

0

0 25 50 75 100 125 150 175

Mounting Base temperature, Tmb (C)

D 25 ˚C

= f(Tmb)

Peak Pulsed Drain Current, IDM (A)

100

RDS(on) = VDS/ ID

tp = 10 us

10

D.C.

1

0.1
1 10 100

Drain-Source Voltage, VDS (V)

100 ms

Fig.3. Safe operating area. Tmb = 25 ˚C

ID & IDM = f(VDS); IDM single pulse; parameter t

Transient thermal impedance, Zth j-mb (K/W)

10

D = 0.5

1

0.2

0.1

0.05

0.02

0.1
single pulse

0.01
1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00

Pulse width, tp (s)

P

D

tp

D = tp/T

T

100 us

1 ms
10 ms

p

Fig.2. Normalised continuous drain current.

ID% = 100⋅ID/I

= f(Tmb); conditions: VGS ≥ 5 V

D 25 ˚C

Fig.4. Transient thermal impedance.

Z

= f(t); parameter D = tp/T

th j-mb

August 1999 3 Rev 1.500

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PHP21N06LT, PHB21N06LT
Logic level FET PHD21N06LT

Drain Current, ID (A)

35

Tj = 25 C

30

25

20

15

10

5

0

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

Drain-Source Voltage, VDS (V)

VGS = 10V

5 V

3.4 V

3.2 V
3 V

2.8 V

2.6 V

2.4 V

Fig.5. Typical output characteristics, Tj = 25 ˚C

ID = f(VDS)

Drain-Source On Resistance, RDS(on) (Ohms)

0.3

0.25

0.2

0.15

0.1

0.05

2.6 V

2.8V

2.4 V
3 V

3.2 V

3.4 V

0

0 5 10 15 20 25 30 35

Drain Current, ID (A)

Tj = 25 C

5 V

VGS = 10V

Fig.6. Typical on-state resistance, Tj = 25 ˚C

R

= f(ID)

DS(ON)

Transconductance, gfs (S)

15

VDS > ID X RDS(ON)

14
13
12
11
10

9
8
7
6
5
4
3
2
1
0

0 2 4 6 8 10 12 14 16 18 20

.

Fig.8. Typical transconductance, Tj = 25 ˚C

Drain current, ID (A)

Tj = 25 C

175 C

.

gfs = f(ID)

Normalised On-state Resistance

2.4

2.2
2

1.8

1.6

1.4

1.2
1

0.8

0.6

0.4

0.2
0

-60 -40 -20 0 20 40 60 80 100 120 140 160 180

.

Fig.9. Normalised drain-source on-state resistance.

Junction temperature, Tj (C)

R

DS(ON)/RDS(ON)25 ˚C

= f(Tj)

Drain current, ID (A)

20

VDS > ID X RDS(ON)

18
16
14
12
10

8
6
4
2
0

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

175 C

Gate-source voltage, VGS (V)

Tj = 25 C

Fig.7. Typical transfer characteristics.

ID = f(VGS)

Threshold Voltage, VGS(TO) (V)

2.25

2

1.75

1.5

1.25

1

0.75

0.5

0.25

0

-60 -40 -20 0 20 40 60 80 100 120 140 160 180
Junction Temperature, Tj (C)

maximum

typical

minimum

Fig.10. Gate threshold voltage.

V

= f(Tj); conditions: ID = 1 mA; VDS = V

GS(TO)

GS

August 1999 4 Rev 1.500