Philips PHB13N40E, PHP13N40E Datasheet

Philips Semiconductors Product specification

PowerMOS transistors PHP13N40E, PHB13N40E, PHW13N40E
Avalanche energy rated

FEATURES SYMBOL QUICK REFERENCE DATA

• Repetitive Avalanche Rated

• Fast switching V

d

= 400 V

DSS

• Stable off-state characteristics

• High thermal cycling performance I

• Low thermal resistance

g

s

R

DS(ON)

D

= 13.7 A

≤ 0.35 Ω

GENERAL DESCRIPTION

N-channel,enhancementmodefield-effect power transistor, intendedforusein off-line switched mode powersupplies,
T.V.andcomputer monitor powersupplies, d.c. to d.c.converters, motor controlcircuitsand general purpose switching
applications.

The PHP13N40E is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHW13N40E is supplied in the SOT429 (TO247) conventional leaded package.
The PHB13N40E is supplied in the SOT404 surface mounting package.

PINNING SOT78 (TO220AB) SOT404 SOT429 (TO247)

PIN DESCRIPTION

1 gate
2 drain

1

tab

tab

3 source

2

tab drain

123

13

2

3

1

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DSS

V

DGR

V

GS

I

D

I

DM

P

D

Tj, T

Drain-source voltage Tj = 25 ˚C to 150˚C - 400 V
Drain-gate voltage Tj = 25 ˚C to 150˚C; RGS = 20 kΩ - 400 V
Gate-source voltage - ± 30 V
Continuous drain current Tmb = 25 ˚C; VGS = 10 V - 13.7 A

Tmb = 100 ˚C; VGS = 10 V - 8.7 A
Pulsed drain current Tmb = 25 ˚C - 55 A
Total dissipation Tmb = 25 ˚C - 156 W
Operating junction and - 55 150 ˚C

stg

storage temperature range

1 It is not possible to make connection to pin 2 of the SOT404 package.

December 1998 1 Rev 1.000

Philips Semiconductors Product specification

PowerMOS transistors PHP13N40E, PHB13N40E, PHW13N40E
Avalanche energy rated

AVALANCHE ENERGY LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

E

AS

E

AR

IAS, I

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

R

th j-mb

R

th j-a

Non-repetitive avalanche Unclamped inductive load, IAS = 13.6 A; - 705 mJ
energy tp = 0.2 ms; Tj prior to avalanche = 25˚C;

VDD ≤ 50 V; RGS = 50 Ω; VGS = 10 V
Repetitive avalanche energy2IAR = 13.7 A; tp = 2.5 µs; Tj prior to - 18 mJ

avalanche = 25˚C; RGS = 50 Ω; VGS = 10 V
Repetitive and non-repetitive - 13.7 A

AR

avalanche current

Thermal resistance junction - - 0.8 K/W
to mounting base
Thermal resistance junction SOT78 package, in free air - 60 - K/W
to ambient SOT429 package, in free air - 45 - K/W

SOT404 package, pcb mounted, minimum - 50 - K/W

footprint

ELECTRICAL CHARACTERISTICS

Tj = 25 ˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(BR)DSS

∆V
∆T

R

DS(ON)

V

GS(TO)

g

fs

I

DSS

I

GSS

Q

g(tot)

Q

gs

Q

gd

t

d(on)

t

r

t

d(off)

t

f

L

d

L

d

L

s

C

iss

C

oss

C

rss

(BR)DSS

j

Drain-source breakdown VGS = 0 V; ID = 0.25 mA 400 - - V
voltage

/ Drain-source breakdown VDS = VGS; ID = 0.25 mA - 0.1 - %/K

voltage temperature
coefficient
Drain-source on resistance VGS = 10 V; ID = 6.5 A - 0.26 0.35 Ω
Gate threshold voltage VDS = VGS; ID = 0.25 mA 2.0 3.0 4.0 V
Forward transconductance VDS = 30 V; ID = 6.5 A 4 7.5 - S
Drain-source leakage current VDS = 400 V; VGS = 0 V - 1 25 µA

VDS = 320 V; VGS = 0 V; Tj = 125 ˚C - 50 500 µA
Gate-source leakage current VGS = ±30 V; VDS = 0 V - 10 200 nA

Total gate charge ID = 13 A; V

= 320 V; VGS = 10 V - 79 100 nC

DD

Gate-source charge - 7.2 12 nC
Gate-drain (Miller) charge - 43 55 nC

Turn-on delay time VDD = 200 V; RD = 15 Ω; - 16 - ns
Turn-on rise time RG = 5.6 Ω -40-ns
Turn-off delay time - 100 - ns
Turn-off fall time - 42 - ns

Internal drain inductance Measured from tab to centre of die - 3.5 - nH
Internal drain inductance Measured from drain lead to centre of die - 4.5 - nH

(SOT78 package only)
Internal source inductance Measured from source lead to source - 7.5 - nH

bond pad
Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 1283 - pF

Output capacitance - 218 - pF
Feedback capacitance - 120 - pF

2 pulse width and repetition rate limited by Tj max.

December 1998 2 Rev 1.000

Philips Semiconductors Product specification

PowerMOS transistors PHP13N40E, PHB13N40E, PHW13N40E
Avalanche energy rated

SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS

Tj = 25 ˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

S

I

SM

V

SD

t

rr

Q

rr

Continuous source current Tmb = 25˚C - - 13.7 A
(body diode)
Pulsed source current (body Tmb = 25˚C - - 55 A
diode)
Diode forward voltage IS = 13 A; VGS = 0 V - - 1.2 V

Reverse recovery time IS = 13 A; VGS = 0 V; dI/dt = 100 A/µs - 420 - ns
Reverse recovery charge - 5.4 - µC

December 1998 3 Rev 1.000

Philips Semiconductors Product specification

PowerMOS transistors PHP13N40E, PHB13N40E, PHW13N40E
Avalanche energy rated

PD%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140

Normalised Power Derating

Tmb / C

Fig.1. Normalised power dissipation.

PD% = 100⋅PD/P

ID%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140

Tmb / C

= f(Tmb)

D 25 ˚C

Normalised Current Derating

Fig.2. Normalised continuous drain current.

ID% = 100⋅ID/I

= f(Tmb); conditions: VGS ≥ 10 V

D 25 ˚C

P

D

PHP13N40E

D = tp/T

tp

T

t

Transient Thermal Impedance, Zth j-a (K/W)

1

D = 0.5

0.2

0.1

0.1

0.05

0.02

0.01

0.001
1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01

Single pulse

pulse width, tp (s)

Fig.4. Transient thermal impedance.

Z

= f(t); parameter D = tp/T

th j-mb

Drain Current, ID (A)

8

Tj = 25 C

7
6
5
4
3
2
1
0

012345

Drain-Source Voltage, VDS (V)

VGS = 10 V

Fig.5. Typical output characteristics

ID = f(VDS); parameter V

PHP13N40E

5 V

4.8 V

4.6 V

4.4 V

4.2 V
4 V

.

GS

Drain-Source On Resistance, RDS(on) (Ohms)

Peak Pulsed Drain Current, IDM (A)

100

RDS(on) = VDS/ ID

10

1

0.1
10 100 1000

Drain-Source Voltage, VDS (V)

d.c.

PHP13N40E

tp = 10 us

100 us

1 ms

10 ms

100 ms

Fig.3. Safe operating area. Tmb = 25 ˚C

ID & IDM = f(VDS); IDM single pulse; parameter t

p

1.4

1.2

1

0.8

0.6

0.4

0.2

0

012345678

4.2V

4 V

Drain Current, ID (A)

4.4V

4.6V

4.8V

Tj = 25 C

5V

VGS = 10 V

PHP13N40E

Fig.6. Typical on-state resistance

R

= f(ID); parameter V

DS(ON)

GS

.

December 1998 4 Rev 1.000

Philips Semiconductors Product specification

PowerMOS transistors PHP13N40E, PHB13N40E, PHW13N40E
Avalanche energy rated

Drain current, ID (A)

20

VDS > ID X RDS(ON)

18
16
14
12
10

8
6
4
2
0

01234567

Gate-source voltage, VGS (V)

150 C

PHP13N40E

Tj = 25 C

Fig.7. Typical transfer characteristics.

ID = f(VGS); parameter T

Transconductance, gfs (S)

12

VDS > ID X RDS(ON)

10

8

6

4

j

PHP13N40E

Tj = 25 C

150 C

VGS(TO) / V

4

3

2

1

0

-60 -40 -20 0 20 40 60 80 100 120 140

max.

typ.

min.

Tj / C

Fig.10. Gate threshold voltage

V

= f(Tj); conditions: ID = 0.25 mA; VDS = V

GS(TO)

1E-01

1E-02

1E-03

1E-04

ID / A

SUB-THRESHOLD CONDUCTION

2 %

typ

.

GS

98 %

2

0

0 5 10 15 20

Drain current, ID (A)

Fig.8. Typical transconductance

gfs = f(ID); parameter T

a

2

1

0

-60 -40 -20 0 20 40 60 80 100 120 140

Normalised RDS(ON) = f(Tj)

Tj / C

.

j

Fig.9. Normalised drain-source on-state resistance.

a = R

DS(ON)/RDS(ON)25 ˚C

= f(Tj); ID = 6.5 A; VGS = 10 V

1E-05

1E-06

0 1 2 3 4

VGS / V

Fig.11. Sub-threshold drain current.

ID = f(V

10000

1000

100

10

0.1 1 10 100

Fig.12. Typical capacitances, C

C = f(VDS); conditions: VGS = 0 V; f = 1 MHz

; conditions: Tj = 25 ˚C; VDS = V

GS)

Capacitances, Ciss, Coss, Crss (pF)

Drain-source voltage, VDS (V)

, C

iss

PHP13N40E

oss

Ciss

Coss
Crss

, C

GS

rss

.

December 1998 5 Rev 1.000

Philips Semiconductors Product specification

PowerMOS transistors PHP13N40E, PHB13N40E, PHW13N40E
Avalanche energy rated

Gate-source voltage, VGS (V)
15
14

ID = 13A

13

Tj = 25 C

12
11
10

9
8
7
6
5
4
3
2
1
0

0 20 40 60 80 100 120

200V

100 V

VDD=320V

Gate charge, QG (nC)

PHP13N40E

Fig.13. Typical turn-on gate-charge characteristics.

V

= f(QG); parameter V

GS

Switching times, td(on), tr, td(off), tf (ns)

450

VDD = 200V

400

RD = 15 Ohms

350
300
250
200
150
100

50

0

0 1020304050

Gate resistance, RG (Ohms)

Fig.14. Typical switching times; t

d(on)

DS

td(off)

, tr, t

PHP13N40E

tf

td(on)

, tf = f(RG)

d(off)

tr

Source-Drain Diode Current, IF (A)

20
18
16
14
12
10

8
6
4
2
0

0 0.2 0.4 0.6 0.8 1 1.2

Drain-Source Voltage, VSDS (V)

150 C

PHP13N40E

Tj = 25 C

Fig.16. Source-Drain diode characteristic.

IF = f(V

Non-repetitive Avalanche current, IAS (A)

100

10

VDS

tp

ID

1
1E-06 1E-05 1E-04 1E-03 1E-02

); parameter T

SDS

Tj prior to avalanche = 25 C

125 C

Avalanche time, tp (s)

j

PHP13N40E

Fig.17. Maximum permissible non-repetitive

avalanche current (IAS) versus avalanche time (tp);

unclamped inductive load

Normalised Drain-source breakdown voltage

1.15

V(BR)DSS @ Tj
V(BR)DSS @ 25 C

1.1

1.05

1

0.95

0.9

0.85

-100 -50 0 50 100 150
Tj, Junction temperature (C)

Fig.15. Normalised drain-source breakdown voltage

V

(BR)DSS/V(BR)DSS 25 ˚C

= f(Tj)

;

Maximum Repetitive Avalanche Current, IAR (A)

100

10

1

0.1
1E-06 1E-05 1E-04 1E-03 1E-02

Tj prior to avalanche = 25 C

125 C

PHP13N40E

Avalanche time, tp (s)

Fig.18. Maximum permissible repetitive avalanche

current (IAR) versus avalanche time (tp)

December 1998 6 Rev 1.000

Philips Semiconductors Product specification

PowerMOS transistors PHP13N40E, PHB13N40E, PHW13N40E
Avalanche energy rated

MECHANICAL DATA

Dimensions in mm
Net Mass: 2 g

10,3
max

1,3

3,7

4,5
max

3,0 max

not tinned

1,3

max

(2x)

123

2,54 2,54

2,8

3,0

13,5

min

0,9 max (3x)

5,9

min

15,8

max

0,6

2,4

Fig.19. SOT78 (TO220AB); pin 2 connected to mounting base.

Notes

1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.

2. Refer to mounting instructions for SOT78 (TO220) envelopes.

3. Epoxy meets UL94 V0 at 1/8".

December 1998 7 Rev 1.000

Philips Semiconductors Product specification

PowerMOS transistors PHP13N40E, PHB13N40E, PHW13N40E
Avalanche energy rated

MECHANICAL DATA

Dimensions in mm
Net Mass: 1.4 g

2.54 (x2)

MOUNTING INSTRUCTIONS

Dimensions in mm

10.3 max

11 max

15.4

0.85 max
(x2)

4.5 max

1.4 max

0.5

Fig.20. SOT404 : centre pin connected to mounting base.

11.5

2.5

9.0

17.5

2.0

3.8

5.08

Fig.21. SOT404 : soldering pattern for surface mounting

.

Notes

1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.

2. Epoxy meets UL94 V0 at 1/8".

December 1998 8 Rev 1.000

Philips Semiconductors Product specification

PowerMOS transistors PHP13N40E, PHB13N40E, PHW13N40E
Avalanche energy rated

MECHANICAL DATA

Dimensions in mm
Net Mass: 5 g

21

max

15.5
min

3.5

4.0
max

2.2 max

3.2 max

16 max

5.3

15.5

max

1

2

5.45

3

1.1

5.45

7.3

0.4

seating

plane

M

5.3 max

1.8
o

2.5

0.9 max

Fig.22. SOT429; pin 2 connected to mounting base.

3.5
max

Notes

1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.

2. Refer to mounting instructions for SOT429 envelope.

3. Epoxy meets UL94 V0 at 1/8".

December 1998 9 Rev 1.000

Philips Semiconductors Product specification

PowerMOS transistors PHP13N40E, PHB13N40E, PHW13N40E
Avalanche energy rated

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

 Philips Electronics N.V. 1998

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.

The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.

December 1998 10 Rev 1.000