Datasheet PHB130N03LT, PHP130N03LT Datasheet (Philips)

Philips Semiconductors Product specification

TrenchMOS transistor PHP130N03LT, PHB130N03LT
Logic level FET

FEATURES SYMBOL QUICK REFERENCE DATA

• ’Trench’ technology V

d

= 30 V

DSS

• Very low on-state resistance

• Fast switching I

= 75 A

D

• Stable off-state characteristics

• High thermal cycling performance R

• Low thermal resistance

g

R

s

≤ 6 mΩ (VGS = 5 V)

DS(ON)

≤ 5 mΩ (VGS = 10 V)

DS(ON)

GENERAL DESCRIPTION

N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology.
Thedevicehasverylowon-stateresistance. Itis intended for use in dc to dc convertersand general purpose switching
applications.

The PHP130N03LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB130N03LT is supplied in the SOT404 surface mounting package.

PINNING SOT78 (TO220AB) SOT404

PIN DESCRIPTION

1 gate
2 drain

1

3 source

tab drain

tab

123

tab

2

13

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DSS

V

DGR

V

GS

I

D

I

DM

P

D

Tj, T

1 It is not possible to make connection to pin 2 of the SOT404 package.

January 1998 1 Rev 1.300

Drain-source voltage Tj = 25 ˚C to 175˚C - 30 V
Drain-gate voltage Tj = 25 ˚C to 175˚C; RGS = 20 kΩ -30V
Gate-source voltage - ± 13 V
Continuous drain current Tmb = 25 ˚C; VGS = 5 V - 75 A

Tmb = 100 ˚C; VGS = 5 V - 75 A
Pulsed drain current Tmb = 25 ˚C - 240 A
Total power dissipation Tmb = 25 ˚C - 187 W
Operating junction and - 55 175 ˚C

stg

storage temperature

Philips Semiconductors Product specification

TrenchMOS transistor PHP130N03LT, PHB130N03LT

Logic level FET

ESD LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

C

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

R

th j-mb

R

th j-a

ELECTRICAL CHARACTERISTICS

Tj= 25˚C unless otherwise specified

Electrostatic discharge Human body model (100 pF, 1.5 kΩ)-2kV
capacitor voltage, all pins

Thermal resistance junction - - 0.8 K/W
to mounting base
Thermal resistance junction SOT78 package, in free air - 60 - K/W
to ambient SOT404 package, pcb mounted, minimum - 50 - K/W

footprint

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(BR)DSS

Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 30 - - V
voltage Tj = -55˚C 27 - - V

V

(BR)GSS

Gate-source breakdown IG = 1 mA 10 - - V
voltage

V

GS(TO)

Gate threshold voltage VDS = VGS; ID = 1 mA 1 1.5 2 V

Tj = 175˚C 0.5 - - V

Tj = -55˚C - - 2.3 V

R

DS(ON)

Drain-source on-state VGS = 5 V; ID = 25 A - 5 6 mΩ
resistance VGS = 10 V; ID = 25 A - 4.5 5 mΩ

VGS = 5 V; ID = 25 A; Tj = 175˚C - - 11 mΩ

g
I

fs

GSS

Forward transconductance VDS = 25 V; ID = 25 A 20 40 - S
Gate-source leakage current VGS = ±5 V; VDS = 0 V; - 0.02 1 µA

Tj = 175˚C - - 10 µA

I

DSS

Zero gate voltage drain VDS = 30 V; VGS = 0 V; - 0.05 10 µA
current Tj = 175˚C - - 500 µA

Q
Q
Q

t
t
t
t

L
L

g(tot)
gs
gd

d on
r
d off
f

d
d

Total gate charge ID = 75 A; V

= 24 V; VGS = 5 V - 92 - nC

DD

Gate-source charge - 10 - nC
Gate-drain (Miller) charge - 36 - nC

Turn-on delay time VDD = 15 V; ID = 25 A; - 45 60 ns
Turn-on rise time VGS = 5 V; RG = 5 Ω - 120 170 ns
Turn-off delay time Resistive load - 225 300 ns
Turn-off fall time - 100 135 ns

Internal drain inductance Measured tab to centre of die - 3.5 - nH
Internal drain inductance Measured from drain lead to centre of die - 4.5 - nH

(SOT78 package only)

L

s

Internal source inductance Measured from source lead to source - 7.5 - nH

bond pad

C

iss

C

oss

C

rss

Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 5000 - pF
Output capacitance - 1150 - pF
Feedback capacitance - 500 - pF

January 1998 2 Rev 1.300

Philips Semiconductors Product specification

TrenchMOS transistor PHP130N03LT, PHB130N03LT

Logic level FET

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tj = 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

S

I

SM

V

SD

t

rr

Q

rr

AVALANCHE LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

W

DSS

Continuous source current - - 75 A
(body diode)
Pulsed source current (body - - 240 A
diode)
Diode forward voltage IF = 25 A; VGS = 0 V - 0.85 1.2 V

IF = 75 A; VGS = 0 V - 1.0 ­Reverse recovery time IF = 75 A; -dIF/dt = 100 A/µs; - 100 - ns

Reverse recovery charge VGS = -10 V; VR = 25 V - 0.6 - µC

Drain-source non-repetitive ID = 75 A; VDD ≤ 15 V; - 500 mJ
unclamped inductive turn-off VGS = 5 V; RGS = 50 Ω; Tmb = 25 ˚C
energy

PD%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140 160 180

Normalised Power Derating

Tmb / C

Fig.1. Normalised power dissipation.

PD% = 100⋅PD/P

D 25 ˚C

= f(Tmb)

ID (A) Current Derating

140
120
100

80
60
40
20

0

0 20 40 60 80 100 120 140 160 180

Limited by package

Tmb / C

Fig.2. Normalised continuous drain current.

ID% = 100⋅ID/I

= f(Tmb); conditions: VGS ≥ 5 V

D 25 ˚C

January 1998 3 Rev 1.300

Philips Semiconductors Product specification

TrenchMOS transistor PHP130N03LT, PHB130N03LT
Logic level FET

Drain current, ID (A)

1000

RDS(ON) = VDS / ID

100

DC

10

1

1 10 100

Drain-source voltage, VDS (V)

7506-30

tp = 10 us

100 us
1 ms

10 ms
100 ms

Fig.3. Safe operating area. Tmb = 25 ˚C

ID & IDM = f(VDS); IDM single pulse; parameter t

Zth / (K/W)

1E+00

0.5

1E-01

1E-02

0.2

0.1

0.05

0.02

t

p

P

D

0

D =

T

RDS(ON) / mOhm

10

8

6

4

2

0

0 20406080100

3

ID / A

Fig.6. Typical on-state resistance, Tj = 25 ˚C

R

p

ID / A

100

80

60

t

p

T

t

40

20

= f(ID); parameter V

DS(ON)

Tj / C = 175

25

9506-30

3.5
4

5
6

.

GS

9506-30

1E-03

1E-07 1E-05 1E-03 1E-01 1E+01

t / s

Fig.4. Transient thermal impedance.

Z

= f(t); parameter D = tp/T

th j-mb

ID / A

100

3.56

80

60

40

20

5

VGS / V =

0

0246810

VDS / V

Fig.5. Typical output characteristics, Tj = 25 ˚C

ID = f(VDS); parameter V

BUK9506-30

3

2.8

2.6

2.4

2.2

.

GS

0

012345

VGS / V

Fig.7. Typical transfer characteristics.

ID = f(VGS) ; conditions: VDS = 25 V; parameter T

gfs / S

100

80

60

40

20

0

0 20406080100

Tj / C = 25

175

ID / A

9506-30

Fig.8. Typical transconductance, Tj = 25 ˚C

j

.

gfs = f(ID); conditions: VDS = 25 V

January 1998 4 Rev 1.300

Philips Semiconductors Product specification

TrenchMOS transistor PHP130N03LT, PHB130N03LT
Logic level FET

a

2

1.5

1

0.5

0

-100 0 100 200
Tj / C

30V TrenchMOS

15050-50

Fig.9. Normalised drain-source on-state resistance.

a = R

DS(ON)/RDS(ON)25 ˚C

VGS(TO) / V

2.5

max.

2

typ.

1.5

min.

1

= f(Tj); ID = 25 A; VGS = 5 V

BUK959-60

C / pF

10000

1000

100

0.1 1 10 100

Fig.12. Typical capacitances, C

VDS / V

, C

iss

oss

C = f(VDS); conditions: VGS = 0 V; f = 1 MHz

VGS / V

5

4

3

2

VDS / V = 6 24

9506-30

Ciss

Coss

Crss

, C

rss

9506-30

.

0.5

0

-100 -50 0 50 100 150 200
Tj / C

Fig.10. Gate threshold voltage.

V

= f(Tj); conditions: ID = 1 mA; VDS = V

GS(TO)

1E-01

1E-02

1E-03

1E-04

1E-05

1E-05

0 0.5 1 1.5 2 2.5 3

2% typ

Sub-Threshold Conduction

98%

Fig.11. Sub-threshold drain current.

ID = f(V

; conditions: Tj = 25 ˚C; VDS = V

GS)

GS

GS

1

0

0 20406080100

QG / nC

Fig.13. Typical turn-on gate-charge characteristics.

V

= f(QG); conditions: ID = 75 A; parameter V

GS

IF / A

100

80

60

40

20

0

0 0.5 1 1.5 2

Tj / C = 175 25

VSDS / V

DS

9506-30

Fig.14. Typical reverse diode current.

IF = f(V

); conditions: V

SDS

= 0 V; parameter T

GS

j

January 1998 5 Rev 1.300

Philips Semiconductors Product specification

TrenchMOS transistor PHP130N03LT, PHB130N03LT
Logic level FET

WDSS%

120
110
100

90
80
70
60
50
40
30
20
10

0

20 40 60 80 100 120 140 160 180

Tmb / C

Fig.15. Normalised avalanche energy rating.

W

% = f(Tmb); conditions: ID = 75 A

DSS

L

VDS

VGS

0

RGS

T.U.T.

Fig.16. Avalanche energy test circuit.

W

= 0.5 ⋅ LI

DSS

2

D

⋅BV

DSS

/(BV

R 01

shunt

DSS−VDD

VDD

+

-

-ID/100

)

January 1998 6 Rev 1.300