Datasheet PHP125N06T Datasheet (Philips)

Philips Semiconductors Product specification

TrenchMOS transistor PHP125N06T
Standard level FET

GENERAL DESCRIPTION QUICK REFERENCE DATA

N-channel enhancement mode SYMBOL PARAMETER MAX. UNIT
standard level field-effect power
transistor in a plastic envelope using V
’trench’ technology. The device I
featuresverylowon-state resistance P
and has integral zener diodes giving T
ESD protection up to 2kV. It is R

DS

D

tot
j

DS(ON)

intended for use in DC-DC resistance VGS = 10 V
converters and general purpose
switching applications.

PINNING - TO220AB PIN CONFIGURATION SYMBOL

Drain-source voltage 55 V
Drain current (DC)

1

75 A
Total power dissipation 250 W
Junction temperature 175 ˚C
Drain-source on-state 8 mΩ

PIN DESCRIPTION

tab

d

1 gate
2 drain
3 source

tab drain

123

g

s

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V
V
±V
I

D

I

D

I

DM

P
T

DS
DGR

tot

stg

GS

, T

j

Drain-source voltage - - 55 V
Drain-gate voltage RGS = 20 kΩ -55V
Gate-source voltage - - 20 V
Drain current (DC)
Drain current (DC)

1
1

Tmb = 25 ˚C - 75 A

Tmb = 100 ˚C - 75 A
Drain current (pulse peak value) Tmb = 25 ˚C - 240 A
Total power dissipation Tmb = 25 ˚C - 250 W
Storage & operating temperature - - 55 175 ˚C

ESD LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

C

Electrostatic discharge capacitor Human body model - 2 kV
voltage, all pins (100 pF, 1.5 kΩ)

1 Current limited by package to 75A from a theoretical value of 125A.

December 1997 1 Rev 1.100

Philips Semiconductors Product specification

TrenchMOS transistor PHP125N06T

Standard level FET

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT

R

th j-mb

R

th j-a

STATIC CHARACTERISTICS

Tj= 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(BR)DSS

V

GS(TO)

I

DSS

I

GSS

±V

(BR)GSS

R

DS(ON)

Thermal resistance junction to - - 0.6 K/W
mounting base
Thermal resistance junction to in free air 60 - K/W
ambient

Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 55 - - V
voltage Tj = -55˚C 50 - - V
Gate threshold voltage VDS = VGS; ID = 1 mA 2 3.0 4.0 V

Tj = 175˚C 1 - - V

Tj = -55˚C - - 4.4 V

Zero gate voltage drain current VDS = 55 V; VGS = 0 V; - 0.05 10 µA

Tj = 175˚C - - 500 µA

Gate source leakage current VGS = ±10 V; VDS = 0 V - 0.02 1 µA

Tj = 175˚C - - 20 µA
Gate-source breakdown IG = ±1 mA; 16 - - V
voltage
Drain-source on-state VGS = 10 V; ID = 25 A - 6.5 8 mΩ
resistance Tj = 175˚C - - 17 mΩ

DYNAMIC CHARACTERISTICS

Tmb = 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

g
Q

Q
Q

C
C
C

t
t
t
t

L
L
L

fs

g(tot)
gs
gd

iss
oss
rss

d on
r
d off
f

d

d

s

Forward transconductance VDS = 25 V; ID = 25 A 10 45 - S
Total gate charge ID = 50 A; V

= 44 V; VGS = 10 V - 86 - nC

DD

Gate-source charge - 21 - nC
Gate-drain (Miller) charge - 34 - nC

Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 3600 4500 pF
Output capacitance - 830 1000 pF
Feedback capacitance - 320 440 pF

Turn-on delay time VDD = 30 V; ID = 25 A; - 27 40 ns
Turn-on rise time VGS = 10 V; RG = 10 Ω - 70 105 ns
Turn-off delay time Resistive load - 100 140 ns
Turn-off fall time - 50 70 ns

Internal drain inductance Measured from contact screw on - 3.5 - nH

tab to centre of die

Internal drain inductance Measured from drain lead 6 mm - 4.5 - nH

from package to centre of die

Internal source inductance Measured from source lead 6 mm - 7.5 - nH

from package to source bond pad

December 1997 2 Rev 1.100

Philips Semiconductors Product specification

TrenchMOS transistor PHP125N06T

Standard level FET

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tj = 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

DR

I

DRM

V

SD

t

rr

Q

rr

AVALANCHE LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

W

DSS

Continuous reverse drain - - 75 A
current
Pulsed reverse drain current - - 240 A
Diode forward voltage IF = 25 A; VGS = 0 V - 0.85 1.2 V

IF = 75 A; VGS = 0 V - 1.0 - V

Reverse recovery time IF = 75 A; -dIF/dt = 100 A/µs; - 65 - ns
Reverse recovery charge VGS = -10 V; VR = 30 V - 0.18 - µC

Drain-source non-repetitive ID = 75 A; VDD ≤ 25 V; - - 500 mJ
unclamped inductive turn-off VGS = 10 V; RGS = 50 Ω; Tmb = 25 ˚C
energy

December 1997 3 Rev 1.100

Philips Semiconductors Product specification

TrenchMOS transistor PHP125N06T
Standard level FET

PD%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140 160 180

Normalised Power Derating

Tmb / C

Fig.1. Normalised power dissipation.

PD% = 100⋅PD/P

ID (A)

150

125

100

75

50

25

0

0 20 40 60 80 100 120 140 160 180

Tmb / C

= f(Tmb)

D 25 ˚C

Current Derating

Limited by package

Fig.2. Normalised continuous drain current.

ID% = 100⋅ID/I

= f(Tmb); conditions: VGS ≥ 5 V

D 25 ˚C

Zth / (K/W)

1E+00

0.5

1E-01

1E-02

1E-03

0.2

0.1

0.05

t

p

t / s

P

D

0.02

0

1E-07 1E-05 1E-03 1E-01 1E+01

t

p

D =

T

t

T

Fig.4. Transient thermal impedance.

Z

= f(t); parameter D = tp/T

th j-mb

100

ID/A

80

60

40

20

0

6.516
10

0246810

VDS/V

VGS/V = 6.0

5.5

5.0

4.5

4.0

Fig.5. Typical output characteristics, Tj = 25 ˚C

ID = f(VDS); parameter V

GS

.

1000

ID / A

RDS(ON) = VDS/ID

100

10

1

1

DC

10

VDS / V

BUKX508-55

tp = 10 us
100 us

1 ms
10 ms

100 ms

100

Fig.3. Safe operating area. Tmb = 25 ˚C

ID & IDM = f(VDS); IDM single pulse; parameter t

RDS(ON)/mOhm

15

VGS/V=

10

5

0

0 20406080100120

ID/A

65.5

Fig.6. Typical on-state resistance, Tj = 25 ˚C

R

p

= f(ID); parameter V

DS(ON)

BUK7508-55

6.5
7

8

10

.

GS

December 1997 4 Rev 1.100

Philips Semiconductors Product specification

TrenchMOS transistor PHP125N06T
Standard level FET

100

ID/A

80

60

40

Tj/C = 175 25

20

0

01234567

VGS/V

Fig.7. Typical transfer characteristics.

ID = f(VGS) ; conditions: VDS = 25 V; parameter T

70

gfs/S

60

50

40

30

20

10

VGS(TO) / V

5

max.

4

typ.

3

min.

2

1

0

-100 -50 0 50 100 150 200
Tj / C

BUK759-60

Fig.10. Gate threshold voltage.

V

j

1E-01

1E-02

1E-03

1E-04

1E-05

= f(Tj); conditions: ID = 1 mA; VDS = V

GS(TO)

Sub-Threshold Conduction

2%

typ

GS

98%

0

0 20406080100

Fig.8. Typical transconductance, Tj = 25 ˚C

ID/A

.

gfs = f(ID); conditions: VDS = 25 V

a

2.5

2

1.5

1

0.5

-100 -50 0 50 100 150 200

BUK959-60

Rds(on) normlised to 25degC

Tmb / degC

Fig.9. Normalised drain-source on-state resistance.

a = R

DS(ON)/RDS(ON)25 ˚C

= f(Tj); ID = 25 A; VGS = 5 V

1E-06

012345

Fig.11. Sub-threshold drain current.

ID = f(V

7

6

5

4

3

Thousands pF

2

1

0

0.01 0.1 1 10 100

Fig.12. Typical capacitances, C

; conditions: Tj = 25 ˚C; VDS = V

GS)

VDS/V

, C

iss

oss

, C

GS

rss

Ciss

Coss
Crss

.

C = f(VDS); conditions: VGS = 0 V; f = 1 MHz

December 1997 5 Rev 1.100

Philips Semiconductors Product specification

TrenchMOS transistor PHP125N06T
Standard level FET

12

VGS/V

10

8

6

4

2

0

0 102030405060708090100

VDS = 14V

QG/nC

BUK7508-55

VDS = 44V

Fig.13. Typical turn-on gate-charge characteristics.

V

= f(QG); conditions: ID = 50 A; parameter V

GS

100

IF/A

80

60

Tj/C = 175 25

40

DS

WDSS%

120
110
100

90
80
70
60
50
40
30
20
10

0

20 40 60 80 100 120 140 160 180

Tmb / C

Fig.15. Normalised avalanche energy rating.

W

% = f(Tmb); conditions: ID = 75 A

DSS

+

L

VDS

VGS

0

T.U.T.

-

VDD

-ID/100

20

0

0 0.2 0.4 0.6 0.8 1 1.2

VSDS/V

Fig.14. Typical reverse diode current.

IF = f(V

); conditions: V

SDS

= 0 V; parameter T

GS

RGS

R 01

shunt

Fig.16. Avalanche energy test circuit.

RG

2

D

⋅BV

DSS

/(BV

RD

DSS−VDD

VDS

T.U.T.

)

VDD

+

-

W

= 0.5 ⋅ LI

j

VGS

0

DSS

Fig.17. Switching test circuit.

December 1997 6 Rev 1.100

Philips Semiconductors Product specification

TrenchMOS transistor PHP125N06T

Standard level FET

MECHANICAL DATA

Dimensions in mm
Net Mass: 2 g

10,3
max

1,3

3,7

4,5
max

3,0 max

not tinned

1,3

max

(2x)

123

2,54 2,54

2,8

3,0

13,5

min

0,9 max (3x)

5,9

min

15,8

max

0,6

2,4

Fig.18. SOT78 (TO220AB); pin 2 connected to mounting base.

Notes

1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.

2. Refer to mounting instructions for SOT78 (TO220) envelopes.

3. Epoxy meets UL94 V0 at 1/8".

December 1997 7 Rev 1.100

Philips Semiconductors Product specification

TrenchMOS transistor PHP125N06T

Standard level FET

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

 Philips Electronics N.V. 1997

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.

The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.

December 1997 8 Rev 1.100