Philips PHN70308 Datasheet
Philips Semiconductors Product specification
N-channel enhancement mode PHN70308
TrenchMOS transistor array
FEATURES SYMBOL QUICK REFERENCE DATA
• 30 mΩ isolation transistor
• 80 mΩ spindle transistors V
• TrenchMOS technology
• Logic level compatible I
isolation FET
G4
S4
= 25 V
DS
= 5 A
D
• Surface mount package
D4
G7
S7
D1
G6
S6
D2 D3
G5
(VGS = 10 V; isolation FET)
S5
R
DS(ON)
R
DS(ON)
≤ 30 mΩ
≤ 80 mΩ
(VGS = 10 V; spindle FETs)
G1 G2
S1
S2
G3
S3
GENERAL DESCRIPTION
This product is used to drive high performance, three phase brushless d.c. motors in computer disk drives.
The PHN70308 contains seven, n-channel enhancement mode trenchMOS transistors in a surface mounting plastic
package. Six of the transistors can be configured as a three phase bridge to drive the spindle of a disk drive motor.
The remaining transistor delivers power to the three phase bridge during normal operation. In the event of a power
failure occurring whilst the motor is still spinning, this transistor isolates the computer power supply from the back
emf generated by the motor.
The PHN70308 is supplied in the surface mounting SOT341-1 (SSOP28) package.
PINNING SOT341-1 (SSOP28)
PIN DESCRIPTION PIN DESCRIPTION
1,3 drain 1 16,17 source 4
2 source 1 18 gate 4
4 gate 1 20 gate 5
5,7 drain 2 21 source 5
6 source 2 23 gate 6
8 gate 2 24 source 6
9,11 drain 3 26 gate 7
10 source 3 27 source 7
12 gate 3 13-15,19,22,25,28 drain 4
28
1
Top view
15
14
May 1999 1 Rev 1.000
Philips Semiconductors Product specification
N-channel enhancement mode PHN70308
TrenchMOS transistor array
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
P
tot
T
, T
stg
j
Drain-source voltage Tj = 25 ˚C to 150˚C - 25 V
Drain-gate voltage RGS = 20 kΩ -25V
Gate-source voltage - ± 20 V
Peak drain current per device Tsp = 50 ˚C
1
(continuous operation) spindle FETs; δ = 33.3% - 5 A
Isolation FET (dc) - 5 A
Peak current per device (pulse spindle FETs - 20 A
peak value) isolation FET - 20 A
Power dissipation per device
2
Tsp = 50 ˚C
spindle FETs; δ = 33.3% - 1.13 W
isolation FET (dc) - 1.275 W
Total power dissipation in normal Tsp = 50 ˚C - 8 W
operation
2
spindle FETs; δ = 33.3%
isolation FET (dc)
Storage & operating temperature - 55 150 ˚C
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
R
th j-sp
R
th j-a
1 Tsp is the temperature at the soldering point of the drain leads.
2 In normal operation, the isolation FET conducts continuously whilst each of the spindle FETs conducts for 33.3%
of the time. The dissipation in the isolation transistor is given by:-
P
= I2xR
isolation
The dissipation in each of the spindle transistors is given by:-
P
= 0.333xI2xR
spindle
The total dissipation under these conditions is given by:-
P
= P
tot
isolation
With the motor being driven at 5 A and assuming Tj = 150˚C, the total dissipation is:-
P
= 25x0.03x1.7 +0.333x25x0.08x1.7x6 = 8W
tot
Switching losses are assumed to be negligible.
Thermal resistance junction to isolation FET 20 - K/W
solder point spindle FET 43 - K/W
Thermal resistance junction to device soldered to FR4 board,
ambient minimum footprint.
isolation FET 85 - K/W
spindle FET 100 - K/W
DS(ON)(isolation FET)
DS(ON)(spindleFET)
+6xP
spindle
May 1999 2 Rev 1.000
Philips Semiconductors Product specification
N-channel enhancement mode PHN70308
TrenchMOS transistor array
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
(BR)DSS
V
GS(TO)
R
DS(ON)
R
DS(ON)
R
DS(ON)
I
GSS
I
DSS
Q
g(tot)
Q
gs
Q
gd
t
on
t
off
C
iss
C
oss
C
rss
Drain-source breakdown VGS = 0 V; ID = 10 µA25--V
voltage
Gate threshold voltage VDS = VGS; ID = 1 mA 1.0 1.5 - V
Drain-source on-state VGS = 10 V; ID = 4 A
resistance spindle FET - 60 80 mΩ
isolation FET - 27 30 mΩ
Drain-source on-state VGS = 4.5 V; ID = 2 A
resistance spindle FET - 95 150 mΩ
isolation FET - 38 60 mΩ
Drain-source on-state VGS = 10 V; ID = 4 A; Tj = 150˚C
resistance spindle FET - 102 136 mΩ
isolation FET - 46 51 mΩ
Gate source leakage current VGS = ±20 V; VDS = 0 V - 10 100 nA
Zero gate voltage drain VDS = 20 V; VGS = 0 V; - 10 100 nA
current Tj = 150˚C - 0.1 0.5 mA
Total gate charge ID = 1 A; V
= 20 V; VGS = 10 V
DD
spindle FET - 5.4 - nC
isolation FET - 17.6 - nC
Gate-source charge spindle FET - 0.4 - nC
isolation FET - 1.4 - nC
Gate-drain (Miller) charge spindle FET - 1.6 - nC
isolation FET - 5.7 - nC
Turn-on time VDD = 20 V; ID = 1 A; VGS = 10 V; RG = 6 Ω;
resistive load
spindle FET - 5.5 10 ns
isolation FET - 11 20 ns
Turn-off time spindle FET - 16 25 ns
isolation FET - 45 60 ns
Input capacitance VGS = 0 V; VDS = 20 V; f = 1 MHz
spindle FET - 180 - pF
isolation FET - 546 - pF
Output capacitance spindle FET - 70 - pF
isolation FET - 311 - pF
Feedback capacitance spindle FET - 36 - pF
isolation FET - 133 - pF
May 1999 3 Rev 1.000
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