Philips PHN405 Datasheet

DISCRETE SEMICONDUCTORS

DATA SH EET

PHN405

4 N-channel 60 mΩ FET array enhancement mode MOS transistors

Product speciﬁcation Supersedes data of 1997 Jun 19 File under Discrete Semiconductors, SC13

1998 Mar 17

Philips Semiconductors Product speciﬁcation

4 N-channel 60 mΩ FET array enhancement mode MOS transistors

FEATURES

• High-speed switching

• No secondary breakdown

• Very low on-state resistance

• Current monitoring.

APPLICATIONS

• Motor and actuator driver

• Power management

• Synchronized rectification.

DESCRIPTION

Four enhancement mode MOS transistors in a 16-pin plastic SOT338-1 (SSOP16) package. Two transistors feature current monitoring (sense FETs).

PINNING - SOT338-1 (SSOP16)

PIN SYMBOL DESCRIPTION

1 and 4 d

2s 3g

5 and 8 d

6s 7g 9g

10 s

11 and 15 d

12 m 13 g 14 s 16 m

1 1 1 2 2 2 3 3 3

3 4 4

4

drain 1 source 1 gate 1 drain 2 source 2 gate 2 gate 3 source 3 drain 3 current monitor 3 gate 4 source 4 current monitor 4

PHN405

CAUTION

The device is supplied in an antistatic package. The gate-source input must be protected against static discharge during transport or handling.

handbook, full pagewidth

16

1

9

8

d

3

g

4

m

4

g

1

s

4

d

1

s

1

g

3

m

3

s

3

d

2

g

2

MAM276

s

2

Fig.1 Simplified outline and symbol.

1998 Mar 17 2

Philips Semiconductors Product speciﬁcation

4 N-channel 60 mΩ FET array

PHN405

enhancement mode MOS transistors

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DS

V

GS

V

GSth

I

D

R

DSon

P

tot

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

Per FET

V

DS

V

GS

I

D

I

DM

P

tot

T

stg

T

j

Current monitor

I

M

I

MM

Source-drain diode

I

S

I

SM

drain-source voltage (DC) − 30 V gate-source voltage (DC) −±20 V gate-source threshold voltage ID= 1 mA; VDS=V

GS

1 2.8 V drain current (DC) Ts=80°C − 3.7 A drain-source on-state resistance ID= 2 A; VGS=10V − 60 mΩ total power dissipation Ts=80°C − 1.4 W

drain-source voltage (DC) − 30 V gate-source voltage (DC) −±20 V drain current (DC) Ts=80°C; note 1 − 3.7 A peak drain current note 2 − 14.8 A total power dissipation Ts=80°C; note 3 − 1.4 W

T

=80°C; note 4 − 1.25 W

s

T

=80°C; note 5 − 1.09 W

s

storage temperature −55 +150 °C operating junction temperature −55 +150 °C

monitor current (DC) Ts=80°C − 50 mA peak monitor current note 2 − 220 mA

source current (DC) Ts=80°C − 1.4 A peak source current note 2 − 5.6 A

Notes

1. T

is the temperature at the soldering point of the drain lead.

s

2. Pulse width and duty cycle limited by maximum junction temperature.

3. When only one FET dissipates.

4. When either FETs 1 and 3 or 2 and 4 dissipate an equal amount of power.

5. When all four FETs dissipate an equal amount of power.

1998 Mar 17 3

Philips Semiconductors Product speciﬁcation

4 N-channel 60 mΩ FET array enhancement mode MOS transistors

150

MDA804

Ts (°C)

200

handbook, halfpage

2

P

tot

(W)

1.6

1.2

0.8

0.4

0

0 50 100

2

10

handbook, halfpage

I

D

(A)

10

1

10

2

10

1

10

PHN405

MDA805

(1)

t

P

t

p

T

p

=

δ

T

DC

t

1

10

V

DS

tp =

1 ms 10 ms

100 ms

1 s

(V)

2

10

δ =0.01; Ts=80°C. (1) R

Fig.2 Power derating curve.

DSon

limitation.

Fig.3 SOAR.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

Per FET

R

th j-s

thermal resistance from junction to soldering point note 1 50 K/W

note 2 56 K/W note 3 64 K/W

Notes

1. When only one FET dissipates.

2. When either FETs 1 and 3 or 2 and 4 dissipate an equal amount of power.

3. When all four FETs dissipate an equal amount of power.

1998 Mar 17 4