Philips PHN210 Datasheet
Philips Semiconductors Product specification
Dual N-channel enhancement mode PHN210
TrenchMOS
FEATURES SYMBOL QUICK REFERENCE DATA
• Dual device VDS = 30 V
• Low threshold voltage
• Fast switching ID = 3.4 A
• Logic level compatible
• Surface mount package R
GENERAL DESCRIPTION PINNING SOT96-1
Dual N-channel enhancement PIN DESCRIPTION
mode field-effect transistor in a
plastic envelope using ’trench’ 1 source 1
technology.
Applications:-
• Motor and relay drivers 3 source 2
• d.c. to d.c. converters
• Logic level translator 4 gate 2
TM
transistor
d1
s1
2 gate 1
d1 d2g2d2
s2
g1
≤ 100 mΩ (VGS = 10 V)
DS(ON)
R
≤ 200 mΩ (VGS = 4.5 V)
DS(ON)
pin 1 index
1234
5678
The PHN210 is supplied in the 5,6 drain 2
SOT96-1 (SO8) surface mounting
package. 7,8 drain 1
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DS
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
P
tot
T
, T
stg
j
Repetitive peak drain-source Tj = 25 ˚C to 150˚C - 30 V
voltage
Continuous drain-source voltage - 30 V
Drain-gate voltage RGS = 20 kΩ -30V
Gate-source voltage - ± 20 V
Drain current per MOSFET
1
Ta = 25 ˚C - 3.4 A
Ta = 70 ˚C - 2.8 A
Drain current per MOSFET (both Ta = 25 ˚C - 2.4 A
MOSFETs conducting)
1
Ta = 70 ˚C - 1.9 A
Drain current per MOSFET (pulse Ta = 25 ˚C - 14 A
peak value)
Total power dissipation (either or Ta = 25 ˚C - 2 W
both MOSFETs conducting)
1
Ta = 70 ˚C - 1.3 W
Storage & operating temperature - 65 150 ˚C
1 Surface mounted on FR4 board, t ≤ 10 sec
February 1999 1 Rev 1.000
Philips Semiconductors Product specification
Dual N-channel enhancement mode PHN210
TrenchMOS
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
R
th j-a
R
th j-a
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
E
AS
I
AS
ELECTRICAL CHARACTERISTICS
Tj= 25˚C, per MOSFET unless otherwise specified
TM
transistor
Thermal resistance junction Surface mounted, FR4 board, t ≤ 10 sec - 62.5 K/W
to ambient
Thermal resistance junction Surface mounted, FR4 board 150 - K/W
to ambient
Non-repetitive avalanche Unclamped inductive load, IAS = 3.4 A; - 13 mJ
energy (per MOSFET) tp = 0.2 ms; Tj prior to avalanche = 25˚C;
VDD ≤ 15 V; RGS = 50 Ω; VGS = 10 V
Non-repetitive avalanche - 3.4 A
current (per MOSFET)
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
(BR)DSS
Drain-source breakdown VGS = 0 V; ID = 10 µA; 30 - - V
voltage Tj = -55˚C 27 - - V
V
GS(TO)
Gate threshold voltage VDS = VGS; ID = 1 mA 1 2 2.8 V
Tj = 150˚C 0.4 - - V
Tj = -55˚C - 3.2 V
R
DS(ON)
Drain-source on-state VGS = 10 V; ID = 2.2 A - 80 100 mΩ
resistance VGS = 4.5 V; ID = 1 A - 120 200 mΩ
VGS = 10 V; ID = 2.2 A; Tj = 150˚C - - 170 mΩ
g
fs
I
D(ON)
Forward transconductance VDS = 20 V; ID = 2.2 A 2 4.5 - S
On-state drain current VGS = 10 V; VDS = 1 V; 3.5 - - A
VGS = 4.5 V; VDS = 5 V 2 - - A
I
DSS
Zero gate voltage drain VDS = 24 V; VGS = 0 V; - 10 100 nA
current VDS = 24 V; VGS = 0 V; Tj = 150˚C - 0.6 10 µA
I
Q
Q
Q
t
t
t
t
L
L
GSS
g(tot)
gs
gd
d on
r
d off
f
d
s
Gate source leakage current VGS = ±20 V; VDS = 0 V - 10 100 nA
Total gate charge ID = 2.3 A; V
= 15 V; VGS = 10 V - 6 - nC
DD
Gate-source charge - 0.7 - nC
Gate-drain (Miller) charge - 0.7 - nC
Turn-on delay time VDD = 20 V; RD = 18 Ω;-6-ns
Turn-on rise time VGS = 10 V; RG = 6 Ω -8-ns
Turn-off delay time Resistive load - 21 - ns
Turn-off fall time - 15 - ns
Internal drain inductance Measured from drain lead to centre of die - 2.5 - nH
Internal source inductance Measured from source lead to source - 5 - nH
bond pad
C
iss
C
oss
C
rss
Input capacitance VGS = 0 V; VDS = 20 V; f = 1 MHz - 250 - pF
Output capacitance - 88 - pF
Feedback capacitance - 54 - pF
February 1999 2 Rev 1.000
Philips Semiconductors Product specification
Dual N-channel enhancement mode PHN210
TrenchMOS
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C, per MOSFET unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
I
S
I
SM
V
SD
t
rr
Q
rr
PD%
120
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140
Fig.1. Normalised power dissipation.
TM
transistor
Continuous source diode Ta = 25 ˚C - - 2.2 A
current (per MOSFET)
Pulsed source diode current - - 14 A
(per MOSFET)
Diode forward voltage IF = 1.25 A; VGS = 0 V - 0.82 1.2 V
Reverse recovery time IF = 1.25 A; -dIF/dt = 100 A/µs; - 69 - ns
Reverse recovery charge VGS = 0 V; VR = 25 V - 55 - nC
Normalised Power Derating
PHN210
tp = 10 us
100 us
1 ms
10 ms
100 ms
10 s
Tamb / C
Peak Pulsed Drain Current, IDM (A)
100
RDS(on) = VDS/ ID
10
1
0.1
0.01
0.1 1 10 100
Drain-Source Voltage, VDS (V)
Fig.3. Safe operating area. Ta = 25 ˚C
PD% = 100⋅PD/P
D 25 ˚C
= f(Ta)
ID & IDM = f(VDS); IDM single pulse; parameter t
p
ID%
120
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140
Ambient temperature, Tamb (C)
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/I
= f(Ta); conditions: VGS ≥ 10 V
D 25 ˚C
Normalised Current Derating
tp
PHN210
D = tp/T
T
Peak Pulsed Drain Current, IDM (A)
100
D = 0.5
0.2
10
0.1
0.05
0.02
1
0.1
single pulse
0.01
1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01
Pulse width, tp (s)
P
D
Fig.4. Transient thermal impedance.
Z
= f(t); parameter D = tp/T
th j-a
February 1999 3 Rev 1.000
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