Philips PHN205 Datasheet
DISCRETE SEMICONDUCTORS
DATA SH EET
PHN205
Dual N-channel enhancement
mode
MOS transistor
Product specification
Supersedes data of 1997 Jun 18
File under Discrete Semiconductors, SC13b
1997 Oct 22
Philips Semiconductors Product specification
Dual N-channel enhancement mode
MOS transistor
FEATURES
• High-speed switching
• No secondary breakdown
• Very low on-state resistance.
APPLICATIONS
• Motor and actuator driver
• Power management
• Synchronized rectification.
DESCRIPTION
Two N-channel enhancement mode MOS transistors in an
8-pin plastic SOT96-1 (SO8) package.
CAUTION
The device is supplied in an antistatic package.
The gate-source input must be protected against static
discharge during transport or handling.
PINNING - SOT96-1 (SO8)
PIN SYMBOL DESCRIPTION
1s
2g
3s
4g
5d
6d
7d
8d
handbook, halfpage
58
1
4
MAM117
1
1
2
2
2
2
1
1
source 1
gate 1
source 2
gate 2
drain 2
drain 2
drain 1
drain 1
d
d
1
1
gs
1
PHN205
d
2
2
1
d
2
gs
2
Fig.1 Simplified outline and symbol.
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
Per N-channel
V
DS
V
SD
V
GS
V
GSth
I
D
R
DSon
P
tot
drain-source voltage (DC) − 30 V
source-drain diode forward voltage IS= 1.25 A − 1V
gate-source voltage (DC) −±20 V
gate-source threshold voltage ID= 1 mA; VDS=V
1 2.8 V
GS
drain current (DC) Ts=80°C − 6.4 A
drain-source on-state resistance ID= 3.2 A; VGS=10V − 50 mΩ
total power dissipation Ts=80°C − 3.5 W
1997 Oct 22 2
Philips Semiconductors Product specification
Dual N-channel enhancement mode
PHN205
MOS transistor
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
Per N-channel
V
DS
V
GS
I
D
I
DM
P
tot
T
stg
T
j
Source-drain diode
I
S
I
SM
drain-source voltage (DC) − 30 V
gate-source voltage (DC) −±20 V
drain current (DC) Ts=80°C; note 1 − 6.4 A
peak drain current note 2 − 25 A
total power dissipation Ts=80°C; note 3 − 3.5 W
T
=25°C; note 4 − 2.6 W
amb
T
=25°C; note 5 − 1.1 W
amb
=25°C; note 6 − 1.5 W
T
amb
storage temperature −65 +150 °C
operating junction temperature −65 +150 °C
source current (DC) Ts=80°C − 3.5 A
peak pulsed source current note 2 − 14 A
Notes
is the temperature at the soldering point of the drain lead.
1. T
s
2. Pulse width and duty cycle limited by maximum junction temperature.
3. Maximum permissible dissipation per MOS transistor. Both devices may be loaded up to 3.5 W at the same time.
4. Maximum permissible dissipation per MOS transistor. Device mounted on printed-circuit board with an R
th a-tp
(ambient to tie-point) of 27.5 K/W.
5. Maximum permissible dissipation per MOS transistor. Device mounted on printed-circuit board with an R
th a-tp
(ambient to tie-point) of 90 K/W.
6. Maximum permissible dissipation if only one MOS transistor dissipates. Device mounted on printed-circuit board with
an R
(ambient to tie-point) of 90 K/W.
th a-tp
THERMAL CHARACTERISTICS
SYMBOL PARAMETER VALUE UNIT
R
th j-s
thermal resistance from junction to soldering point 20 K/W
1997 Oct 22 3
Philips Semiconductors Product specification
Dual N-channel enhancement mode
MOS transistor
handbook, halfpage
8
P
tot
(W)
6
4
2
0
0 50 100 150
MGG340
Ts (°C)
2
10
handbook, halfpage
I
D
(A)
10
P
1
−1
10
−1
10
PHN205
MGG341
tp =
(1)
t
p
δ =
T
t
p
T
t
11010
10 µs
100 µs
1 ms
10 ms
100 ms
DC
V
DS
(V)
2
Fig.2 Power derating curve.
δ =0.01; Ts=80°C.
(1) R
DSon
limitation.
Fig.3 SOAR.
1997 Oct 22 4
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