Philips PHN203 Datasheet

Philips Semiconductors Product specification

Dual N-channel enhancement mode PHN203
TrenchMOS

FEATURES SYMBOL QUICK REFERENCE DATA

• Dual device VDS = 25 V

• Low threshold voltage

• Fast switching ID = 6.3 A

• Logic level compatible

• Surface mount package R

GENERAL DESCRIPTION PINNING SOT96-1

N-channel enhancement mode PIN DESCRIPTION
field-effect power transistor in a
plastic envelope using ’trench’ 1 source 1
technology. The device has very
low on-state resistance. It is 2 gate 1
intended for use in dc to dc
converters and general purpose 3 source 2
switching applications.

The PHN203 is supplied in the
SOT96-1 (SO8) surface mounting 5,6 drain 2
package.

TM

transistor

d1

s1

4 gate 2

7,8 drain 1

d1 d2g2d2

s2

g1

≤ 30 mΩ (VGS = 10 V)

DS(ON)

R

≤ 55 mΩ (VGS = 4.5 V)

DS(ON)

pin 1 index

1234

5678

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DS

V

DS

V

DGR

V

GS

I

D

I

D

I

DM

P

tot

T

, T

stg

j

Repetitive peak drain-source Tj = 25 ˚C to 150˚C - 25 V
voltage
Continuous drain-source voltage - 25 V
Drain-gate voltage RGS = 20 kΩ -25V
Gate-source voltage - ± 20 V
Drain current per MOSFET

1

Ta = 25 ˚C - 6.3 A

Ta = 70 ˚C - 5 A
Drain current per MOSFET (both Ta = 25 ˚C - 4.4 A
MOSFETs conducting)

1

Ta = 70 ˚C - 3.5 A
Drain current per MOSFET (pulse Ta = 25 ˚C - 25 A
peak value)
Total power dissipation (either or Ta = 25 ˚C - 2 W
both MOSFETs conducting)

1

Ta = 70 ˚C - 1.3 W
Storage & operating temperature - 55 150 ˚C

1 Surface mounted on FR4 board, t ≤ 10 sec

January 1999 1 Rev 1.000

Philips Semiconductors Product specification

Dual N-channel enhancement mode PHN203

TrenchMOS

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT

R

th j-a

R

th j-a

AVALANCHE ENERGY LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

E

AS

I

AS

ELECTRICAL CHARACTERISTICS

Tj= 25˚C, per MOSFET unless otherwise specified

TM

transistor

Thermal resistance junction Surface mounted on FR4 board, t ≤ 10 - 62.5 K/W
to ambient sec; either or both MOSFETs conducting
Thermal resistance junction Surface mounted on FR4 board; either or 150 - K/W
to ambient both MOSFETs conducting

Non-repetitive avalanche Unclamped inductive load, IAS = 6.3 A; - 20 mJ
energy (per MOSFET) tp = 0.2 ms; Tj prior to avalanche = 25˚C;

VDD ≤ 15 V; RGS = 50 Ω; VGS = 10 V
Non-repetitive avalanche - 6.3 A
current (per MOSFET)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(BR)DSS

Drain-source breakdown VGS = 0 V; ID = 10 µA; 25 - - V
voltage Tj = -55˚C 22.5 - - V

V

GS(TO)

Gate threshold voltage VDS = VGS; ID = 1 mA 1 2 2.8 V

Tj = 150˚C 0.4 - - V

Tj = -55˚C - 3.2 V

R

DS(ON)

Drain-source on-state VGS = 10 V; ID = 4 A - 27 30 mΩ
resistance VGS = 4.5 V; ID = 2 A - 40 55 mΩ

VGS = 10 V; ID = 4 A; Tj = 150˚C - 43 51 mΩ

g
I

fs

DSS

Forward transconductance VDS = 20 V; ID = 4 A 5 9.7 - S
Zero gate voltage drain VDS = 20 V; VGS = 0 V; - 60 100 nA
current VDS = 20 V; VGS = 0 V; Tj = 150˚C - 0.1 10 µA

I
Q

Q
Q

t
t
t
t

L
L

GSS

g(tot)
gs
gd

d on
r
d off
f

d
s

Gate source leakage current VGS = ±20 V; VDS = 0 V - 10 100 nA
Total gate charge ID = 4 A; V

= 20 V; VGS = 10 V - 20 - nC

DD

Gate-source charge - 1.9 - nC
Gate-drain (Miller) charge - 6.1 - nC

Turn-on delay time VDD = 20 V; RD = 18 Ω;-8-ns
Turn-on rise time VGS = 10 V; RG = 6 Ω -11-ns
Turn-off delay time Resistive load - 31 - ns
Turn-off fall time - 17 - ns

Internal drain inductance Measured from drain lead to centre of die - 2.5 - nH
Internal source inductance Measured from source lead to source - 5 - nH

bond pad

C

iss

C

oss

C

rss

Input capacitance VGS = 0 V; VDS = 20 V; f = 1 MHz - 611 - pF
Output capacitance - 260 - pF
Feedback capacitance - 137 - pF

January 1999 2 Rev 1.000

Philips Semiconductors Product specification

Dual N-channel enhancement mode PHN203

TrenchMOS

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tj = 25˚C, per MOSFET unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

S

I

SM

V

SD

t

rr

Q

rr

Normalised Power Dissipation, PD (%)

120

100

80

60

40

20

0

0 25 50 75 100 125 150

Fig.1. Normalised power dissipation.

TM

transistor

Continuous source diode Ta = 25 ˚C - - 2.85 A
current (per MOSFET)
Pulsed source diode current - - 25 A
(per MOSFET)
Diode forward voltage IF = 1.25 A; VGS = 0 V - 0.75 1 V

Reverse recovery time IF = 1.25 A; -dIF/dt = 100 A/µs; - 35 - ns
Reverse recovery charge VGS = 0 V; VR = 25 V - 24 - nC

PHN203

tp = 10 us

100 us
1 ms
10 ms
100 ms

10 s

Ambient Temperature, Ta (C)

Peak Pulsed Drain Current, IDM (A)

100

RDS(on) = VDS/ ID

10

1

0.1

0.01

0.1 1 10 100
Drain-Source Voltage, VDS (V)

Fig.3. Safe operating area. Ta = 25 ˚C

PD% = 100⋅PD/P

D 25 ˚C

= f(Ta)

ID & IDM = f(VDS); IDM single pulse; parameter t

p

tp

PHN203

D = tp/T

T

Normalised Drain Current, ID (%)

120

100

80

60

40

20

0

0 25 50 75 100 125 150

Ambient Temperature, Ta (C)

Fig.2. Normalised continuous drain current.

ID% = 100⋅ID/I

= f(Ta); conditions: VGS ≥ 4.5 V

D 25 ˚C

Peak Pulsed Drain Current, IDM (A)

100

D = 0.5

0.2

10

0.1

0.05

0.02

1

single pulse

0.1

0.01
1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01

Pulse width, tp (s)

P

D

Fig.4. Transient thermal impedance;

Z

= f(t); parameter D = tp/T

th j-a

January 1999 3 Rev 1.000